CN1744314B - 具有层积结构的半导体装置及其制造方法 - Google Patents

具有层积结构的半导体装置及其制造方法 Download PDF

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CN1744314B
CN1744314B CN2005100980208A CN200510098020A CN1744314B CN 1744314 B CN1744314 B CN 1744314B CN 2005100980208 A CN2005100980208 A CN 2005100980208A CN 200510098020 A CN200510098020 A CN 200510098020A CN 1744314 B CN1744314 B CN 1744314B
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semiconductor device
conductor layer
semiconductor chip
distribution conductor
wiring pattern
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CN1744314A (zh
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今冈俊一
臼井良辅
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

一种具有层积结构的半导体装置及其制造方法。其提供一种使半导体装置小型化的方法。半导体装置(100)包括：基体部件(20)，半导体芯片(10a)、10b)，片状部件(12a、12b)，绝缘基体部件(30)，配线图案(34)，通路塞(32)，外部引出电极(36)，凹部(40)，树脂(50)。绝缘基体部件(30)具有多层结构，是层积多个绝缘膜而形成的。半导体芯片(10a)及片状部件(12a)安装在基体部件(20)，埋入绝缘基体部件(30)中。半导体装置(100)的表面形成有凹部(40)，其深度直至某配线导体层，在凹部(40)安装有半导体芯片(10b)、片状部件(12b)。

Description

具有层积结构的半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
随着移动电话及PDA(Personal Digital Assitance)、数码照相机等便携式电子设备的高功能化的加速，为了使这种产品被市场接受，必须实现小型、轻量化，因此，要求高集成系统LSI。另一方面，对这些电子设备要求更容易使用且便利，且要求用于设备的LSI高功能化、高性能化。因此，随着LSI芯片的高集成化，在要求其I/O数增大的同时，强烈要求封装自身的小型化，为了使它们同时实现，强烈要求开发适于半导体部件的高密度衬底安装的半导体封装。对应这种要求，开发了各种被称作CSP(芯片尺寸封装，Chip Size Package)的封装技术。
作为这种封装的例子公知的有BGA(焊球阵列Ball Grid Array)。BGA是将半导体芯片安装在封装用衬底之上并将其树脂模制后，在相反侧的面上作为外部端子面状形成焊球。在BGA中，安装区域以面实现，故比较容易使封装小型化。另外，电路衬底侧也不需要窄间距对应，也不需要高精度的安装技术，故当使用BGA时，即使封装成本多少增加一些，总安装成本仍可降低。
在这种封装中，密封半导体芯片使用了例如传递模、注射模、罐封或浸渍等(例如参照专利文献1)。
另外，为了实现更高精度、高功能、薄形化的LSI，还公开了如下技术，其在基体衬底部的上部，利用薄膜技术或厚膜技术，构成含有由介由介质绝缘层自基体衬底侧接受电源或信号的供给的电阻部、电容器部或图案配线部构成的无源元件的层(例如参照专利文献2)。
专利文献1：特开平8-162486号公报
专利文献2：特开2002-94247号公报
发明内容
本发明与上述现有技术具有共同的课题，但利用与这些技术不同的装置解决上述课题，其目的在于提供一种使半导体装置小型化的技术。
本发明第一方面的半导体装置包括：积层衬底，其反复层积绝缘层和配线导体层而构成；凹部，其形成于层积衬底一侧面侧的绝缘层上；电路元件，其埋入与形成有凹部的绝缘层不同的绝缘层中。凹部的底部到达配线导体层。
根据该方面，通过在半导体装置的绝缘层设置凹部可追加部件安装面，可实现更高密度的部件安装。电路元件是指半导体芯片及电阻、电容器等电路部件。
绝缘层可以有机物为主要成分构成。以有机物为主要成分是指也可以为提高强度及导热性而混入玻璃纤维等无机物。
可以在凹部安装电路元件。通过在凹部安装电路元件可实现高密度安装。另外，相对于埋入绝缘层的电路元件组装后不能变更，在将片状电阻及片状电容器安装在凹部时，组装后可变更电路常数，因此，可实现电路特性的提高以及成品率的提高。并且，在安装了半导体芯片时，可通过微调调节形成于半导体芯片上的电阻及电容器的电阻值、电容值。
埋入绝缘层的电路元件利用通路塞与配线导体层上的配线图案电连接，安装在凹部的电路元件也可以利用焊料或引线与配线导体层上的配线图案电连接。
凹部的特征可以是以该配线导体层的深度形成，以可自外部微调配线导体层上的配线图案。通过由凹部微调配线图案可在组装后进行电路特性的调节，因此可实现电路特性的提高及成品率的提高。
凹部可以由树脂密封。通过在安装于凹部的电路元件的调节、配线图案的微调结束后，利用模制树脂等密封凹部，可保护这些电路元件。
本发明的另一方面也提供一种半导体装置。该装置包括：层积衬底，其层积绝缘层和配线导体层而构成；多个凹部，形成于层积衬底一侧面侧的绝缘层上；电路元件，其埋入与形成有凹部的绝缘层不同的绝缘层。多个凹部的底部分别到达某一配线导体层。
通过根据安装于凹部的电路元件的高度形成不同深度的凹部，可实现恰当的高密度安装。另外形成于不同配线导体层的配线图案的微调也可以分别进行。
本发明的再一方面也提供一种半导体装置，该装置包括：层积衬底，其由多个绝缘层和配线导体层构成；多个电路元件，其埋入绝缘层。埋入多个电路元件的绝缘层其内部具有配线导体层，利用多个电路元件的间隙部形成配线图案。
根据该方面，通过有效利用半导体芯片及片状部件周边的空间可实现高密度配线。
本发明的又一方面也提供一种半导体装置。该装置包括：基体部件；层积衬底，其由层积于基体部件上的多个绝缘层和配线导体层构成；多个电路元件，其埋入层积衬底中和基体部件邻接的绝缘层。埋入多个电路元件的绝缘层其内部具有配线导体层，利用多个电路元件的间隙部形成配线图案。
根据该方面，通过有效利用半导体芯片及片状部件周边的空间可实现高密度配线。
本发明的还一方面提供一种半导体装置的制造方法。该制造方法包括：将多个电路元件安装在基体部件上的工序；在多个电路元件的间隙部形成厚度比该电路元件小的绝缘层的工序；在绝缘层上形成配线图案的工序。
本发明的下一方面也提供一种半导体装置的制造方法。该制造方法包括：将多个电路元件安装在基体部件上的工序；将在与多个电路元件的间隙部对应的部位预先形成开口部的第一绝缘膜压装在基体部件上的工序；在开口部形成比第一绝缘膜薄的第二绝缘膜的工序；在第二绝缘膜上形成配线图案的工序。
本发明的再下一方面也提供一种半导体装置的制造方法。该制造方法包括：将多个电路元件安装在基体部件上的工序；将第一绝缘膜自多个电路元件之上压装在基体部件上的工序；在第一绝缘膜的电路元件的间隙部形成开口部的工序；在开口部形成比第一绝缘膜薄的第二绝缘膜的工序；在第二绝缘膜上形成配线图案的工序。
根据这些方面的半导体装置的制造方法，可在多个电路元件的间隙部恰当地形成配线图案。
当然，上述结构要素的任意组合、再配置等也均有效，且它们均包括在本发明的范围中。
并且，上述叙述并非记载本发明的所有必要技术特征，本发明也可以是上述特征的其他组合。
附图说明
图1是实施例1的半导体装置的剖面图；
图2A～图2I是表示图1所示的半导体装置的制造工序的工序剖面图；
图3是实施例2的半导体装置的剖面图；
图4A～图4H是表示图3所示的半导体装置的制造工序的一部分的工序剖面图；
图5A～图5C是表示图3所示的半导体装置的制造工序的一部分的工序剖面图；
图6A～图6F是表示图3所示的半导体装置的制造工序的一部分的工序剖面图；
具体实施方式
下面参照附图说明实施例。另外，它们只是一例，并不限定本发明，另外，在多个附图中，同样的结构要素采用同一符号。
下面以实施例为基础说明本发明。这些并不限定本发明，只不过是发明的例示，另外，记载于实施例中的所有特征及它们的组合并不一定都是本发明必须的。
实施例1
图1是本发明实施例1的半导体装置100的剖面图。在下面的图中，同一结构要素使用同一符号，并适当省略说明。
半导体装置100包括：基体部件20，半导体芯片10a、10b，片状部件12a、12b，绝缘基体部件30，配线图案34，通路塞32，外部引出电极36，凹部40，树脂50。图1中，为了便于理解，设设有基体部件20的面为下方向，设有凹部40的面为上方向。
基体部件20上形成有绝缘基体部件30，绝缘基体部件30内部埋入半导体芯片10a、10b和片状部件12a、12b，通过利用配线图案34及通路塞34相互连接形成电子电路。
绝缘基体部件30具有多层结构，是层积多个绝缘层30a～30c而形成的。这些绝缘层可以由同一材料构成，也可以由分别不同的材料构成。在绝缘层30a～30c之间设有配线导体层，形成配线图案34。配线图案34可以作为连接各元件间的配线，也可以作为电感器或电容器形成。
半导体芯片10a、10b是例如集成了晶体管、二极管及无源元件的IC芯片等，是形成于硅或硅锗、砷化镓等半导体上的集成电路。片状部件12a、12b具体地说是电容器、电感器、电阻器等。半导体芯片10a及片状部件12a安装在基体部件20上，埋入绝缘层30a。
通路塞32用于电连接不同配线导体层的配线图案34。且埋入绝缘层30a的半导体芯片10a、片状部件12a利用该通路塞32与配线图案34电连接。
在绝缘基体部件30的上面形成有凹部40。该凹部40的底部为某一配线导体层，当自上方观察半导体装置100时，底部露出配线图案34。半导体芯片10b及片状部件12b相对于该露出的配线图案34，装片接合或与其引线接合，或利用焊料安装在其上，分别和配线图案34物理连接且电连接。凹部40由树脂50密封。
外部引出电极36设于半导体装置100的上面，作为自外部接受电源供给或进行信号的输入输出的I/O端子起作用。外部引出电极36也可以设于半导体装置100的下面。这种情况下，只要在基体部件20设置通路塞，在下面引出信号线即可。
根据本实施例的半导体装置100，通过在半导体装置100的表面形成凹部，可追加各种部件的安装面，可实现更高密度的部件安装。
安装在该凹部40的半导体芯片10b只要是在由树脂50进行的密封工序之前，就可进行形成于内部的电阻、电容器的微调。因此，在半导体装置100组装后，也可以进行电路特性的调节，可提高成品率。
在将片状电阻及片状电容器等片状部件12b安装在凹部40的情况下，只要是在由树脂50进行的密封工序之前，就可通过更换片状部件12b变更电路常数，可提高电路特性，改善成品率等。
另外，在形成于绝缘基体部件30内的配线导体层上的配线图案34自凹部40露出的情况下，也可通过微调该配线图案变更电路常数。
自半导体芯片产生的热量的一部分经外部引出电极36向外部散热。因此，在如本实施例这样将凹部40形成于与形成有外部引出电极36的面同一面上的情况下，通过将发热多的半导体芯片安装在该凹部，使半导体芯片和外部电极的距离接近，故有利于散热。该效果在绝缘层使用导热率低的材料时尤其显著。
下面说明本实施例的半导体装置100的制造方法。图2A～图2I是表示图1的半导体装置100的制造工序的工序剖面图。
首先，如图2A所示，进行将多个半导体芯片10a及片状部件12a等电路元件固定在基体部件20上的装片接合工序。在此，基体部件20可以是具有粘接性并可将半导体芯片10a及片状部件12a固定在表面的带状基体部件。基体部件20的材料也可采用树脂薄膜、铝板等导热性材料。还可采用后述的环氧树脂、BT树脂等蜜胺衍生物、液晶聚合物、PPE树脂、聚酰亚胺树脂、氟树脂、酚醛树脂、聚酰胺双马来酰亚胺等有机物。
在本实施例中，基体部件20也可以使用可伸缩的材料。这种材料例如可使用PET薄膜。或者基体部件20也可以使用UV光反应性薄膜。UV光反应性薄膜例如是切断半导体(芯片)时作为支承体使用的粘接带，通过照射紫外线可改变粘接力型的粘接带市场有售。
在基体部件20使用可伸缩的材料的情况下，要在将基体部件20沿图中横向拉伸后，将多个半导体芯片10a及片状部件12a固定在基体部件20上。
然后，如图2B所示，将在绝缘树脂膜122上粘贴有导电膜120的带导电膜绝缘树脂膜124粘贴在基体部件20上，通过真空加压压装基体部件20和带导电膜绝缘树脂膜124。带导电膜绝缘树脂膜124例如为带铜箔树脂膜。
其结果，半导体芯片10a及片状部件12a被按压在绝缘树脂膜122内。导电膜120形成配线导体层，在之后的工序中形成配线图案。
在本实施例中，在将固定有半导体芯片10a及片状部件12a的基体部件20拉伸的状态下，将半导体芯片10a及片状部件12a压入绝缘树脂膜122内时，在将半导体芯片10a及片状部件12a压入绝缘树脂膜122内时，元件间的间隔增大，容易在元件间压入绝缘树脂膜122。因此，可使半导体芯片10a及片状部件12a和绝缘树脂膜122的密接性良好。
相反，在使基体部件20收缩的状态下将半导体芯片10a及片状部件12a压入绝缘树脂膜122内时，由于元件间的间隔狭窄，故可进行高密度的元件配置。
即使在多个半导体芯片10a及片状部件12a产生台阶的情况下，由于绝缘树脂膜进入半导体芯片10a及片状部件12a上，故也可保持从基体部件20至导电膜120的厚度均匀。由此，可提高半导体装置100的尺寸精度。
导电膜120例如是压延铜箔等压延金属。绝缘树脂膜122只要是可加热软化的材料则可使用任何材料，例如可使用环氧树脂、BT树脂等蜜胺衍生物、液晶聚合物、PPE树脂、聚酰亚胺树脂、氟树脂、酚醛树脂、聚酰胺双马来酰亚胺等有机物。通过使用这样的材料，可提高电路装置的刚性，可提高电路装置的稳定性。
作为环氧树脂，可以举出蜜胺、蜜胺氰尿酸酯、羟甲基化蜜胺、(异)氰尿酸、蜜白胺、蜜勒胺、蜜弄、丁二酰鸟粪胺、硫酸蜜胺、硫酸乙酰鸟粪胺、硫酸蜜白胺、硫酸脒基蜜胺、蜜胺树脂、BT树脂、氰尿酸、异氰尿酸、异氰尿酸衍生物、蜜胺异氰尿酸、苯并鸟粪胺、乙酰鸟粪胺等蜜胺衍生物、胍类化合物等。
作为液晶聚合物，可以举出芳香族类液晶聚酯、聚酰亚胺、聚酯酰胺以及，包含这些的树脂组合物。其中，耐热性、加工性及吸湿性平衡优良的液晶聚酯或含有液晶聚酯的组合物是优选的。
作为液晶聚酯，例如可以举出(1)芳香族二羧酸和芳香族二醇与芳香族羟基羧酸反应得到的液晶聚酯；(2)使不同种芳香族羟基羧酸组合反应得到的液晶聚酯；(3)芳香族二羧酸和芳香族二醇反应得到的液晶聚酯；(4)聚对苯二甲酸乙二醇酯等聚酯与芳香族羟基羧酸反应得到的液晶聚酯；等。还有，可以使用这些酯的衍生物来代替这些芳香族二羧酸、芳香族二醇及芳香族羟基羧酸。另外，这些芳香族二羧酸、芳香族二醇及芳香族羟基羧酸的芳香族部分也可用卤原子、烷基、芳基等取代后使用。
另外，绝缘树脂膜122可包括填充物或纤维等填充材料。填充物例如可使用粒子状或纤维状SiO2或SiN。通过在绝缘树脂膜122中包含填充物或纤维，可在加热绝缘树脂膜122、热压装半导体芯片10a及片状部件12a之后，将绝缘树脂膜122冷却到例如室温时，降低绝缘树脂膜122的翘曲，还会使导热性提高。由此，可提高半导体芯片10a及片状部件12a和绝缘树脂膜122的密接性。另外，在绝缘树脂膜122含有纤维的情况下，可提高绝缘树脂膜122的刚性，使操作容易。基于这种观点，当使用芳酰胺无纺布作为构成绝缘树脂膜122的材料时，由于树脂的流动性高于纤维，故可使加工性能良好。
带导电膜绝缘树脂膜124可使用在薄膜状绝缘树脂膜122上附着有导电膜120的材料。带导电膜绝缘树脂膜124也可通过在导电膜120上涂敷构成绝缘树脂膜122的树脂组成物并使其干燥来形成。在本实施例中，树脂组成物在不违反本发明目的的范围内可包含硬化剂、硬化促进剂及其他成分。带导电膜绝缘树脂膜124在绝缘树脂膜122B级化(表示一次硬化、半硬化或临时硬化的状态)的状态下配置在基体部件20上。
这样，可提高绝缘树脂膜122和半导体芯片10a及片状部件12a的密接性。然后，根据构成绝缘树脂膜122的树脂的种类加热绝缘树脂膜122，并在真空下或减压状态下压装带导电膜绝缘树脂膜124和半导体芯片10a及片状部件12a。另外，在其他例子中，将薄膜状绝缘树脂膜122在B级化后的状态下配置在基体部件20上，然后，在其上配置导电膜120，将绝缘树脂膜122与半导体芯片10a及片状部件12a热压装，此时，通过将导电膜120热压装在绝缘树脂膜122上，也可以形成带导电膜绝缘树脂膜124。
然后，如图2C所示，进行利用激光直射法(穿孔校准)或湿式铜蚀刻加工导电膜120形成配线的配线构图工序，形成配线图案34。
其后，如图2D所示，进行组合二氧化碳激光、YAG激光、干式蚀刻在绝缘树脂膜122上形成通路孔(通孔)的通路孔形成工序。
接着，如图2E所示，进行通过对应高纵横尺寸比的无电解镀铜、电解镀铜形成导电膜，同时在通孔内填埋导电性材料并形成通路塞32的镀敷工序。
更详细地说，通路塞32可如下形成。组合二氧化碳激光、YAG激光、干式蚀刻等在绝缘层上形成通孔128。然后，在通孔128内利用无电解镀铜在整个面上形成0.5～1μm左右的薄膜，然后，利用电解镀铜形成约20μm左右的膜。无电解镀铜用催化剂通常多使用钯，为了将无电解镀敷催化剂附着在挠性的绝缘基体部件上，可通过将钯以络合物状态含在水溶液中，并浸渍挠性绝缘基体部件，使在其表面上附着钯络合物，并直接用还原剂还原成金属钯，从而形成用于在挠性绝缘基体部件表面上开始镀敷的核。
也可以在通路塞32内适当埋入充填材料。充填材料可使用绝缘性材料或导电性材料等各种材料。另外，也可以利用镀敷等将铜作为充填材料埋入。
然后，反复进行依次层积带导电膜绝缘树脂膜124，在导电膜120上形成配线图案34，并由通路塞32连接的工序，来形成层积了绝缘层30a～30e的绝缘基体部件30(图2F)。
之后，如图2G所示，在绝缘基体部件30的上面设置凹部40。凹部40除可用钻机械加工而成外，还可通过激光加工或蚀刻或它们的组合来形成。凹部40的深度设定为直至某一配线导体层为止，使形成于该配线导体层的配线图案34b露出。
然后，在凹部40内部安装半导体芯片10b、片状部件12b。半导体芯片10b利用银膏等进行装片，利用金线等通过引线接合，和配线图案34b物理性、电气性连接。片状部件12b利用焊料和配线图案34b物理性、电气性连接。
然后，形成未图示的外部引出电极，并根据需要进行检查工序。若该检查结果为未能得到所希望的特性，则可以进行半导体芯片10b的微调或片状部件12b的变更等。
然后，在凹部40罐封树脂50，密封半导体芯片10b及片状部件12b。
通过以上的工序可制造实施例1的半导体装置100。
实施例2
下面以与上述半导体装置100的不同点为中心说明实施例2的半导体装置200。图3是实施例2的半导体装置200的剖面图。
半导体装置200包括基体部件20、半导体芯片10a、片状部件12a、绝缘基体部件30、配线图案34、通路塞32、外部引出电极36。图3中，为了便于说明，也将基体部件20定为下方向，将设有外部引出电极36的面定为上方向。
绝缘基体部件30具有多层结构，其是层积多层绝缘层30a～30e形成的。在与基体部件20邻接的绝缘层30a埋入半导体芯片10a、片状部件12a，利用通路塞32及配线图案34连接各部件构成电路，这一点和图1的半导体装置100相同。
在图3的半导体装置200中，在半导体芯片10a、片状部件12a的间隙部即周边的空间设有配线图案34c。
通常的半导体芯片10a的厚度为100～300μm，电阻及电容器等片状部件12a的高度在所谓的0603尺寸为300μm，在1005尺寸为500μm左右。在本实施例中，在未安装半导体芯片10a等的间隙部也形成配线导体层，进行更高密度的配线。
根据该半导体装置200，通过有效利用半导体芯片和片状部件周边的空间，可实现高密度配线，可提高配线的回绕自由度。
下面就实施例2的半导体装置200的制造方法进行说明。图4A～图4H为表示图3所示的半导体装置200的制造工序的一部分的工序剖面图。
图4A表示在基体部件20装片接合半导体芯片10a、片状部件12a并埋入绝缘树脂膜122的状态。至此可由图2A～图2B所示的工序进行。在绝缘树脂膜122上是否粘贴导电膜120均可以。
然后，如图4B所示，在绝缘树脂膜122形成开口部150。开口部150的形成是对半导体芯片10a、片状部件12a的间隙部即对要形成图3的配线图案34c的部位进行。开口部150利用例如钻孔、激光加工或蚀刻以及它们的组合形成。
在图4C中，在由上述工序形成于绝缘树脂膜122的开口部150形成绝缘层130a。该绝缘层130a可由树脂罐封等形成。罐封的树脂与绝缘树脂膜122同样可使用可加热软化的环氧树脂、BT树脂等蜜胺衍生物、液晶聚合物、PPE树脂、聚酰亚胺树脂、氟树脂、酚醛树脂、聚酰胺双马来酰亚胺等有机物。
然后，如图4D所示，在绝缘层130a上形成配线图案34c。配线图案34c可组合例如无电解镀敷法及蚀刻而形成。同样，如图4E所示，通过再次树脂罐封层积绝缘层130b，并在其上形成配线图案34c。
接着，如图4F所示，在绝缘层130b上利用激光照射等形成通路孔，利用通路塞32，将配线图案34c之间电连接(图4G)。
然后，通过利用树脂罐封形成绝缘层130c，在绝缘树脂膜122中形成多个配线导体层。以后的工序可和图2同样进行。另外，绝缘层130c也可以在图4G所示的状态中，在半导体装置200整体上自上部压绝缘树脂膜而形成。
利用以上的制造方法可在多个半导体芯片10a或片状部件12a之间的间隙部形成配线图案，可有效利用半导体装置200内的空间，实现更高密度配线。
图4A～图4B所示的工序也可以由图5A～图5C所示的工序进行。图5A中，将半导体芯片10a、片状部件12a装片接合在基体部件20上。接着，预先在绝缘树脂膜122上设置开口部150，如图5B、图5C所示，将该绝缘树脂膜122粘贴在基体部20上，通过真空加压，将半导体芯片10a及片状部件12a压入绝缘树脂膜122内。
绝缘树脂膜122的开口部150设于要形成配线图案34c的部位。
另外，利用图6A～图6F所示的工序也可以形成配线图案34c。
首先，如图6A所示，将半导体芯片10a及片状部件12a装片接合在基体部件20上。然后，如图6B所示，对要形成配线图案34c的部位局部进行树脂罐封，形成绝缘层130a。接着如图6C～E所示，形成配线图案34c、绝缘层130b，形成通路塞32。
接着，如图6F所示，将绝缘树脂膜122粘贴在基体部件20上，进行真空加压，将半导体芯片10a及片状部件12a压入绝缘树脂膜122内。
如上所述，也可在多个半导体芯片10a或片状部件12a之间的间隙部形成配线图案34c，可实现有效利用半导体装置200内的空间的高密度配线。
本发明不限于上述各实施例，根据本领域人员的知识，可进行各种设计变更等变形，进行了这种变形的实施方式也包含在本发明范围内。
在实施例中，就半导体芯片及片状部件混载的半导体装置进行了说明，但不限于此，可应用于各种安装有半导体芯片的半导体装置。
在实施例1中，在一个凹部40中既可安装半导体芯片或片状部件等单一的电路元件，也可以安装多个电路元件。这些可根据凹部的尺寸适当决定。
另外，在上述实施例中，是在基体部件20上安装半导体芯片10及片状部件12，但作为具有铜等形成的配线图案而不使用用于支承半导体电路元件的芯件的无芯SIP(系统封装)周知的ISB(Intcgrated System in Board：注册商标)也可应用本发明。
以上使用数个用语说明了本发明的恰当实施例，但这些叙述只是用于说明的一例，在所附权利要求意图范围内的置换及变形当然也包括在内。

Claims (4)

1.一种电路装置，其特征在于，包括：
基体部件，其固定有高度不同的多个第一电路元件；
第一绝缘膜，通过该第一绝缘膜将所述多个第一电路元件埋入在所述基体部件上；
第一配线导体层，其配置在所述第一绝缘膜上，由导电性膜构成，自所述基体部件的厚度均一，并且所述第一配线导体层通过通路塞对所述多个第一电路元件进行电连接；
多层构造体，其在所述第一绝缘膜以及所述第一配线导体层上设有多个层积体，所述各个层积体由膜厚比所述第一绝缘膜薄的第二绝缘膜以及第二配线导体层构成；
凹部，其设置在所述多层构造体中，到达所述第一配线导体层或所述第二配线导体层；
第二电路元件，其安装在所述凹部中，与所述第一配线导体层或所述第二配线导体层连接。
2.如权利要求1所述的电路装置，其特征在于，所述凹部通过树脂覆盖所述第二电路元件而被密封。
3.如权利要求1所述的电路装置，其特征在于，所述第一电路元件以及所述第二电路元件为半导体芯片、片状电阻、片状电容器以及片状电感器中的任一种。
4.如权利要求1所述的电路装置，其特征在于，所述第一绝缘膜或所述第二绝缘膜以有机物为主要成分而构成。
CN2005100980208A 2004-09-01 2005-09-01 具有层积结构的半导体装置及其制造方法 Expired - Fee Related CN1744314B (zh)

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