JP2006060177A - pn接合を有する化合物半導体エピタキシャル基板の製造方法 - Google Patents
pn接合を有する化合物半導体エピタキシャル基板の製造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 64
- 150000001875 compounds Chemical class 0.000 title claims abstract description 60
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 51
- 230000006866 deterioration Effects 0.000 abstract description 16
- 239000010410 layer Substances 0.000 description 26
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 15
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- 239000013078 crystal Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 230000007774 longterm Effects 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008014 freezing Effects 0.000 description 1
- 238000007710 freezing Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02579—P-type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
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Abstract
選択成長工程を含むエピタキシャル成長法によるpn接合を有する化合物半導体エピタキシャル基板の製造方法であって、特性劣化の少ない化合物半導体素子を与える化合物半導体エピタキシャル基板の製造方法を提供する。
【解決手段】
pn接合を有する化合物半導体エピタキシャル基板を選択成長法により製造する方法であって、残留歪の平均値が1.0×10-5以下である元基板を用いることを特徴とする化合物半導体エピタキシャル基板の製造方法。元基板が、VGF法またはVB法により製造された元基板である前記記載の製造方法。
【選択図】 図6
Description
|Sr−St|=kδ[(cos2φ/P11−P12)2+(sin2φ/P44)2]1/2
ただし、k=(λ/πdn0)3である。
(ここで、λは測定に用いる光の波長、dは基板厚さ、n0は基板の屈折率、δは複屈折により生じる位相差、φは主振動方位角、P11とP12とP44は弾性テンソルにおける光弾性定数成分を表す。)
図1に示す層構造のダイオードを下記のようにして製作することができる。
まず、残留歪の平均値が2×10-6である半絶縁性GaAs基板1の上に、MOCVD法によりバッファ層2及びn+GaAs層3を順に積層する。次にエピタキシャル基板全面にSiO2絶縁膜7を堆積し、続いてフォトレジストをマスクとしてパターニングを行い、p+GaAsを形成部となる領域に存在するSiO2絶縁膜を開口する。次いで、この開口部分にp+GaAs層4をMOCVD法により選択成長させる。さらに、p+GaAs層4上にp電極5をスパッタ法により堆積した後、n電極形成部のSiO2絶縁膜をフォトレジストをマスクとして開口し、n電極6を形成する(図4)。
基板をVB法により製造され、平均残留歪4×10-6のGaAs基板を用いる以外は、実施例1と同様の条件で実施した。その結果、実施例1と同様に素子の劣化(逆バイアスのリーク電流増加)はほとんどなく、転位の発生も見られなかった。
基板をLEC法により製造され、平均残留歪4×10-5のGaAs基板を用いる以外は、実施例1と同様の条件で実施した。その結果、図7に示すように、逆バイアスのリーク電流が増加した。実施例と同様に通電試験を行なったところ、図7のように逆バイアスのリーク電流がさらに大きくなった。また、通電後の素子の断面をTEM(透過型電子顕微鏡)で観察したところ、大量の転位が見られた。
2 バッファ層
3 n+GaAs層
4 p+GaAs層
5 p電極
6 n電極
7 SiO2絶縁膜
Claims (2)
- pn接合を有する化合物半導体エピタキシャル基板を選択成長法により製造する方法であって、残留歪の平均値が1.0×10-5以下である元基板を用いることを特徴とする化合物半導体エピタキシャル基板の製造方法。
- 元基板が、VGF法またはVB法により製造された元基板である請求項1記載の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004243413A JP2006060177A (ja) | 2004-08-24 | 2004-08-24 | pn接合を有する化合物半導体エピタキシャル基板の製造方法 |
TW094122568A TWI381428B (zh) | 2004-08-24 | 2005-07-04 | 具有pn接合之化合物半導體磊晶基板之製造方法 |
US11/660,936 US8906158B2 (en) | 2004-08-24 | 2005-08-23 | Method for producing compound semiconductor epitaxial substrate having PN junction |
PCT/JP2005/015248 WO2006022245A1 (ja) | 2004-08-24 | 2005-08-23 | pn接合を有する化合物半導体エピタキシャル基板の製造方法 |
KR1020077004607A KR20070048207A (ko) | 2004-08-24 | 2005-08-23 | pn 접합을 갖는 화합물 반도체 에피택셜 기판의 제조방법 |
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JP2004243413A JP2006060177A (ja) | 2004-08-24 | 2004-08-24 | pn接合を有する化合物半導体エピタキシャル基板の製造方法 |
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JP2006060177A true JP2006060177A (ja) | 2006-03-02 |
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JP2004243413A Pending JP2006060177A (ja) | 2004-08-24 | 2004-08-24 | pn接合を有する化合物半導体エピタキシャル基板の製造方法 |
Country Status (5)
Country | Link |
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US (1) | US8906158B2 (ja) |
JP (1) | JP2006060177A (ja) |
KR (1) | KR20070048207A (ja) |
TW (1) | TWI381428B (ja) |
WO (1) | WO2006022245A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011035066A (ja) * | 2009-07-30 | 2011-02-17 | Sumitomo Electric Ind Ltd | 窒化物半導体素子、及び窒化物半導体素子を作製する方法 |
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KR20150118405A (ko) * | 2014-04-14 | 2015-10-22 | 삼성전자주식회사 | 메시지 운용 방법 및 그 전자 장치 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5237766A (en) * | 1975-09-19 | 1977-03-23 | Nec Corp | Semiconductor device |
JPH05339100A (ja) * | 1992-04-10 | 1993-12-21 | Sumitomo Electric Ind Ltd | 化合物半導体単結晶およびその成長方法 |
JP2000103699A (ja) * | 1998-09-28 | 2000-04-11 | Sumitomo Electric Ind Ltd | GaAs単結晶基板およびそれを用いたエピタキシャルウェハ |
JP2003257997A (ja) * | 2002-02-28 | 2003-09-12 | Sumitomo Electric Ind Ltd | 窒化ガリウム系半導体装置を製造する方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3656261B2 (ja) | 1994-10-24 | 2005-06-08 | 住友電気工業株式会社 | GaAs結晶の熱処理方法 |
JPH11268998A (ja) | 1998-03-23 | 1999-10-05 | Sumitomo Electric Ind Ltd | GaAs単結晶インゴットおよびその製造方法ならびにそれを用いたGaAs単結晶ウエハ |
JP2001053005A (ja) * | 1999-08-06 | 2001-02-23 | Sumitomo Electric Ind Ltd | 化合物半導体エピタキシャルウェハおよびその製造方法 |
-
2004
- 2004-08-24 JP JP2004243413A patent/JP2006060177A/ja active Pending
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2005
- 2005-07-04 TW TW094122568A patent/TWI381428B/zh not_active IP Right Cessation
- 2005-08-23 US US11/660,936 patent/US8906158B2/en not_active Expired - Fee Related
- 2005-08-23 KR KR1020077004607A patent/KR20070048207A/ko not_active Application Discontinuation
- 2005-08-23 WO PCT/JP2005/015248 patent/WO2006022245A1/ja active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5237766A (en) * | 1975-09-19 | 1977-03-23 | Nec Corp | Semiconductor device |
JPH05339100A (ja) * | 1992-04-10 | 1993-12-21 | Sumitomo Electric Ind Ltd | 化合物半導体単結晶およびその成長方法 |
JP2000103699A (ja) * | 1998-09-28 | 2000-04-11 | Sumitomo Electric Ind Ltd | GaAs単結晶基板およびそれを用いたエピタキシャルウェハ |
JP2003257997A (ja) * | 2002-02-28 | 2003-09-12 | Sumitomo Electric Ind Ltd | 窒化ガリウム系半導体装置を製造する方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011035066A (ja) * | 2009-07-30 | 2011-02-17 | Sumitomo Electric Ind Ltd | 窒化物半導体素子、及び窒化物半導体素子を作製する方法 |
Also Published As
Publication number | Publication date |
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WO2006022245A1 (ja) | 2006-03-02 |
TWI381428B (zh) | 2013-01-01 |
US8906158B2 (en) | 2014-12-09 |
KR20070048207A (ko) | 2007-05-08 |
US20090031944A1 (en) | 2009-02-05 |
TW200616049A (en) | 2006-05-16 |
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