JP2005528596A5 - - Google Patents

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Publication number
JP2005528596A5
JP2005528596A5 JP2004502010A JP2004502010A JP2005528596A5 JP 2005528596 A5 JP2005528596 A5 JP 2005528596A5 JP 2004502010 A JP2004502010 A JP 2004502010A JP 2004502010 A JP2004502010 A JP 2004502010A JP 2005528596 A5 JP2005528596 A5 JP 2005528596A5
Authority
JP
Japan
Prior art keywords
semiconductor device
pins
storage element
signal generator
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004502010A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005528596A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2003/014328 external-priority patent/WO2003093845A2/en
Publication of JP2005528596A publication Critical patent/JP2005528596A/ja
Publication of JP2005528596A5 publication Critical patent/JP2005528596A5/ja
Pending legal-status Critical Current

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JP2004502010A 2002-05-06 2003-05-06 マルチタスク・アルゴリズミック・パターン・ジェネレータを有する半導体試験システム Pending JP2005528596A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37848802P 2002-05-06 2002-05-06
PCT/US2003/014328 WO2003093845A2 (en) 2002-05-06 2003-05-06 Semiconductor test system having multitasking algorithmic pattern generator

Publications (2)

Publication Number Publication Date
JP2005528596A JP2005528596A (ja) 2005-09-22
JP2005528596A5 true JP2005528596A5 (enExample) 2006-05-18

Family

ID=29401608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004502010A Pending JP2005528596A (ja) 2002-05-06 2003-05-06 マルチタスク・アルゴリズミック・パターン・ジェネレータを有する半導体試験システム

Country Status (5)

Country Link
US (1) US7472326B2 (enExample)
JP (1) JP2005528596A (enExample)
KR (1) KR101021375B1 (enExample)
TW (1) TWI278778B (enExample)
WO (1) WO2003093845A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7913002B2 (en) * 2004-08-20 2011-03-22 Advantest Corporation Test apparatus, configuration method, and device interface
JP2006179144A (ja) * 2004-12-24 2006-07-06 Fujitsu Ltd Ｉｃの高速試験方法及び装置
KR20130069853A (ko) * 2005-05-19 2013-06-26 넥스테스트 시스템즈 코포레이션 스마트 카드들을 테스트하기 위한 시스템 및 방법
JP4915779B2 (ja) * 2006-06-02 2012-04-11 株式会社メガチップス 装置間の接続方式および接続装置
KR20090036144A (ko) * 2006-08-14 2009-04-13 가부시키가이샤 어드밴티스트 시험 장치 및 시험 방법
TWI436077B (zh) * 2010-11-24 2014-05-01 Etron Technology Inc 增加晶片預燒掃描效率的方法
US9514016B2 (en) * 2011-02-01 2016-12-06 Echostar Technologies L.L.C. Apparatus systems and methods for facilitating testing of a plurality of electronic devices
CN104425269B (zh) * 2013-08-27 2017-07-14 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
US10242750B2 (en) * 2017-05-31 2019-03-26 Sandisk Technologies Llc High-speed data path testing techniques for non-volatile memory

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4759021A (en) * 1985-01-31 1988-07-19 Hitachi, Ltd. Test pattern generator
JPH0750159B2 (ja) * 1985-10-11 1995-05-31 株式会社日立製作所 テストパタ−ン発生装置
JPH0754345B2 (ja) * 1986-07-30 1995-06-07 株式会社日立製作所 Ｉｃ試験装置
DE3752280T2 (de) * 1986-07-30 2000-02-03 Hitachi, Ltd. Mustergenerator
JP2514223Y2 (ja) * 1989-11-07 1996-10-16 ミサワホーム株式会社 引違い障子を納めたサッシ
US5349587A (en) * 1992-03-26 1994-09-20 Northern Telecom Limited Multiple clock rate test apparatus for testing digital systems
JPH07198798A (ja) * 1993-12-28 1995-08-01 Hitachi Ltd アルゴリズミックパターン発生器
US5572666A (en) * 1995-03-28 1996-11-05 Sun Microsystems, Inc. System and method for generating pseudo-random instructions for design verification
EP0813151A4 (en) * 1995-12-27 1999-03-31 Koken Kk CONTROL DEVICE
US5883905A (en) * 1997-02-18 1999-03-16 Schlumberger Technologies, Inc. Pattern generator with extended register programming
JPH10319095A (ja) * 1997-05-22 1998-12-04 Mitsubishi Electric Corp 半導体テスト装置
US6118304A (en) * 1997-11-20 2000-09-12 Intrinsity, Inc. Method and apparatus for logic synchronization
US6246250B1 (en) * 1998-05-11 2001-06-12 Micron Technology, Inc. Probe card having on-board multiplex circuitry for expanding tester resources
JP2000276367A (ja) 1999-03-23 2000-10-06 Advantest Corp データ書込装置、データ書込方法、及び試験装置
US6363510B1 (en) * 1999-08-31 2002-03-26 Unisys Corporation Electronic system for testing chips having a selectable number of pattern generators that concurrently broadcast different bit streams to selectable sets of chip driver circuits
US6571365B1 (en) * 1999-11-03 2003-05-27 Unisys Corporation Initial stage of a multi-stage algorithmic pattern generator for testing IC chips
US6314034B1 (en) * 2000-04-14 2001-11-06 Advantest Corp. Application specific event based semiconductor memory test system
US6754868B2 (en) * 2001-06-29 2004-06-22 Nextest Systems Corporation Semiconductor test system having double data rate pin scrambling
US6631340B2 (en) * 2001-10-15 2003-10-07 Advantest Corp. Application specific event based semiconductor memory test system

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