Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/26—Testing of individual semiconductor devices
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/31813—Test pattern generators
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/319—Tester hardware, i.e. output processing circuits
  • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
  • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
  • G11C29/56004—Pattern generation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
  • G11C29/26—Accessing multiple arrays
  • G11C2029/2602—Concurrent test
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
  • G11C2029/5602—Interface to device under test

Definitions

• Each PE channel 251 typically includes a PE driver (not shown) capable of coupling signals to a pin 231 of DUT 203, a comparator (not shown) for comparing an.-output signal with an expected output signal, and an error logic circuit (not shown) for coupling results of the comparison back through the multitasking APG 201 to an error catch RAM 260.
• PE driver and comparator are not active in the same PE channel 251 at the same time, since pin 231 is either receiving data or control signals or transmitting a result at a given time.
• the Address Generator 220 being driven by MicroRAM 204.
• the output of the Address Generator 220 drives, an Address Topological Scrambler 222 and a Data Generator 230.
• the Address Topological Scrambler 222 is typically Random Access Memory that provides a topologically true data pattern to the DUT's internal array (not shown) after passing through the DUT's address decoders (not shown), which often scramble the address applied to pins 231 of the DUT 203.
• test site's timing system or T/Fs 250 is executing the DUT cycle just loaded, the multitasking APG 201 continues on to the other DUT sites to do the same thing.
• the multitasking capability does not cause any dead cycles in pattern execution. Patterns execute just like they would on a conventional APG. Users write all test patterns to the multitasking APG 201 from the host computer (not shown) as they would with a conventional APG and they do not have to manage any of the multitasking hardware: The only thing the user needs to be cognizant of is the number of DUTs 203 to be tested or time domains into which the multitasking APG •
• DUTs 203 in a particular time domain have been programmed and adjusting the period or frequency with which the test pattern is coupled to DUTs in the remaining time domains, thereby maximizing the efficiency of tester 200.
• the DUTs 203 or time -domains need not be serviced in a regular, or sequential staggered order, but can selecting any of the storage elements 272, 273, 274, to service the DUTs or time domains in any order required based on priorities. For example, where a plurality of DUTs are tested in four time domains having or requiring in upcoming cycles, cycle times of 80nSec, 100 nSec, 80 nSec and 200nSec, the DUT

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Tests Of Electronic Circuits (AREA)

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Publications (2)

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• 2003
  • 2003-05-06 KR KR1020047017833A patent/KR101021375B1/ko not_active Expired - Lifetime
  • 2003-05-06 JP JP2004502010A patent/JP2005528596A/ja active Pending
  • 2003-05-06 TW TW092112502A patent/TWI278778B/zh not_active IP Right Cessation
  • 2003-05-06 US US10/431,043 patent/US7472326B2/en not_active Expired - Lifetime
  • 2003-05-06 WO PCT/US2003/014328 patent/WO2003093845A2/en not_active Ceased

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