JP2005528596A - マルチタスク・アルゴリズミック・パターン・ジェネレータを有する半導体試験システム - Google Patents
マルチタスク・アルゴリズミック・パターン・ジェネレータを有する半導体試験システム Download PDFInfo
- Publication number
- JP2005528596A JP2005528596A JP2004502010A JP2004502010A JP2005528596A JP 2005528596 A JP2005528596 A JP 2005528596A JP 2004502010 A JP2004502010 A JP 2004502010A JP 2004502010 A JP2004502010 A JP 2004502010A JP 2005528596 A JP2005528596 A JP 2005528596A
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- Prior art keywords
- semiconductor devices
- apg
- test
- under test
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 327
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 38
- 238000012545 processing Methods 0.000 claims description 5
- 238000012546 transfer Methods 0.000 claims description 2
- 238000007689 inspection Methods 0.000 claims 3
- 230000006870 function Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000004317 sodium nitrate Substances 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000013598 vector Substances 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31813—Test pattern generators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56004—Pattern generation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
- G11C2029/2602—Concurrent test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5602—Interface to device under test
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US37848802P | 2002-05-06 | 2002-05-06 | |
| PCT/US2003/014328 WO2003093845A2 (en) | 2002-05-06 | 2003-05-06 | Semiconductor test system having multitasking algorithmic pattern generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2005528596A true JP2005528596A (ja) | 2005-09-22 |
| JP2005528596A5 JP2005528596A5 (enExample) | 2006-05-18 |
Family
ID=29401608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004502010A Pending JP2005528596A (ja) | 2002-05-06 | 2003-05-06 | マルチタスク・アルゴリズミック・パターン・ジェネレータを有する半導体試験システム |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7472326B2 (enExample) |
| JP (1) | JP2005528596A (enExample) |
| KR (1) | KR101021375B1 (enExample) |
| TW (1) | TWI278778B (enExample) |
| WO (1) | WO2003093845A2 (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006179144A (ja) * | 2004-12-24 | 2006-07-06 | Fujitsu Ltd | Icの高速試験方法及び装置 |
| JP2008546063A (ja) * | 2005-05-19 | 2008-12-18 | ネクステスト システムズ コーポレイション | スマートカードを試験するためのシステム及びその方法 |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7913002B2 (en) * | 2004-08-20 | 2011-03-22 | Advantest Corporation | Test apparatus, configuration method, and device interface |
| JP4915779B2 (ja) * | 2006-06-02 | 2012-04-11 | 株式会社メガチップス | 装置間の接続方式および接続装置 |
| WO2008020555A1 (en) * | 2006-08-14 | 2008-02-21 | Advantest Corporation | Test device and test method |
| TWI436077B (zh) * | 2010-11-24 | 2014-05-01 | Etron Technology Inc | 增加晶片預燒掃描效率的方法 |
| US9514016B2 (en) * | 2011-02-01 | 2016-12-06 | Echostar Technologies L.L.C. | Apparatus systems and methods for facilitating testing of a plurality of electronic devices |
| CN104425269B (zh) * | 2013-08-27 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | 鳍式场效应晶体管及其形成方法 |
| US10242750B2 (en) * | 2017-05-31 | 2019-03-26 | Sandisk Technologies Llc | High-speed data path testing techniques for non-volatile memory |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4759021A (en) * | 1985-01-31 | 1988-07-19 | Hitachi, Ltd. | Test pattern generator |
| JPH0750159B2 (ja) * | 1985-10-11 | 1995-05-31 | 株式会社日立製作所 | テストパタ−ン発生装置 |
| JPH0754345B2 (ja) * | 1986-07-30 | 1995-06-07 | 株式会社日立製作所 | Ic試験装置 |
| DE3752280T2 (de) * | 1986-07-30 | 2000-02-03 | Hitachi, Ltd. | Mustergenerator |
| JP2514223Y2 (ja) * | 1989-11-07 | 1996-10-16 | ミサワホーム株式会社 | 引違い障子を納めたサッシ |
| US5349587A (en) * | 1992-03-26 | 1994-09-20 | Northern Telecom Limited | Multiple clock rate test apparatus for testing digital systems |
| JPH07198798A (ja) * | 1993-12-28 | 1995-08-01 | Hitachi Ltd | アルゴリズミックパターン発生器 |
| US5572666A (en) * | 1995-03-28 | 1996-11-05 | Sun Microsystems, Inc. | System and method for generating pseudo-random instructions for design verification |
| EP1632780A2 (en) * | 1995-12-27 | 2006-03-08 | Koken Co., Ltd. | Monitoring control apparatus |
| US5883905A (en) * | 1997-02-18 | 1999-03-16 | Schlumberger Technologies, Inc. | Pattern generator with extended register programming |
| JPH10319095A (ja) * | 1997-05-22 | 1998-12-04 | Mitsubishi Electric Corp | 半導体テスト装置 |
| US6118304A (en) * | 1997-11-20 | 2000-09-12 | Intrinsity, Inc. | Method and apparatus for logic synchronization |
| US6246250B1 (en) * | 1998-05-11 | 2001-06-12 | Micron Technology, Inc. | Probe card having on-board multiplex circuitry for expanding tester resources |
| JP2000276367A (ja) | 1999-03-23 | 2000-10-06 | Advantest Corp | データ書込装置、データ書込方法、及び試験装置 |
| US6363510B1 (en) * | 1999-08-31 | 2002-03-26 | Unisys Corporation | Electronic system for testing chips having a selectable number of pattern generators that concurrently broadcast different bit streams to selectable sets of chip driver circuits |
| US6571365B1 (en) * | 1999-11-03 | 2003-05-27 | Unisys Corporation | Initial stage of a multi-stage algorithmic pattern generator for testing IC chips |
| US6314034B1 (en) * | 2000-04-14 | 2001-11-06 | Advantest Corp. | Application specific event based semiconductor memory test system |
| US6754868B2 (en) * | 2001-06-29 | 2004-06-22 | Nextest Systems Corporation | Semiconductor test system having double data rate pin scrambling |
| US6631340B2 (en) * | 2001-10-15 | 2003-10-07 | Advantest Corp. | Application specific event based semiconductor memory test system |
-
2003
- 2003-05-06 KR KR1020047017833A patent/KR101021375B1/ko not_active Expired - Lifetime
- 2003-05-06 JP JP2004502010A patent/JP2005528596A/ja active Pending
- 2003-05-06 TW TW092112502A patent/TWI278778B/zh not_active IP Right Cessation
- 2003-05-06 US US10/431,043 patent/US7472326B2/en not_active Expired - Lifetime
- 2003-05-06 WO PCT/US2003/014328 patent/WO2003093845A2/en not_active Ceased
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006179144A (ja) * | 2004-12-24 | 2006-07-06 | Fujitsu Ltd | Icの高速試験方法及び装置 |
| JP2008546063A (ja) * | 2005-05-19 | 2008-12-18 | ネクステスト システムズ コーポレイション | スマートカードを試験するためのシステム及びその方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2003093845A2 (en) | 2003-11-13 |
| TWI278778B (en) | 2007-04-11 |
| KR20050003411A (ko) | 2005-01-10 |
| WO2003093845A3 (en) | 2005-05-26 |
| US7472326B2 (en) | 2008-12-30 |
| KR101021375B1 (ko) | 2011-03-14 |
| US20040153920A1 (en) | 2004-08-05 |
| TW200401227A (en) | 2004-01-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060322 |
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| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060322 |
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| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090316 |
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| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20090616 |
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| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20090623 |
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| A02 | Decision of refusal |
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