JP2005517325A5 - - Google Patents

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Publication number
JP2005517325A5
JP2005517325A5 JP2003559096A JP2003559096A JP2005517325A5 JP 2005517325 A5 JP2005517325 A5 JP 2005517325A5 JP 2003559096 A JP2003559096 A JP 2003559096A JP 2003559096 A JP2003559096 A JP 2003559096A JP 2005517325 A5 JP2005517325 A5 JP 2005517325A5
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JP
Japan
Prior art keywords
receiver
communication circuit
adc
circuit according
driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2003559096A
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English (en)
Japanese (ja)
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JP2005517325A (ja
JP4554934B2 (ja
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Publication date
Application filed filed Critical
Priority claimed from PCT/IE2002/000168 external-priority patent/WO2003058902A2/en
Publication of JP2005517325A publication Critical patent/JP2005517325A/ja
Publication of JP2005517325A5 publication Critical patent/JP2005517325A5/ja
Application granted granted Critical
Publication of JP4554934B2 publication Critical patent/JP4554934B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2003559096A 2002-01-11 2002-12-11 データ受信機および送信機におけるタイミング制御 Expired - Fee Related JP4554934B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US34698302P 2002-01-11 2002-01-11
PCT/IE2002/000168 WO2003058902A2 (en) 2002-01-11 2002-12-11 Timing control in data receivers and transmitters

Publications (3)

Publication Number Publication Date
JP2005517325A JP2005517325A (ja) 2005-06-09
JP2005517325A5 true JP2005517325A5 (https=) 2006-01-26
JP4554934B2 JP4554934B2 (ja) 2010-09-29

Family

ID=23361851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003559096A Expired - Fee Related JP4554934B2 (ja) 2002-01-11 2002-12-11 データ受信機および送信機におけるタイミング制御

Country Status (8)

Country Link
US (1) US7158562B2 (https=)
EP (1) EP1464147B1 (https=)
JP (1) JP4554934B2 (https=)
KR (1) KR100806536B1 (https=)
AU (1) AU2002348700A1 (https=)
CA (1) CA2471255A1 (https=)
DE (1) DE60239159D1 (https=)
WO (1) WO2003058902A2 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100223186A1 (en) * 2000-04-11 2010-09-02 Hogan Edward J Method and System for Conducting Secure Payments
US20100228668A1 (en) * 2000-04-11 2010-09-09 Hogan Edward J Method and System for Conducting a Transaction Using a Proximity Device and an Identifier
US7379919B2 (en) * 2000-04-11 2008-05-27 Mastercard International Incorporated Method and system for conducting secure payments over a computer network
US8133113B2 (en) * 2004-10-04 2012-03-13 Igt Class II/Class III hybrid gaming machine, system and methods
US7421014B2 (en) * 2003-09-11 2008-09-02 Xilinx, Inc. Channel bonding of a plurality of multi-gigabit transceivers
EP1763146A1 (en) * 2005-09-12 2007-03-14 Sigma Designs, Inc. Ultra wideband baseband chip with intelligent array radio and method of use thereof
US7873132B2 (en) * 2005-09-21 2011-01-18 Hewlett-Packard Development Company, L.P. Clock recovery
US8638843B2 (en) 2010-06-03 2014-01-28 Fujitsu Limited Receiving device and receiving method
JP5700546B2 (ja) 2010-06-03 2015-04-15 富士通株式会社 受信装置および受信方法
JP5545098B2 (ja) * 2010-07-29 2014-07-09 富士通株式会社 Ａｄ変換装置
US8976050B1 (en) * 2013-09-12 2015-03-10 Fujitsu Semiconductor Limited Circuitry and methods for use in mixed-signal circuitry

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009130A (en) * 1995-12-28 1999-12-28 Motorola, Inc. Multiple access digital transmitter and receiver
US5970093A (en) 1996-01-23 1999-10-19 Tiernan Communications, Inc. Fractionally-spaced adaptively-equalized self-recovering digital receiver for amplitude-Phase modulated signals
US5703905A (en) 1996-02-16 1997-12-30 Globespan Technologies, Inc. Multi-channel timing recovery system
US5838744A (en) * 1996-10-22 1998-11-17 Talx Corporation High speed modem and method having jitter-free timing recovery
JPH10336087A (ja) * 1997-05-30 1998-12-18 Kyocera Corp 最大比合成送信ダイバーシティ装置
US6307906B1 (en) 1997-10-07 2001-10-23 Applied Micro Circuits Corporation Clock and data recovery scheme for multi-channel data communications receivers
CA2649659A1 (en) * 1998-03-09 1999-09-16 Broadcom Corporation Gigabit ethernet transceiver
GB9905997D0 (en) * 1999-03-16 1999-05-12 Koninkl Philips Electronics Nv Radio receiver
JP4547064B2 (ja) * 1999-03-24 2010-09-22 株式会社アドバンテスト Ａ／ｄ変換装置およびキャリブレーション装置
AU4490600A (en) 1999-04-22 2000-11-10 Broadcom Corporation Phy control module for a multi-pair gigabit transceiver
DE60022755T2 (de) * 1999-07-16 2006-05-18 Thomson Licensing S.A., Boulogne Selektive verstärkungseinstellung zur erleichterung der trägerrückgewinnung in einem hochauflösenden fernsehempfänger
JP3890867B2 (ja) * 1999-09-17 2007-03-07 松下電器産業株式会社 受信機および送受信機
GB2359705B (en) 2000-02-28 2003-11-26 Virata Ltd xDSL sample rate compensation using phase balancing
JP3745962B2 (ja) * 2001-01-24 2006-02-15 株式会社アドバンテスト インターリーブａｄ変換方式波形ディジタイザ装置、及び試験装置
JP2002246910A (ja) * 2001-02-20 2002-08-30 Advantest Corp インターリーブａｄ変換方式波形ディジタイザ装置
US6993673B2 (en) * 2001-12-17 2006-01-31 Mysticom Ltd. Apparatus for frequency and timing recovery in a communication device
US7505809B2 (en) * 2003-01-13 2009-03-17 Mediguide Ltd. Method and system for registering a first image with a second image relative to the body of a patient

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