JP2005347442A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2005347442A
JP2005347442A JP2004164091A JP2004164091A JP2005347442A JP 2005347442 A JP2005347442 A JP 2005347442A JP 2004164091 A JP2004164091 A JP 2004164091A JP 2004164091 A JP2004164091 A JP 2004164091A JP 2005347442 A JP2005347442 A JP 2005347442A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
electronic device
wiring layer
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004164091A
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English (en)
Japanese (ja)
Other versions
JP2005347442A5 (enExample
Inventor
Kojiro Kameyama
工次郎 亀山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2004164091A priority Critical patent/JP2005347442A/ja
Publication of JP2005347442A publication Critical patent/JP2005347442A/ja
Publication of JP2005347442A5 publication Critical patent/JP2005347442A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

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  • Solid State Image Pick-Up Elements (AREA)
JP2004164091A 2004-06-02 2004-06-02 半導体装置 Withdrawn JP2005347442A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004164091A JP2005347442A (ja) 2004-06-02 2004-06-02 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004164091A JP2005347442A (ja) 2004-06-02 2004-06-02 半導体装置

Publications (2)

Publication Number Publication Date
JP2005347442A true JP2005347442A (ja) 2005-12-15
JP2005347442A5 JP2005347442A5 (enExample) 2007-07-12

Family

ID=35499547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004164091A Withdrawn JP2005347442A (ja) 2004-06-02 2004-06-02 半導体装置

Country Status (1)

Country Link
JP (1) JP2005347442A (enExample)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007311395A (ja) * 2006-05-16 2007-11-29 Toppan Printing Co Ltd 半導体装置及び半導体装置の製造方法
JP2009094246A (ja) * 2007-10-05 2009-04-30 Rohm Co Ltd 半導体装置
JP2009111356A (ja) * 2007-09-20 2009-05-21 Promerus Llc チップを積層するために、そしてチップ及びウェハを接合させるために有用な方法及び材料
JP2010067844A (ja) * 2008-09-11 2010-03-25 Omron Corp 固体撮像素子の製造方法
JP2010516057A (ja) * 2007-01-11 2010-05-13 ヒューレット−パッカード デベロップメント カンパニー エル．ピー． 多層デバイスの層の容量結合
US8373278B2 (en) * 2007-03-15 2013-02-12 Sanyo Semiconductor Co., Ltd. Semiconductor device having stacked dice disposed on base substrate
JP2014007201A (ja) * 2012-06-21 2014-01-16 Fujitsu Ltd 赤外線検知素子の製造方法、および赤外線検知素子
JP2014503992A (ja) * 2010-11-15 2014-02-13 テッセラ，インコーポレイテッド 埋込みトレースによって画定される導電性パッド
CN104025568A (zh) * 2011-12-28 2014-09-03 株式会社尼康 拍摄装置
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
KR101761817B1 (ko) * 2011-03-04 2017-07-26 삼성전자주식회사 대면적 엑스선 검출기
US10354942B2 (en) 2010-09-17 2019-07-16 Tessera, Inc. Staged via formation from both sides of chip
JP2023087210A (ja) * 2021-12-13 2023-06-23 浜松ホトニクス株式会社 光半導体パッケージ及び光半導体パッケージの製造方法

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007311395A (ja) * 2006-05-16 2007-11-29 Toppan Printing Co Ltd 半導体装置及び半導体装置の製造方法
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
KR101409309B1 (ko) * 2007-01-11 2014-06-18 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 다중층 디바이스의 용량성 결합층들
JP2010516057A (ja) * 2007-01-11 2010-05-13 ヒューレット−パッカード デベロップメント カンパニー エル．ピー． 多層デバイスの層の容量結合
US8373278B2 (en) * 2007-03-15 2013-02-12 Sanyo Semiconductor Co., Ltd. Semiconductor device having stacked dice disposed on base substrate
JP2009111356A (ja) * 2007-09-20 2009-05-21 Promerus Llc チップを積層するために、そしてチップ及びウェハを接合させるために有用な方法及び材料
JP2009094246A (ja) * 2007-10-05 2009-04-30 Rohm Co Ltd 半導体装置
JP2010067844A (ja) * 2008-09-11 2010-03-25 Omron Corp 固体撮像素子の製造方法
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US10354942B2 (en) 2010-09-17 2019-07-16 Tessera, Inc. Staged via formation from both sides of chip
JP2014503992A (ja) * 2010-11-15 2014-02-13 テッセラ，インコーポレイテッド 埋込みトレースによって画定される導電性パッド
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
KR101761817B1 (ko) * 2011-03-04 2017-07-26 삼성전자주식회사 대면적 엑스선 검출기
CN104025568A (zh) * 2011-12-28 2014-09-03 株式会社尼康 拍摄装置
CN104025568B (zh) * 2011-12-28 2017-10-27 株式会社尼康 拍摄装置
JP2014007201A (ja) * 2012-06-21 2014-01-16 Fujitsu Ltd 赤外線検知素子の製造方法、および赤外線検知素子
JP2023087210A (ja) * 2021-12-13 2023-06-23 浜松ホトニクス株式会社 光半導体パッケージ及び光半導体パッケージの製造方法

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