JP2005328005A - 半導体装置及びその製造方法、回路基板並びに電子機器 - Google Patents
半導体装置及びその製造方法、回路基板並びに電子機器 Download PDFInfo
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- JP2005328005A JP2005328005A JP2004146942A JP2004146942A JP2005328005A JP 2005328005 A JP2005328005 A JP 2005328005A JP 2004146942 A JP2004146942 A JP 2004146942A JP 2004146942 A JP2004146942 A JP 2004146942A JP 2005328005 A JP2005328005 A JP 2005328005A
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Abstract
【解決手段】 半導体装置は、配線パターン14,16を有する配線基板10と、配線基板10に搭載され第1の電極24を有する第1の半導体チップ20と、第1の電極24と間隔をあけてオーバーラップするように第1の半導体チップ20に搭載された第2の半導体チップ30と、第1の半導体チップ20と第2の半導体チップ30との間に介在するスペーサ40と、配線パターン14と第1の電極24とを電気的に接続するワイヤ50と、を含む。ワイヤ50は、第2の半導体チップ30のオーバーラップする範囲の外側に最頂部54が位置し、かつ、第2の半導体チップ30のオーバーラップする範囲の境界部57から第1の電極24との接続部58までの部分が、配線基板10の面とほぼ平行に延出されてなる。
【選択図】 図1
Description
配線パターンを有する配線基板と、
前記配線基板に搭載され、第1の電極を有する第1の半導体チップと、
前記第1の電極と間隔をあけてオーバーラップするように前記第1の半導体チップに搭載された第2の半導体チップと、
前記第1の半導体チップと前記第2の半導体チップとの間に介在するスペーサと、
前記配線パターンと前記第1の電極とを電気的に接続するワイヤと、
を含み、
前記ワイヤは、
前記第2の半導体チップのオーバーラップする範囲の外側に最頂部が位置し、かつ、
前記第2の半導体チップのオーバーラップする範囲の境界部から前記第1の電極との接続部までの部分が、前記配線基板の面とほぼ平行に延出されてなる。本発明によれば、ワイヤは、上段の第2の半導体チップのオーバーラップする範囲の境界部から、下段の第1の半導体チップの第1の電極との接続部までの部分が、配線基板の面とほぼ平行になるように延出されている。したがって、上下の半導体チップの間隔を可能な限り狭くすることができ、半導体装置の薄型化を図ることができる。また、ワイヤは、上段の第2の半導体チップのオーバーラップする範囲の外側に最頂部が位置している。したがって、ワイヤの配線パターンからの立ち上がり部が急な角度で倒し込まれるのを防止し、ワイヤにダメージが加えられるのを回避することができ、半導体装置の高信頼性化を図ることができる。
(2)この半導体装置において、
前記ワイヤは、
前記配線パターン上に配置されたバンプを有し、
前記バンプから、前記配線基板の面に対してほぼ垂直に立ち上がるように、第1中間点まで延出され、
前記第1中間点から、前記第1の電極に近づく方向であって前記配線基板から離れる方向に、第2中間点まで延出され、
いずれかに前記最頂部を有するように、前記第2中間点から前記第1の電極に近づく方向に第3中間点まで延出され、
前記第3中間点から、前記第1の電極に近づく方向であって前記配線基板に近づく方向に、第4中間点まで延出され、
前記第4中間点から、前記境界部を通過するとともに前記配線基板の面に対してほぼ平行に、前記接続部まで延出されてなる半導体装置。
(3)この半導体装置において、
前記ワイヤの前記第2中間点から前記第3中間点までの部分は、前記配線基板の面に対してほぼ平行に延出されてなる半導体装置。
(4)この半導体装置において、
前記ワイヤの前記最頂部は、前記第2の半導体チップの最底面よりも高い位置に配置されてなる半導体装置。これによって、ワイヤの最頂部までの軌道が緩やかなカーブになるので、ワイヤにダメージが加えられるのを回避することができる。
(5)この半導体装置において、
前記第1の半導体チップの平面形状は、前記第2の半導体チップの平面形状とほぼ同じである半導体装置。
(6)この半導体装置において、
前記第1の半導体チップの平面形状は、前記第2の半導体チップの平面形状よりも小さい半導体装置。
(7)この半導体装置において、
前記第2の半導体チップは、第2の電極を有し、
前記配線パターンと前記第2の電極とを電気的に接続する他のワイヤをさらに含む半導体装置。
(8)本発明に係る回路基板には、上記半導体装置が実装されている。
(9)本発明に係る電子機器は、上記半導体装置を有する。
(10)本発明に係る半導体装置の製造方法は、
(a)前記配線パターンを有する配線基板に、第1の電極を有する第1の半導体チップを搭載すること、
(b)前記配線パターンと前記第1の電極とを電気的に接続するように、ワイヤを前記配線パターンにボンディングし、その後に前記第1の電極にボンディングすること、
(c)第2の半導体チップを、前記第1の電極と間隔をあけてオーバーラップするように第1の半導体チップに搭載すること、
を含み、
前記(b)工程で、前記ワイヤを、
前記第2の半導体チップのオーバーラップする範囲の外側に最頂部が位置し、かつ、
前記第2の半導体チップのオーバーラップする範囲の境界部から前記第1の電極との接続部までの部分が、前記配線基板の面とほぼ平行に延出させる。本発明によれば、ワイヤを、上段の第2の半導体チップのオーバーラップする範囲の境界部から、下段の第1の半導体チップの第1の電極との接続部までの部分が、配線基板の面とほぼ平行になるように延出させる。したがって、上下の半導体チップの間隔を可能な限り狭くすることができ、半導体装置の薄型化を図ることができる。また、ワイヤを、上段の第2の半導体チップのオーバーラップする範囲の外側に最頂部が位置するように形成する。したがって、ワイヤの配線パターンからの立ち上がり部が急な角度で倒し込まれるのを防止し、ワイヤにダメージが加えられるのを回避することができ、半導体装置の高信頼性化を図ることができる。
24…第1の電極 30…第2の半導体チップ 34…第2の電極 40…スペーサ
50…ワイヤ 51…バンプ 52…第1中間点 53…第2中間点 54…最頂部
55…第3中間点 56…第4中間点 57…境界部 58…接続部 60…ワイヤ
120…第1の半導体チップ 124…第1の電極
Claims (10)
- 配線パターンを有する配線基板と、
前記配線基板に搭載され、第1の電極を有する第1の半導体チップと、
前記第1の電極と間隔をあけてオーバーラップするように前記第1の半導体チップに搭載された第2の半導体チップと、
前記第1の半導体チップと前記第2の半導体チップとの間に介在するスペーサと、
前記配線パターンと前記第1の電極とを電気的に接続するワイヤと、
を含み、
前記ワイヤは、
前記第2の半導体チップのオーバーラップする範囲の外側に最頂部が位置し、かつ、
前記第2の半導体チップのオーバーラップする範囲の境界部から前記第1の電極との接続部までの部分が、前記配線基板の面とほぼ平行に延出されてなる半導体装置。 - 請求項1記載の半導体装置において、
前記ワイヤは、
前記配線パターン上に配置されたバンプを有し、
前記バンプから、前記配線基板の面に対してほぼ垂直に立ち上がるように、第1中間点まで延出され、
前記第1中間点から、前記第1の電極に近づく方向であって前記配線基板から離れる方向に、第2中間点まで延出され、
いずれかに前記最頂部を有するように、前記第2中間点から前記第1の電極に近づく方向に第3中間点まで延出され、
前記第3中間点から、前記第1の電極に近づく方向であって前記配線基板に近づく方向に、第4中間点まで延出され、
前記第4中間点から、前記境界部を通過するとともに前記配線基板の面に対してほぼ平行に、前記接続部まで延出されてなる半導体装置。 - 請求項2記載の半導体装置において、
前記ワイヤの前記第2中間点から前記第3中間点までの部分は、前記配線基板の面に対してほぼ平行に延出されてなる半導体装置。 - 請求項1から請求項3のいずれかに記載の半導体装置において、
前記ワイヤの前記最頂部は、前記第2の半導体チップの最底面よりも高い位置に配置されてなる半導体装置。 - 請求項1から請求項4のいずれかに記載の半導体装置において、
前記第1の半導体チップの平面形状は、前記第2の半導体チップの平面形状とほぼ同じである半導体装置。 - 請求項1から請求項4のいずれかに記載の半導体装置において、
前記第1の半導体チップの平面形状は、前記第2の半導体チップの平面形状よりも小さい半導体装置。 - 請求項1から請求項6のいずれかに記載の半導体装置において、
前記第2の半導体チップは、第2の電極を有し、
前記配線パターンと前記第2の電極とを電気的に接続する他のワイヤをさらに含む半導体装置。 - 請求項1から請求項7のいずれかに記載の半導体装置が実装された回路基板。
- 請求項1から請求項7のいずれかに記載の半導体装置を有する電子機器。
- (a)前記配線パターンを有する配線基板に、第1の電極を有する第1の半導体チップを搭載すること、
(b)前記配線パターンと前記第1の電極とを電気的に接続するように、ワイヤを前記配線パターンにボンディングし、その後に前記第1の電極にボンディングすること、
(c)第2の半導体チップを、前記第1の電極と間隔をあけてオーバーラップするように第1の半導体チップに搭載すること、
を含み、
前記(b)工程で、前記ワイヤを、
前記第2の半導体チップのオーバーラップする範囲の外側に最頂部が位置し、かつ、
前記第2の半導体チップのオーバーラップする範囲の境界部から前記第1の電極との接続部までの部分が、前記配線基板の面とほぼ平行に延出させる半導体装置の製造方法。
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JP2008187109A (ja) * | 2007-01-31 | 2008-08-14 | Toshiba Corp | 積層型半導体装置とその製造方法 |
US8039970B2 (en) | 2007-01-31 | 2011-10-18 | Kabushiki Kaisha Toshiba | Stacked semiconductor device and method of manufacturing the same |
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