JP2005322811A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP2005322811A JP2005322811A JP2004140431A JP2004140431A JP2005322811A JP 2005322811 A JP2005322811 A JP 2005322811A JP 2004140431 A JP2004140431 A JP 2004140431A JP 2004140431 A JP2004140431 A JP 2004140431A JP 2005322811 A JP2005322811 A JP 2005322811A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
Abstract
【解決手段】 エッチング材料であるGaN系半導体層、SiCやサファイヤの基板21上に、Ti膜22およびNi膜24をこの順で積層させて真空蒸着成膜し、この積層膜にフォトリソグラフ法でパターニングを施してマスクを形成する。例えばエッチング基体がSiC基板である場合、SiCの熱膨張係数は4.2×10−6/℃、Niの熱膨張係数は12.8×10−6/℃であるが、熱膨張係数が9.0×10−6/℃のTi膜22を設けることでドライエッチング中の温度上昇により生じる熱膨張に伴って発生する歪が緩和され、SiC基板表面へのマスクの密着性を高めて剥離やクラックの発生が抑制される。
【選択図】 図2
Description
12 ステンレスマスク
22、42 Ti膜
23、43、53 フォトレジストマスク
24、44 Ni膜
25、45、55 バイアホール
54 Ni合金膜
Claims (13)
- GaN系半導体、SiCまたはサファイアからなる被エッチング材料の表面にTi膜とNi含有金属膜とを順次成膜して積層膜を形成する第1のステップと、
前記積層膜にパターニングを施して前記エッチング材料表面の一部領域を暴露する第2のステップと、
前記暴露された前記被エッチング材料表面にドライエッチングを施す第3のステップとを備えていることを特徴とする半導体装置の製造方法。 - 前記第2のステップにおける前記積層膜のパターニングは、前記被エッチング材料上に所定のマスクを設け、前記積層膜を形成した後に前記マスクを除去することでなされるリフトオフ工程であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第3のステップにおけるドライエッチングは、反応性イオンエッチング法、電子サイクロトロン共鳴エッチング法、または誘導結合型プラズマエッチング法の何れかにより実行されることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記GaN系半導体は、InGaN、AlGaNもしくはInGaNPであることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記Ni含有金属膜およびTi膜は、真空蒸着法またはスパッタリング法により成膜されることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記Ti膜の厚みは10〜30nmであることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記Ti膜の厚みは概ね20nmであることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記Ni含有金属膜の厚みは、10μm以下であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記Ni含有金属膜はNiまたはNiを含有する金属のメッキ膜であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記Niを含有する金属のメッキ膜は、Niに加え、Ag、Sn、P、またはBの少なくとも一つからなる他の金属とにより構成されることを特徴とする請求項9に記載の半導体装置の製造方法。
- 前記他の金属として、AgまたはSnが選択された場合、その含有量は組成比で10〜20%であることを特徴とする請求項10に記載の半導体装置の製造方法。
- 前記他の金属として、PまたはBが選択された場合、その含有量は組成比で8〜10%であることを特徴とする請求項10に記載の半導体装置の製造方法。
- GaN系半導体またはSiCまたはサファイアからなる層を備え、前記層は、表面にTi膜、Ni含有金属膜の順に設けられた積層膜のマスクにより、選択的にドライエッチングが施されることを特徴とする半導体装置。
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JP2004140431A JP4030982B2 (ja) | 2004-05-10 | 2004-05-10 | 半導体装置および半導体装置の製造方法 |
US11/125,137 US20050250336A1 (en) | 2004-05-10 | 2005-05-10 | Semiconductor device and method for fabricating the same |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007157806A (ja) * | 2005-12-01 | 2007-06-21 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2007234912A (ja) * | 2006-03-01 | 2007-09-13 | Eudyna Devices Inc | 半導体装置およびその製造方法 |
JP2008226962A (ja) * | 2007-03-09 | 2008-09-25 | Sumitomo Chemical Co Ltd | 半導体発光素子およびその製造方法 |
US7829919B2 (en) | 2008-03-31 | 2010-11-09 | Kabushiki Kaisha Toshiba | Semiconductor device |
JP2011096700A (ja) | 2009-10-27 | 2011-05-12 | Sumitomo Precision Prod Co Ltd | プラズマエッチング方法 |
US8071482B2 (en) | 2007-05-21 | 2011-12-06 | Fuji Electric Co., Ltd. | Manufacturing method of a silicon carbide semiconductor device |
US8084793B2 (en) | 2008-04-03 | 2011-12-27 | Kabushiki Kaisha Toshiba | Microwave semiconductor device using compound semiconductor and method for manufacturing the same |
US8541298B2 (en) | 2010-07-21 | 2013-09-24 | Sumitomo Electric Device Innovations, Inc. | Method for fabricating semiconductor device |
JP7258719B2 (ja) | 2019-10-24 | 2023-04-17 | 株式会社ノリタケカンパニーリミテド | ダイヤモンドドレッサ |
Families Citing this family (4)
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JP2008098456A (ja) * | 2006-10-13 | 2008-04-24 | Eudyna Devices Inc | 半導体装置の製造方法 |
CN102110592A (zh) * | 2010-12-02 | 2011-06-29 | 南京大学扬州光电研究院 | 用于干法刻蚀的蓝宝石衬底表面加工前期生产方法 |
CN104599949A (zh) * | 2014-12-30 | 2015-05-06 | 上海师范大学 | 基于SiC衬底片深刻蚀光滑表面的加工工艺 |
CN106910711A (zh) * | 2017-02-13 | 2017-06-30 | 苏州本然微电子有限公司 | 一种用于GaN HEMT芯片生产中通孔的刻蚀方法 |
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FR2633451B1 (fr) * | 1988-06-24 | 1990-10-05 | Labo Electronique Physique | Procede de realisation de dispositifs semiconducteurs incluant au moins une etape de gravure ionique reactive |
JP3292044B2 (ja) * | 1996-05-31 | 2002-06-17 | 豊田合成株式会社 | p伝導形3族窒化物半導体の電極パッド及びそれを有した素子及び素子の製造方法 |
US6106907A (en) * | 1996-06-25 | 2000-08-22 | Canon Kabushiki Kaisha | Electrode plate, liquid crystal device and production thereof |
JP4217778B2 (ja) * | 2003-04-11 | 2009-02-04 | 古河電気工業株式会社 | 抵抗層付き導電性基材、抵抗層付き回路基板及び抵抗回路配線板 |
US7074631B2 (en) * | 2003-04-15 | 2006-07-11 | Luminus Devices, Inc. | Light emitting device methods |
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2004
- 2004-05-10 JP JP2004140431A patent/JP4030982B2/ja not_active Expired - Lifetime
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2005
- 2005-05-10 US US11/125,137 patent/US20050250336A1/en not_active Abandoned
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007157806A (ja) * | 2005-12-01 | 2007-06-21 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP4612534B2 (ja) * | 2005-12-01 | 2011-01-12 | 三菱電機株式会社 | 半導体装置の製造方法 |
US7754616B2 (en) | 2006-03-01 | 2010-07-13 | Eudyna Devices Inc. | Semiconductor device and method of manufacturing the same |
JP4516538B2 (ja) * | 2006-03-01 | 2010-08-04 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
JP2007234912A (ja) * | 2006-03-01 | 2007-09-13 | Eudyna Devices Inc | 半導体装置およびその製造方法 |
JP2008226962A (ja) * | 2007-03-09 | 2008-09-25 | Sumitomo Chemical Co Ltd | 半導体発光素子およびその製造方法 |
US8071482B2 (en) | 2007-05-21 | 2011-12-06 | Fuji Electric Co., Ltd. | Manufacturing method of a silicon carbide semiconductor device |
US7829919B2 (en) | 2008-03-31 | 2010-11-09 | Kabushiki Kaisha Toshiba | Semiconductor device |
US8084793B2 (en) | 2008-04-03 | 2011-12-27 | Kabushiki Kaisha Toshiba | Microwave semiconductor device using compound semiconductor and method for manufacturing the same |
US8338866B2 (en) | 2008-04-03 | 2012-12-25 | Kabushiki Kaisha Toshiba | Microwave semiconductor device using compound semiconductor and method for manufacturing the same |
JP2011096700A (ja) | 2009-10-27 | 2011-05-12 | Sumitomo Precision Prod Co Ltd | プラズマエッチング方法 |
US8673781B2 (en) | 2009-10-27 | 2014-03-18 | Sumitomo Precision Products Co., Ltd. | Plasma etching method |
US8541298B2 (en) | 2010-07-21 | 2013-09-24 | Sumitomo Electric Device Innovations, Inc. | Method for fabricating semiconductor device |
JP7258719B2 (ja) | 2019-10-24 | 2023-04-17 | 株式会社ノリタケカンパニーリミテド | ダイヤモンドドレッサ |
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JP4030982B2 (ja) | 2008-01-09 |
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