JP2005285910A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem, wherein the distance up to the second base electrode of the base region, near the center of a second emitter electrode, is large and drawing of carrier is delayed in a semiconductor device, including a ladder-shaped first base electrode, a narrow and longer first emitter electrode, a flat type second base electrode, and a second emitter electrode in which the bonding region can be ensured and the wire-bonding location is effectively arranged for the first emitter electrode. <P>SOLUTION: In the semiconductor device wherein a base and an emitter terminals are guided to a side of chip, the flat second emitter electrode is provided, and the first emitter electrode is extended vertically for the chip side where an external terminal is allocated; and a projected part of the second base electrode is provided near the center of the second emitter electrode. Accordingly, the base region of the cell near the center of the second emitter electrode can be provided adjacent to the second base electrode. Consequently, emitter resistance can be lowered, and drawing rate of the carrier of the base region can be improved. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that reduces the distance from a wire-bonded electrode to a base region of a cell and realizes high-speed operation of a transistor.

  A conventional semiconductor device will be described with reference to FIG. 4 by taking an npn transistor as an example.

  4A is a schematic diagram of the entire semiconductor element 100, FIG. 4B is a plan view of the first-layer electrode structure, and FIG. 4C is a cross-sectional view of FIG. FIG.

A collector region 52 is provided on the n + -type silicon semiconductor substrate 51 by, for example, laminating an n-type epitaxial layer. A base region 53 that is a p-type impurity region is provided on the surface of the collector region 52, and an emitter region 54 is formed on the surface of the base region 53 by diffusing n ⁺ -type impurities in a lattice shape. As a result, the base regions 53 are separated into island shapes and are alternately arranged with the emitter regions 54. It is to be noted that the island structure is separated from the surface structure, and the base region 53 formed deeper than the emitter region 54 is one continuous region in a deep region.

  A transistor formed of the base region divided into islands and the emitter region around the island is hereinafter referred to as a cell, and a region where a large number of cells are arranged is referred to as an operation region 58.

  Each of the base electrode and the emitter electrode connected to the base region 53 and the emitter region 54 has a two-layer structure.

  The first base electrode 56 which is the first layer is provided in an island shape or a strip shape, and is in contact with the base region 53 via the first base contact hole BC1 provided in the first insulating film 25. The first emitter electrode 57 is provided in a lattice shape and is in contact with the emitter region 54 through the first emitter contact hole EC1 provided in the first insulating film 25.

  A second base electrode 66 and a second emitter electrode 67 which are second layers are provided on the first base electrode 56 and the emitter electrode 57, and a second base contact hole (here, the second insulating film 26). And a second emitter contact hole EC2 (not shown here) for connection.

  The second base electrode 66 is provided on and in contact with a part of all the island-shaped first base electrodes 56 and the strip-shaped first base electrodes 56. The second emitter electrode 67 is provided above the strip-shaped first base electrode 56 and is in contact with the first emitter electrode 57.

As described above, the second base electrode 66 and the second emitter electrode 67 are shaped so as to cover the first layer electrode in a flat plate shape and wire bonded to these second layer electrodes, thereby enabling wire bonding. The versatility at the time of assembly increases. In addition, since the second base electrode 66 and the second emitter electrode 67 are adjacent to each other only on one side of the respective rectangles, the mask misalignment and the separation distance for obtaining a desired resist pattern are limited to this portion. What is necessary is just to consider (for example, refer patent document 1).
JP 2000-40703 A

  FIG. 5 shows a case where the semiconductor chip 100 is mounted.

  In the assembly process, for example, as shown in FIG. 5A, there are cases where both the base and emitter terminals are arranged on one side of the chip (in the figure, the lower side of the chip). In such a case, since the external terminals (for example, leads) 200 arranged along one chip side are connected to the second emitter electrode 67 and the second base electrode 66, a flat electrode structure can be used. It can be connected by the bonding wire 150 as shown.

  Here, it is desirable to reduce the emitter resistance in order to improve the characteristics of the bipolar transistor. For this reason, for example, the area of the second emitter electrode 67 is ensured to be large, or the bonding wire is made as short as possible.

  In particular, as the package becomes thinner, there is a desire to reduce the bonding wire loop. At this time, the wire bond position may be near the end of the chip as shown in the figure so that the low loop does not contact the end of the chip.

  However, the current path portion has a two-layer portion of the first emitter electrode 57 and the second emitter electrode 67 and a one-layer portion of only the second emitter electrode 67. When the wire bond position is at the chip end, for example, in the figure The emitter resistance from the first emitter electrode 57 on the upper side to the wire bond position is increased. For this reason, there has been a problem that the emitter resistance is not reduced or the chip is not thinned.

  Therefore, in such a case, the electrode of the second layer is formed into a flat plate shape, and the distance between the first emitter electrode 57 of the first layer and the bonding wire 150 is as short as possible as shown by the broken line in FIG. Also, the first emitter electrode 57 may be formed in two layers with the second emitter electrode, and the first emitter electrode 57 may be formed in a direction perpendicular to the chip side (upper side or lower side in the figure) where the external terminal 200 is disposed.

  FIG. 5C is a partially enlarged view of FIG. 5B, showing the first-layer electrode structure with a solid line, and the second-layer electrode structure with an alternate long and short dash line.

  The first base electrode 56 below the second emitter electrode 67 is continuous through, for example, a plurality of island-shaped base regions 53 arranged in the vertical direction in the drawing and a first base contact hole BC1 provided in the first insulating film. Then, they are bundled outside the operation region 58 to form a ladder-like pattern, and extend to the second base electrode 66 side through the second base contact hole BC2 provided in the second insulating film. Contact the electrode 66. An island-shaped first base electrode 56 is provided below the second base electrode 66 and is in contact with the second base electrode 66 through the second base contact hole BC2.

  The first emitter electrode is provided in a strip shape below the second emitter electrode 67 and is provided in a lattice shape below the second base electrode 66. Some of them are continuous and contact the second emitter electrode 67 through the second emitter contact hole EC2 provided in the second insulating film.

  The two layers of the first emitter electrode and the second emitter electrode can be connected to the wire bond position, and even when wire bonding is performed at the chip end, the emitter resistance to the first emitter electrode 57 farthest from the wire bond position is reduced. Can be reduced. Further, the bonding wire can be shortened as shown in FIG. 5A, which can contribute to the reduction of the emitter resistance. Further, since the bonding wire loop can be lowered, it can be mounted on a thin package.

  However, in this case, the first base electrode 56 disposed in parallel with the first emitter electrode 57 below the second emitter electrode 67 is bundled outside the operation region 58 and connected to the second base electrode 66. That is, in the cell C, for example, the base region 53 and the second base electrode 66 are compared with the base region 53 directly connected to the second base electrode 66 below the second base electrode 66 via the second base contact hole BC2. The distance L2 is increased, and the extraction of minority carriers in the base region when the transistor is turned off is delayed, which causes a problem that prevents high-speed operation.

  The present invention has been made in view of the various problems described above. First, a one-conductivity-type semiconductor substrate serving as a collector region, a reverse-conductivity-type base region provided on the substrate, and the base An emitter region of one conductivity type provided in a grid pattern on the surface of the region, a first base electrode in contact with the base region, a first emitter electrode in contact with the emitter region, the first base electrode, and the first base electrode One second base electrode provided on the emitter electrode via an insulating film and connected to the first base electrode, and provided on the first base electrode and the first emitter electrode via the insulating film. One second emitter electrode connected to one emitter electrode, and a plurality of first base electrodes and first emitter electrodes below the second emitter electrode are arranged in parallel, One base electrode is bundled at an end and connected to the second base electrode, and the second base electrode separates a part of the second emitter electrode and is orthogonal to the parallel first base and emitter electrodes. This problem is solved by having a projecting portion extending in the direction.

  Further, the first emitter electrode below the second base electrode has a lattice shape.

  In addition, the region separated by the protrusion has at least an area to which the connection means connected to the second emitter electrode can be fixed.

  Second, a semiconductor substrate is provided with a collector region, a base region, and an emitter region, a first base electrode that contacts the base region, a first emitter electrode that contacts the emitter region, the first base electrode, and the first emitter A semiconductor chip having a second base electrode and a second emitter electrode provided on the electrode via an insulating film; a base terminal and an emitter terminal arranged along one side of the semiconductor chip; and the base terminal And connecting means for connecting the second base electrode and the emitter terminal to the second emitter electrode, respectively, and the first base electrode and the first emitter electrode below the second emitter electrode are on the one side. The second base electrode is a protrusion that separates a part of the second emitter electrode and extends in parallel with the one side. Part solves by having.

  The connecting means is fixed to the vicinity of the end of the semiconductor chip along the one side.

  In addition, a part of the second emitter electrode is substantially evenly separated by the protruding portion.

  Further, the insulating film under the projecting portion is provided with a contact hole that contacts the first base electrode.

  According to the present invention, the following effects can be obtained.

  First, by providing a protrusion on the second base electrode and providing the first base contact hole BC1 and the second base contact hole BC2 on the protrusion, the cell C that has been far from the second base electrode in the past is provided. In addition, the distance from the base region of the surrounding cell to the second base electrode can be shortened. Thus, minority carriers can be extracted quickly from the base region when the transistor is off, and the speed of the transistor can be increased.

  Second, by separating a part of the second emitter electrode almost uniformly by the protrusion, the difference in distance from the base region of each cell to the second base electrode can be reduced as a whole. As a result, minority carrier extraction time variations can be suppressed, which is advantageous for high-speed operation.

  Thirdly, wire bonding can be performed at the chip end, which can contribute to thinning of the package.

  The embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3 by taking an npn bipolar transistor as an example.

  FIG. 1 shows a structure of a semiconductor device 10 according to an embodiment of the present invention. FIG. 1A is a plan view showing a second-layer electrode structure, and FIG. 1B is a plan view showing a first-layer electrode structure and a diffusion region.

  The npn-type bipolar transistor 10 of this embodiment includes a collector region 2, a base region 3, an emitter region 4, a first base electrode 6, a first emitter electrode 7, a second base electrode 16, and a second emitter. It is comprised from the electrode 17 and the protrusion part 16a of the 2nd base electrode.

  The semiconductor substrate 1 is a high-concentration n + type semiconductor substrate, and a collector region 2 is provided thereon by, for example, growing an n-type epitaxial layer.

  Base region 3 is one p-type diffusion region provided on the surface of collector region 2. An emitter region 4 is formed on the surface of the base region 3 by diffusing n + -type impurities in a lattice pattern. As a result, the base region 3 is separated into island shapes shown in a square shape in the figure. It is to be noted that the island structure is separated from the surface structure, and the base region 3 formed deeper than the emitter region 4 is one continuous region in a deep region. A large number of cells formed by the base region 3 divided into island shapes and the emitter region 4 around the base region 3 are arranged to constitute the operation region 8.

  Each of the base electrode and the emitter electrode connected to the base region 3 and the emitter region 4 has a two-layer structure. Although not shown, the collector region 2 is electrically connected to the collector electrode.

  As shown in FIG. 1A, the second base electrode 16 and the second emitter electrode 17 which are the second layer are respectively provided on the first base electrode 6 and the first emitter electrode 7 via the second insulating film. Provided. The second base electrode 16 and the second emitter electrode 17 are disposed adjacent to each other, and the second base electrode 16 has a projecting portion 16a extending so as to separate a part of the second emitter electrode 17 substantially evenly. The second emitter electrode 17 has a shape surrounding the protrusion 16a, and is not completely divided by the protrusion 16a, but has a continuous flat plate shape.

  And it has the area | region isolate | separated by the substantially equal area, for example, the area | region isolate | separated above the protrusion part 16a, and the lower side. In the present specification, for convenience of explanation, the upper region is referred to as a separation region a, and the lower region is referred to as a separation region b. Here, the number of the protruding portions 16a is not limited to one, and a plurality of protruding portions 16a may be used. In this case, the regions separated by the protruding portions 16a are provided so as to be substantially uniform. Further, in the present embodiment, the case where the protruding portion 16a is provided so as to cover one row of the base region 3 will be described as an example. However, the present invention is not limited thereto, and a shape that continuously covers a plurality of rows may be used. However, the second emitter electrode 17 (separation regions a and b) separated by the protrusion 16a has at least an area to which a bonding wire can be fixed.

  As shown in FIG. 1B, the first base electrode 6 has two patterns. That is, the first base electrode 6 a having an island shape that overlaps the island-shaped base region 3 and a plurality of island-shaped base regions 3 are connected by, for example, vertical skewers, and the skewers are bundled outside the operation region 8. It is the 1st base electrode 6b of the pattern made into the shape of a ladder. The portion where the skewers are bundled extends to the lower side of the second base electrode 16.

  Below the second base electrode 16, an island-shaped first base electrode 6a is arranged, and below the second emitter electrode 17, a ladder-like first base electrode 6b is arranged. Each first base electrode 6 is in contact with the base region 3 through a first base contact hole BC1 provided in the first insulating film.

  The first emitter electrode 7 also has two patterns. That is, the strip-shaped first emitter electrode 7 a disposed between the ladder-shaped first base electrodes 6 b and the grid-patterned first emitter disposed between the island-shaped first base electrodes 6. The grid-shaped first emitter electrode 7b is connected to a part of the strip-shaped first emitter electrode 7a. Each first emitter electrode 7 is in contact with the emitter region 4 through a first emitter contact hole EC1 provided in the first insulating film.

  2A is a plan view in which FIGS. 1A and 1B are overlapped. 2B is a cross-sectional view taken along the line AA ′ in FIG. 2A, and FIG. 2C is a cross-sectional view taken along the line BB ′ in FIG. The electrodes are indicated by hatching.

  Below the second emitter electrode 17, the emitter region 4 is connected to the first emitter electrode 7 a via the first emitter contact hole EC 1 provided in the first insulating film 25, and is further provided in the second insulating film 26. The second emitter electrode 17 is connected via the emitter contact hole EC2. That is, below the second emitter electrode 17, the emitter region 4 is connected to the second emitter electrode 17 almost directly through the first and second emitter contact holes EC1 and EC2.

  The base region 3 below the second emitter electrode 17 is in contact with the first base electrode 6b via the first base contact hole BC1, and is bundled outside the operation region 8 and extends to the second base electrode side. The second base electrode 16 is brought into contact with the second base contact hole BC2.

  On the other hand, below the second base electrode 16, the emitter region 4 is in contact with the first emitter electrode 7b having a lattice pattern through the first emitter contact hole EC1. The first emitter electrode 7b is connected to the first emitter electrode 7a having a strip pattern, and is connected to the second emitter electrode 17 through the second emitter contact hole EC2.

  The base region 3 below the second base electrode 16 is in contact with the first base electrode 6a through the first base contact hole BC1, and the first base electrode 6a is in contact with the second base through the second base contact hole BC2. Contact the electrode 16. That is, below the second base electrode 16, the base region 3 is connected almost directly to the second base electrode 16 via the first and second base contact holes BC1 and BC2.

  In the present embodiment, it is sufficient if the second base electrode 16 has an area where wire bonds can be crimped, and the second emitter electrode 17 contributes to the reduction of the emitter resistance by increasing the occupied area as much as possible.

  Further, in the present embodiment, a protruding portion 16a is provided in which the second base electrode 16 extends in a direction orthogonal to the first base electrode 6b arranged in a ladder shape and the first emitter electrode 7a arranged in a strip shape. . The protrusion 16a extends on the first base electrode 6 in a range that does not completely divide the second emitter electrode 17. A second base contact hole BC2 is provided in a portion of the second insulating film 26 where the protrusion 16a overlaps the first base electrode 6b, and the second base electrode 16 (protrusion 16a) and the first base electrode 6b are provided. Connect. That is, in the protruding portion 16a, the base region 3 is connected to the second base electrode 16 almost directly through the first and second base contact holes BC1 and BC2.

  By doing in this way, the base region 3 of the cell arrange | positioned at the isolation | separation area | region a and the isolation | separation area | region b will approach the 2nd base electrode 16 (projection part 16a).

  That is, when attention is paid to the same cell C as in FIG. 5C, the distance between the base region 3 of the cell C that is in contact only with the first base contact hole BC1 and the second base electrode 16 (projecting portion 16a). L1 can be shortened. In addition, since the first base electrode 6b is evenly arranged by the protruding portion 16a, the difference in distance from each base region 3 to the second base electrode 16 can be reduced as a whole. Therefore, carriers are quickly extracted from the base region when the transistor is off, and high-speed operation is possible.

  As an example, when comparing the distance between the cell C and the closest second base contact BC2, L1 of this embodiment can be shortened by about 75% compared to L2 in FIG. 5C, and the base carrier can be pulled out faster. This is advantageous for high-speed switching.

  FIG. 3 shows a case where the semiconductor element 10 is mounted on a package. The figure is an example, and leads are adopted as external terminals. However, the present invention is not limited to this, and the present invention can be similarly applied to, for example, a chip size package having a conductive pattern on an insulating substrate such as ceramic.

  As shown in the figure, a plurality of external terminals 200 are provided, for example, along one chip side (in the figure, the lower side of the chip) in the vicinity of the separation region b, and both the base terminal and the emitter terminal are derived as external terminals on the same side. In such mounting, the electrode structure of this embodiment is advantageous.

  That is, the bonding wire 150 is wire-bonded to the separation region b at the position of the broken line, and the second emitter electrode 17 and the second base electrode 16 are connected to the external terminal 200, respectively. In the present embodiment, when the bonding wire is fixed as shown in the figure, the strip-shaped first emitter electrode 7 is disposed perpendicular to one side of the chip 10 on which the external terminal 200 is disposed. That is, most of the first emitter electrode 7 linearly extends from directly below the bonding wire 150, so that it is possible to prevent an increase in the extraction resistance of the first emitter electrode 17.

  Therefore, the bonding wire 150 may be the minimum necessary length, and can contribute to the reduction of the emitter resistance together with the second emitter electrode 17 having a large area.

  Furthermore, since an increase in the extraction resistance of the first emitter electrode can be suppressed, wire bonding can be performed on the chip end, and the thin package can be mounted. Specifically, the wire bond loop can be lowered by setting the wire bond position to the end of the chip. For example, the package thickness can be reduced to about 0.75 mm.

  These effects are exactly the same when the external terminal 200 is provided on the separation region a side and wire bonding is performed on the separation region a side.

As described above, although the npn type bipolar transistor has been described in the present embodiment, it can be similarly applied to the pnp type, and the same effect can be obtained.

It is a top view for demonstrating this invention. It is (A) top view, (B) sectional view, and (C) sectional view for explaining the present invention. It is a top view for demonstrating this invention. It is (A) top view, (B) top view, and (C) sectional drawing for demonstrating a prior art. It is a top view for demonstrating a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Collector area | region 3 Base area | region 4 Emitter area | region 6 1st base electrode 7 1st emitter electrode 8 Operation | movement area | region 10 Semiconductor element 16 2nd base electrode 17 2nd emitter electrode 25 1st insulating film 26 2nd insulating film 51 Semiconductor Substrate 52 Collector region 53 Base region 54 Emitter region 56 First base electrode 57 First emitter electrode 58 Operating region 66 Second base electrode 67 Second emitter electrode 100 Semiconductor element 150 Bonding wire 200 External terminal BC1 First base contact hole EC1 First 1 emitter contact hole BC2 2nd base contact hole EC2 2nd emitter contact hole

Claims (7)

A one-conductivity type semiconductor substrate to be a collector region;
A reverse conductivity type base region provided on the substrate;
An emitter region of one conductivity type provided in a lattice pattern on the surface of the base region;
A first base electrode in contact with the base region;
A first emitter electrode in contact with the emitter region;
A second base electrode provided on the first base electrode and the first emitter electrode via an insulating film and connected to the first base electrode;
A second emitter electrode provided on the first base electrode and the first emitter electrode via the insulating film and connected to the first emitter electrode;
A plurality of first base electrodes and first emitter electrodes below the second emitter electrode are arranged in parallel, and the plurality of first base electrodes are bundled at an end portion and connected to the second base electrode,
The semiconductor device according to claim 1, wherein the second base electrode has a protruding portion that separates a part of the second emitter electrode and extends perpendicularly to the parallel first base and emitter electrodes.   2. The semiconductor device according to claim 1, wherein the first emitter electrode below the second base electrode has a lattice shape.   2. The semiconductor device according to claim 1, wherein the region separated by the protruding portion has an area to which at least connection means connected to the second emitter electrode can be fixed. A semiconductor substrate is provided with a collector region, a base region, and an emitter region, a first base electrode that contacts the base region, a first emitter electrode that contacts the emitter region, and insulation on the first base electrode and the first emitter electrode A semiconductor chip having a second base electrode and a second emitter electrode provided via a film;
A base terminal and an emitter terminal arranged along one side of the semiconductor chip;
Connecting means for connecting the base terminal and the second base electrode and the emitter terminal and the second emitter electrode, respectively;
The first base electrode and the first emitter electrode below the second emitter electrode are disposed perpendicular to the one side, and the second base electrode separates a part of the second emitter electrode and forms the one side. A semiconductor device having a protruding portion extending in parallel.   The semiconductor device according to claim 4, wherein the connection unit is fixed to the vicinity of an end portion of the semiconductor chip along the one side.   The semiconductor device according to claim 1, wherein a part of the second emitter electrode is substantially evenly separated by the protrusion.   The semiconductor device according to claim 1, wherein a contact hole that contacts the first base electrode is provided in the insulating film under the protruding portion.

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