CN1677689A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN1677689A CN1677689A CNA2005100045963A CN200510004596A CN1677689A CN 1677689 A CN1677689 A CN 1677689A CN A2005100045963 A CNA2005100045963 A CN A2005100045963A CN 200510004596 A CN200510004596 A CN 200510004596A CN 1677689 A CN1677689 A CN 1677689A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
- H02P21/04—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation specially adapted for very low speeds
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B66—HOISTING; LIFTING; HAULING
- B66D—CAPSTANS; WINCHES; TACKLES, e.g. PULLEY BLOCKS; HOISTS
- B66D5/00—Braking or detent devices characterised by application to lifting or hoisting gear, e.g. for controlling the lowering of loads
- B66D5/02—Crane, lift hoist, or winch brakes operating on drums, barrels, or ropes
- B66D5/24—Operating devices
- B66D5/30—Operating devices electrical
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
In a semiconductor device, which has a ladder-shaped first base electrode, a rectangular first emitter electrode, a plate-shaped second base electrode, and a second emitter electrode, a bonding area can be secured, and a wire bonding position for the first emitter electrode can be effectively arranged. However, the distance from a base area near the center of the second emitter electrode to the second base electrode is long, whereby a problem of slow drawing of carrier occurs. In the present invention, a semiconductor device is provided, in which a base electrode terminal and a emitter electrode terminal are led out from one side of a chip, and a second emitter electrode is set as plate-shaped, a first emitter electrode is extended perpendicularly to the side of the chip provided with the external terminals, and a salient of the second base electrode is provided near the area of a cell near the center of the second emitter electrode center of the second emitter electrode. Thereby, a base can be provided near the second base electrode, while the resistance of the emitter can be reduced, and the drawing speed of carrier in the base area can be increased.
Description
Technical field
The present invention relates to semiconductor device, particularly relate to reduction, realize the semiconductor device of transistor high speed from by the distance of the electrode of wire bonds to the base region of element.
Background technology
With reference to Fig. 4, be example explanation existing semiconductor devices with the npn transistor npn npn.
Fig. 4 (A) is the synoptic diagram of semiconductor element 100 integral body, and Fig. 4 (B) is the plane graph of ground floor electrode structure, and dotted line is a second layer electrode, and Fig. 4 (C) is the C-C line profile of Fig. 4 (B).
Lamination n type epitaxial loayer etc. for example is provided with collector region 52 on n+ type silicon semiconductor substrate 51.52 surfaces are provided as the base region 53 of p type extrinsic region in the collector region, and clathrate ground spreads n+ type impurity on base region 53 surfaces, forms emitter region 54.Thus, base region 53 is separated into island, and and emitter region 54 alternate configurations.In addition, what be separated into island is surface texture, and the base region 53 that forms deeply than emitter region 54 constitutes a continuous zone in dark zone.
Like this, be called as element below the transistor that is formed by the base region 53 that is divided into island and its peripheral emitter region 54, the zone that has disposed a plurality of elements is called as operating space 58.
The base electrode and the emitter electrode that are connected on base region 53 and the emitter region 54 form double-layer structure respectively.
On these first base electrodes 56 and emitter electrode 57, be provided as second base electrode 66 and second emitter electrode 67 of the second layer, and be situated between by the second base stage contact hole (not shown) that on second dielectric film 26, is provided with, the second emitter contact hole EC2 (not shown) connection at this at this.
Like this, second base electrode 66 and second emitter electrode 67 constitute the shape that tabulars cover the ground floor electrodes, by in the enterprising line lead welding of these second layer electrodes, but can enlarge the zone of wire bonds, the versatility when improving assembling.In addition, because second base electrode 66 and second emitter electrode 67 are only adjacent by one side of rectangle separately, so the contraposition deviation of mask or the spacing distance that is used to the resist pattern that obtains stipulating only consider that this part gets final product (for example with reference to patent documentation 1).
Patent documentation 1: the spy opens the 2000-40703 communique
Fig. 5 represents to install the state of described semiconductor chip 100.
In assembling procedure,, dispose the two-terminal of base stage B and emitter E in a limit of chip (in the drawings for constituting the limit of chip bottom) side sometimes for example as Fig. 5 (A).At this moment, because the outside terminal that will arrange along limit (for example lead-in wire) 200 is connected with second emitter electrode 67 and second base electrode 66,, then as shown in the figure, can pass through bonding wire 150 connections so be flat electrode structure as second layer electrode.
At this,, it is desirable to reduce emitter resistance for improving the characteristic of bipolar transistor.Therefore, the area of for example guaranteeing second emitter electrode 67 of needing efforts shortens bonding wire etc. more greatly or as far as possible.
In addition, especially be accompanied by the slimming of packaging part, and wish to reduce the ring of bonding wire.At this moment, as shown in the figure, sometimes the bonding wire position is positioned near the chip end, so that low ring contact chip end not.
But,, have two layer segments of first emitter electrode 57 and second emitter electrode 67 and a layer segment of second emitter electrode 67 only as the part of current path according to the position of the contact hole that connects the ground floor and the second layer.When the wire bonds position was the chip end, for example in the drawings, the emitter resistance from first emitter electrode 57 of last avris to the wire bonds position raise.Therefore, the reduction of emitter resistance or the slimming of chip have been hindered.
Therefore, at this moment,,, shorten first emitter electrode 57 of ground floor and the distance of bonding wire 150 as far as possible and get final product as the dotted line of Fig. 5 (B) as long as second layer electrode is constituted tabular.In addition, two-layer as long as first emitter electrode 57 and second emitter electrode 67 constitute, form first emitter electrode 57 and get final product in the vertical direction in chip limit (being top or bottom in the drawings) with respect to configuring external terminal 200.
Fig. 5 (C) is the partial enlarged drawing of Fig. 5 (B), and solid line is represented the electrode structure of ground floor, and chain-dotted line and hacures are represented the electrode structure of the second layer.
By such structure, can utilize first emitter electrode 57 and second emitter electrode, 67 two-layer electrodes to be connected to the wire bonds position.That is,, also can reduce from the wire bonds position emitter resistance to farthest first emitter electrode 57 even carry out wire bonds in the chip end.In addition, can shorten the bonding wire shown in Fig. 5 (A), reduce emitter resistance, further can reduce the ring of bonding wire, so can carry out installation to slim packaging part.
But, at this moment, below second emitter electrode 67 and first base electrode 56 of first emitter electrode, 57 configured in parallel outside operating space 58 by pack, be connected on second base electrode 66.That is, with base region 53 comparisons of the element C2 that directly is connected with second base electrode 66 by the second base stage contact hole BC2 of being situated between below second base electrode 66, for example on element C1, the distance L 2 that arrives the base region 53 and second base electrode 66 is elongated.The derivation of the minority carrier of base region became evening when transistor cut off, and had constituted the reason that harms high speed motion.
Summary of the invention
The present invention develops in view of described each problem points, and a first aspect of the present invention provides a kind of semiconductor device, and it comprises: a conductive-type semiconductor substrate, and it constitutes the collector region; Contrary conductivity type base region, it is set on the described substrate; One conductivity type emitter region, its by clathrate be arranged on the described base region surface; First base electrode, it contacts with described base region; First emitter electrode, it contacts with described emitter region; One second base electrode, its Jie is set on described first base electrode and described first emitter electrode by dielectric film, and is connected with described first base electrode; One second emitter electrode, its Jie is set on described first base electrode and described first emitter electrode by described dielectric film, and be connected with described first emitter electrode, first base electrode and first emitter electrode of described second emitter electrode below are disposed a plurality of concurrently, and these a plurality of first base electrodes are in the end pack, be connected on described second base electrode, described second base electrode has a part of separating described second emitter electrode and and described parallel first base stage and emitter electrode quadrature and the protuberance that extends.
In addition, described first emitter electrode below described second base electrode has lattice shape.
In addition, has the area that to fix the jockey that is connected with described second emitter electrode at least by described protuberance separate areas.
A second aspect of the present invention provides a kind of semiconductor device, it comprises: semiconductor chip, collector region, base region and emitter region are set on Semiconductor substrate, and it has first base electrode that contacts with described base region, first emitter electrode that contacts with described emitter region, being situated between is arranged on second base electrode, second emitter electrode on described first base electrode and first emitter electrode by dielectric film; Base terminal and emitter terminal are along a limit configuration of described semiconductor chip; Jockey, it connects described base terminal and described second base electrode and the described emitter terminal and second emitter electrode respectively, wherein, the vertical described limit of described first base electrode of described second emitter electrode below and first emitter electrode and disposing, described second base electrode have a part of separating described second emitter electrode and to the parallel protuberance that extends in a described limit.
In addition, described jockey is fixed near the end of the described semiconductor chip on a described limit.
In addition, utilize the part of described second emitter electrode of described protuberance roughly to be separated equably.
In addition, on the described dielectric film under the described protuberance, be provided with the contact hole that contacts with described first base electrode.
According to the present invention, can obtain following effect.
First, by on second base electrode, protuberance being set, and the first base stage contact hole BC1 and the second base stage contact hole BC2 are set on protuberance, can shorten at present from being positioned at away from the base region of the element C of the position of second base electrode and peripheral element thereof distance to second base electrode.Thus, drawing of the minority carrier of the base region in the time of can quickening the transistor disconnection can be sought transistorized high speed.
The second, by separating, the range difference integral body from the base region of each element to second base electrode can be reduced by a part of approximate equality ground of protuberance with second emitter electrode.Thus, can suppress the deviation of the time of drawing of minority carrier, so be favourable to high speed motion.
The 3rd, owing to can carry out wire-bonded in the chip end, so can make the packaging part slimming.
Description of drawings
Fig. 1 (A), (B) are used to illustrate plane graph of the present invention;
(A) is used to illustrate plane graph of the present invention among Fig. 2, (B) is profile, (C) is profile;
Fig. 3 is used to illustrate plane graph of the present invention;
(A) is the plane graph of prior art among Fig. 4, (B) is plane graph, (C) is profile;
Fig. 5 (A), (B), (C) are the plane graphs of explanation prior art.
Symbol description
1 Semiconductor substrate
2 collector regions
3 base regions
4 emitter regions
6 first base electrodes
7 first emitter electrodes
8 operating spaces
10 semiconductor elements
16 second base electrodes
17 second emitter electrodes
25 first dielectric films
26 second dielectric films
51 Semiconductor substrate
52 collector regions
53 base regions
54 emitter regions
56 first base electrodes
57 first emitter electrodes
58 operating spaces
66 second base electrodes
67 second emitter electrodes
100 semiconductor elements
150 bonding wires
200 outside terminals
The BC1 first base stage contact hole
The EC1 first emitter contact hole
The BC2 second base stage contact hole
The EC2 second emitter contact hole
Embodiment
With reference to Fig. 1～Fig. 3, be that example describes embodiments of the invention in detail with npn type bipolar transistor.
Fig. 1 represents the structure as the semiconductor device 10 of the embodiment of the invention.Fig. 1 (A) is the plane graph of expression second layer electrode structure, and Fig. 1 (B) is the plane graph of expression ground floor electrode structure and diffusion zone.
The npn type bipolar transistor 10 of present embodiment is made of the protuberance 16a of collector region 2, base region 3, emitter region 4, first base electrode 6, first emitter electrode 7, second base electrode 16, second emitter electrode 17, second base electrode.
Semiconductor substrate 1 is a high concentration n+ N-type semiconductor N substrate, for example makes growths such as n type epitaxial loayer thereon, and collector region 2 is set.
The base electrode and the emitter electrode that connect on base region 3 and emitter region 4 constitute double-layer structure respectively.In addition, collector region 2 is connected electrically on the collector electrode, and this point is omitted diagram.
As Fig. 1 (A), second base electrode 16 of the formation second layer and second emitter electrode 17 are situated between on first base electrode 6 and first emitter electrode 7 and respectively are provided with one by second dielectric film.Second base electrode 16 and second emitter electrode 17 are by the adjacency configuration, and second base electrode has the protuberance 16a of the extension that roughly part equalization of second emitter electrode 17 is separated.Second emitter electrode 17 is to surround protuberance 16a shape on every side, not by the complete disjunction of protuberance 16a, but a continuous tabular.
And, have zone that is separated in protuberance 16a upside for example and the zone that is separated in downside with the area of approximate equality.Convenient for the explanation of this specification, upper-side area is called separated region a, underside area is called separated region b.At this, protuberance 16a is not limited to one, also can be for a plurality of, at this moment, by protuberance 16a separate areas approximate equality.In addition, in the present embodiment, protuberance 16a is that example describes with the situation of the amount setting of covering base region 3 delegation, but is not limited thereto, and also can be the shape that covers multirow continuously.But, second base electrode 17 (separated region a, b) that separates by protuberance 16a but have the area of fixed engagement lead-in wire at least.
As Fig. 1 (B), first base electrode 6 is made of two patterns.That is, constitute by the first base electrode 6a and the first base electrode 6b, wherein, the first base electrode 6a is the island-shaped pattern overlapping with island base region 3, the first base electrode 6b for example connects a plurality of island base regions 3 with vertical polyphone, each string of pack outside operating space 8, the pattern of formation scalariform.The part of string pack is extended to second base electrode, 16 belows.
Second base electrode, 16 belows dispose the first base electrode 6a of island, and second emitter electrode, 17 belows dispose the first base electrode 6b of scalariform.And each first base electrode 6 is situated between and is contacted with base region 3 by the first base stage contact hole BC1 that is located on first dielectric film.
Fig. 2 (A) is the plane graph behind overlay chart 1 (A), (B).In addition, Fig. 2 (B) is the A-A line profile of Fig. 2 (A), and Fig. 2 C is the B-B line profile of Fig. 2 (A), and the electrode of the second layer is represented by hacures.
Below second emitter electrode 17, emitter region 4 is situated between and is connected on the first emitter electrode 7a by the first emitter contact hole EC1 that is arranged on first dielectric film 25, and further Jie is connected on second emitter electrode 17 by the second emitter contact hole EC2 that is arranged on second dielectric film 26.That is, below second emitter electrode 17, emitter region 4 is situated between and roughly is directly connected on second emitter electrode 17 by first and second emitter contact hole EC1, EC2.
In addition, the base region of second emitter electrode, 17 belows 3 is situated between and is contacted with the first base electrode 6b by the first base stage contact hole BC1, outside operating space 8 by pack.Then, extend to second base electrode, 16 sides, contact with second base electrode 16 by the second base stage contact hole BC2.
On the other hand, below second base electrode 16, emitter region 4 Jie are contacted by the first emitter electrode 7b of the first emitter contact hole EC1 and clathrate pattern.And this first emitter electrode 7b is connected with the first emitter electrode 7a of oblong-shaped pattern, and Jie is connected on second emitter electrode 17 by the second emitter contact hole EC2.
In addition, the base region 3 of second base electrode, 16 belows is situated between and is contacted with the first base electrode 6a by the first base stage contact hole BC1, and the first base electrode 6a is situated between and is contacted with second base electrode 16 by the second base stage contact hole BC2.That is, below second base electrode 16, base region 3 is situated between and roughly directly is connected with second base electrode 16 by first and second base stage contact hole BC1, BC2.
In the present embodiment, as long as but second base electrode 16 is guaranteed the area of crimping bonding wire with regard to enough (with reference to Fig. 3 broken circle mark), the occupied area of second emitter electrode 17 is increased, to reduce emitter resistance.
In addition, in the present embodiment, be provided with in direction and prolong the protuberance 16a that second base electrode 16 forms with the first emitter electrode 7a quadrature of the first base electrode 6b of scalariform configuration and oblong-shaped configuration.Protuberance 16a extends on the first base electrode 6b in the scope of not cutting apart second emitter electrode 17 fully.And, on second dielectric film (not shown) of the overlapping part of protuberance 16a and the first base electrode 6b, the second base stage contact hole BC2 is set at this, second base electrode 16 (protuberance 16a) is connected with the first base electrode 6b.That is, on protuberance 16a, base region 3 is situated between and roughly is directly connected on second base electrode 16 by first and second base stage contact hole BC1, BC2.
Thus, the base region 3 of the element that disposes on separated region a and separated region b is near second base electrode 16 (protuberance 16a).
That is, be conceived to and during the situation components identical C1 of Fig. 5 (C), only can shorten by the base region 3 of the element C1 of first base stage contact hole BC1 contact and the distance L 1 of second base electrode 16 (protuberance 16a).In addition, the first base electrode 6b is cut apart equably, also can whole be reduced from the range difference of each base region 3 to second base electrodes 16 by protuberance 16a.Therefore, when transistor disconnects, the charge carrier of base region draw acceleration, can carry out high speed motion.
As an example, comparing unit 1 and to the distance of the immediate second base stage contact hole BC2, then the distance L 1 of present embodiment can shorten about 75% than the distance L 2 of Fig. 5 (C), and drawing of base stage charge carrier accelerates, so help speed-sensitive switch.
Fig. 3 is illustrated on the packaging part situation when described semiconductor element 10 is installed.Among the figure, as an example, adopt lead-in wire as outside terminal, but be not limited thereto, the chip size package etc. that conductive pattern for example is set on insulating properties substrates such as pottery can be suitable for too.
As shown in the figure, follow the usual practice and be provided with a plurality of outside terminals 200 as near a chip limit the separated region b (the chip bottom among the figure), in addition, when being installed as base terminal B and emitter terminal E and all deriving, be favourable to the electrode structure of present embodiment as the outside terminal of this same avris.
That is, on separated region b,, second emitter electrode 17 and second base electrode 16 are connected respectively with outside terminal 200 at the position of broken circle mark wire bonds bonding wire 150.In the present embodiment, as shown in the figure, went between 150 o'clock, vertically dispose oblong-shaped first emitter electrode 7 with respect to a limit of the chip 10 that disposes outside terminal 200 in fixed engagement.That is, the major part of first emitter electrode 7 is straight-line extension under bonding wire 150, so can prevent the increase of the taking-up resistance of first emitter electrode 17.
Therefore, bonding wire 150 is that required minimal length gets final product, and can reduce emitter resistance together with large-area second emitter electrode 17.
In addition, owing to can suppress the increase of the taking-up resistance of first emitter electrode,, can be installed on the slim packaging part so can carry out wire-bonded in the chip end.Specifically, be positioned at the chip end, can reduce the ring of wire-bonded, for example can make the packaging part thin thickness to the 0.75mm by making the wire bonds position.
These effects have outside terminal 200 in separated region a side, and also identical when separated region a side is carried out wire-bonded.
More than, in the present embodiment, npn type bipolar transistor has been described, but also can have implemented equally the pnp type, obtain identical effect.
Claims (6)
1, a kind of semiconductor device is characterized in that, comprising: a conductive-type semiconductor substrate, and it constitutes the collector region; Contrary conductivity type base region, it is set on the described substrate; One conductivity type emitter region, its by clathrate be arranged on the described base region surface; First base electrode, it contacts with described base region; First emitter electrode, it contacts with described emitter region; One second base electrode, its Jie is set on described first base electrode and described first emitter electrode by dielectric film, and is connected with described first base electrode; One second emitter electrode, its Jie is set on described first base electrode and described first emitter electrode by described dielectric film, and be connected with described first emitter electrode, first base electrode and first emitter electrode of described second emitter electrode below are disposed a plurality of concurrently, these a plurality of first base electrodes are in the end pack, be connected on described second base electrode, described second base electrode has a part of separating described second emitter electrode and and described parallel first base electrode and the first emitter electrode quadrature and the protuberance that extends.
2, semiconductor device as claimed in claim 1 is characterized in that, described first emitter electrode of described second base electrode below has lattice shape.
3, semiconductor device as claimed in claim 1 is characterized in that, by described ledge from after the zone have the area that can fix the jockey that is connected with described second emitter electrode at least.
4, a kind of semiconductor device, it is characterized in that, comprise: semiconductor chip, collector region, base region and emitter region are set on Semiconductor substrate, and it has first base electrode that contacts with described base region, first emitter electrode that contacts with described emitter region, being situated between is arranged on second base electrode, second emitter electrode on described first base electrode and first emitter electrode by dielectric film; Base terminal and emitter terminal are along a limit configuration of described semiconductor chip; Jockey, it connects described base terminal and described second base electrode and the described emitter terminal and second emitter electrode respectively, wherein, the vertical described limit of described first base electrode of described second emitter electrode below and first emitter electrode and disposing, described second base electrode have a part of separating described second emitter electrode and the parallel protuberance that extends along a described limit.
5, semiconductor device as claimed in claim 4 is characterized in that, described jockey is fixed near the end of the described semiconductor chip on a described limit.
6, as claim 1 or 4 described semiconductor devices, it is characterized in that, on the described dielectric film under the described protuberance, be provided with the contact hole that contacts with described first base electrode.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004094686A JP4425034B2 (en) | 2004-03-29 | 2004-03-29 | Semiconductor device |
| JP094686/2004 | 2004-03-29 | ||
| JP094686/04 | 2004-03-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1677689A true CN1677689A (en) | 2005-10-05 |
| CN100413088C CN100413088C (en) | 2008-08-20 |
Family
ID=35050090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100045963A Expired - Fee Related CN100413088C (en) | 2004-03-29 | 2005-01-18 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP4425034B2 (en) |
| KR (1) | KR100616395B1 (en) |
| CN (1) | CN100413088C (en) |
| TW (1) | TWI244208B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108347177A (en) * | 2016-12-28 | 2018-07-31 | 瑞萨电子株式会社 | Semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5341435B2 (en) | 2008-08-26 | 2013-11-13 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Semiconductor device |
| JP2010080925A (en) | 2008-08-26 | 2010-04-08 | Sanyo Electric Co Ltd | Semiconductor device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5138879A (en) * | 1974-09-27 | 1976-03-31 | Hitachi Ltd | |
| JP2912906B1 (en) * | 1998-03-30 | 1999-06-28 | エヌティティエレクトロニクス株式会社 | Semiconductor device |
| JP3510797B2 (en) * | 1998-07-24 | 2004-03-29 | 三洋電機株式会社 | Transistor electrode structure |
| JP3515473B2 (en) * | 2000-03-17 | 2004-04-05 | 三洋電機株式会社 | Semiconductor device |
| JP2003069015A (en) * | 2001-08-22 | 2003-03-07 | Sanyo Electric Co Ltd | Semiconductor device |
-
2004
- 2004-03-29 JP JP2004094686A patent/JP4425034B2/en not_active Expired - Fee Related
- 2004-11-05 TW TW093133776A patent/TWI244208B/en not_active IP Right Cessation
-
2005
- 2005-01-18 CN CNB2005100045963A patent/CN100413088C/en not_active Expired - Fee Related
- 2005-02-21 KR KR1020050013947A patent/KR100616395B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108347177A (en) * | 2016-12-28 | 2018-07-31 | 瑞萨电子株式会社 | Semiconductor device |
| CN108347177B (en) * | 2016-12-28 | 2021-09-07 | 瑞萨电子株式会社 | Semiconductor device with a plurality of semiconductor chips |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200532912A (en) | 2005-10-01 |
| KR20060042135A (en) | 2006-05-12 |
| JP4425034B2 (en) | 2010-03-03 |
| TWI244208B (en) | 2005-11-21 |
| CN100413088C (en) | 2008-08-20 |
| KR100616395B1 (en) | 2006-08-29 |
| JP2005285910A (en) | 2005-10-13 |
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