JP3063790B2 - Transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor having a base island (mesh emitter) structure.

[0002]

2. Description of the Related Art As is well known, a semiconductor device has a safe operation area (hereinafter referred to as AS).
O) is desirable. Switching transistors may be used under severe conditions such as inductive load or reverse bias between base and emitter at turn-off.
There are strict requirements for

A power switching transistor chip employs a so-called base island structure in which a large number of small-area base regions are arranged in an island shape in order to obtain various electrical characteristics. When a reverse bias ASO test is performed on this type of conventional transistor, the distribution of the breakdown current value varies, and there is a transistor that breaks down in a current region considerably smaller than a desired breakdown current value level (actual breakdown level). did.

Accordingly, an object of the present invention is to provide a transistor capable of stably obtaining a reverse bias ASO characteristic at a high level.

[0005]

The present invention for achieving the above object will be described with reference to the drawings of the embodiments, in which a collector region 2 and a base region 3 adjacent to the collector region 2 are formed. A mesh-type emitter region 4 which is arranged adjacent to the base region 3 on the side opposite to the collector region 2 and is exposed on the surface of the semiconductor substrate 1; The base region 3 has an island-like portion 3 exposed in the mesh-type emitter region 4 on the surface of the semiconductor substrate 1 and the mesh-type emitter region. 4 has an annular portion 3b exposed so as to surround the mesh-type emitter region 4. The width W1 of the frame-shaped portion 4a of the mesh-type emitter region 4 is
The width is smaller than the width W2 of the mesh portion 4b.

[0006] First and second connecting portions for connecting a base electrode to the island portion 3a and the annular portion 3b of the base region 3 are provided.
It is preferable that the openings 6 and 8 be provided in the insulating film 5 and the second opening 8 be larger than the opening area of the first opening 6.

[0007]

According to the first aspect of the present invention, the emitter region of the peripheral cell (unit small transistor) is reduced, the emitter current can be made smaller than that of the internal cell, and the base resistance below this emitter region is also reduced. For this reason, the loss of the peripheral cell is reduced, and a favorable reverse bias ASO can be stably obtained. According to the third aspect of the present invention, the outer second
The base contact opening 8 has an opening area larger than that of the inner first base contact opening 6, so that the speed of extracting the stored carriers when the peripheral cell is OFF is improved. As a result, the loss of the peripheral cells is reduced, and good reverse bias characteristics can be stably obtained. According to the second aspect of the present invention, the above two effects can be obtained in combination, and a good reverse bias ASO characteristic can be obtained more stably.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a power switching transistor according to an embodiment of the present invention will be described with reference to FIGS. As is clear from FIG. 1 showing the surface of the substrate 1 from which the insulating film and the electrodes have been removed from the upper surface of the semiconductor substrate 1 and FIG. 2 showing the cross section of the completed transistor chip, the transistor chip of the present embodiment is an n-type transistor. A P-type (second conductivity type) base region 3 is formed therein by, for example, boron diffusion, and a number of n @ + -type collector regions 2 are formed in the base region 3. Is formed by, for example, phosphorus diffusion. This chip has a structure called a mesh emitter or a base island in which an emitter region 4 is formed in a mesh shape, that is, a lattice shape, and a base region 3 is formed in an island shape relatively. A large number of island-shaped base regions 3a have the same size as a planar quadrilateral and are regularly arranged in a grid pattern. The outer peripheral edge of the emitter region 4 is partially spaced inward from the edge of the semiconductor substrate 1 at the center of two opposing sides, and the outer annular base region 3b is partially projected. The projecting portion is a portion for forming an electrode region (bonding pad portion) for connecting the emitter lead member and the base lead member via the insulating film 5 above the projecting portion. Further, in the transistor chip of this embodiment, FIGS.
As is clear from FIG. 5, the width of the frame-shaped portion 4a of the mesh-type emitter region 4 (the annular base region 3b and the island-shaped base region 3
The width W1 between the island-like base regions 3a (the width of the mesh portion 4b of the emitter region 4) W2 is smaller than the width W2. As an example of the width W1 and the width W2, W
1 is 80 μm and W2 is 100 μm.

FIG. 3 shows the surface of the substrate 1 with only the insulating film 5 formed on the upper surface of the semiconductor substrate 1 and the electrodes and the like removed. As shown, a large number of openings are formed in the insulating film 5. The first base contact opening 6 arranged corresponding to the central portion of the island-shaped base region 3a has a square planar shape. A large number of first base contact openings 6 have the same area, and each of the island-shaped base regions 3a
Is exposed. The emitter contact opening 7 provided above the frame-shaped portion 4a and the mesh-shaped portion 4b of the emitter region 4 has a square planar shape and is formed smaller than the opening area of the first base contact opening 6. ing. Many emitter contact openings 7 of the same area
A virtual line connecting the centers of the first and second base contact openings 6 and 8 at the center and outside of a virtual rectangle connecting the centers of the first base contact openings 6 of the four island-shaped base regions 3a surrounding the center. It is located in the center of the rectangle. From the emitter contact opening 7 to the emitter region 4
Is partially exposed. Numerous annular base regions 3b
The second base contact openings 8 respectively disposed above the first base contact openings 8 are formed in a planar rectangular shape with the same opening area, and have an opening area larger than the first base contact openings 6. The distance between the second base contact opening 8 and the emitter contact opening 7 arranged at the outermost periphery is substantially constant at all.

As shown in FIG. 2, an emitter connection conductor 9 and a base connection conductor 10 are formed above the insulating film 5, and the emitter region is formed through the emitter contact opening 7 and the base contact opening 6 or 8, respectively. 4 and the base region 3. The conductor 9 for emitter connection and the conductor 10 for base connection are
Above the inside protruding portion b, it is electrically connected to the emitter connection electrode and the base connection electrode.

FIG. 4 shows the relationship between the breakdown current value and the number of breakdowns when a reverse bias ASO test is performed on the transistor of this embodiment and a conventional transistor. According to the transistor of this embodiment, the breakdown current region shifts to a current level sufficiently larger than the inspection standard (desired breakdown current level) as compared with the conventional transistor, and it can be seen that stable performance can be obtained. In other words, according to the transistor of this embodiment, the safe operation area can be extended to the high voltage side.

The reason why the above-described remarkable effects are obtained by the transistor of this embodiment is considered as follows. In the conventional transistor, the loss is large in the cell region on the outer peripheral side, and this portion becomes a weak point in the reverse bias ASO. It has been confirmed that it has been destroyed near the area). On the other hand, in the transistor of this embodiment, the outer frame portion 4a of the emitter region 4 is narrower than the inner mesh portion 4b, and the emitter area of the outer cell is smaller than the emitter area of the inner cell. ing. Therefore, the emitter current of the outer cell can be made smaller than that of the inner cell. That is, the amount of accumulated carriers on the outer cell side decreases. Further, by making the outer frame-shaped portion 4a narrower and increasing the area of the second base contact opening 8, the base resistance of the outer cell indicated by R in FIG. 2 decreases, and the base contact resistance also decreases. I do. For this reason, the above-mentioned accumulated carrier can be extracted at high speed through the base. As a result, the OFF speed of the peripheral cell when the transistor is switched from ON to OFF is increased, the loss in the peripheral cell is reduced, and good reverse bias ASO characteristics can be stably obtained.

[0013]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) For W1 and W2, the width ratio W1 / W2 should be 0.9 or less, preferably 0.8 or less so that the effects of the present invention can be obtained well. However, in consideration of the mask alignment error and the size of the emitter contact opening, it is preferable that W1 / W2 be 0.6 or more at a practical level. (2) As for the area S1 of the opening 8 and the area S2 of the opening 6, the area ratio S1 / S2 is preferably 1.5 or more, more preferably 2 or more so that the effect of the present invention can be obtained. (3) A narrow portion may be partially present in a part of the inner net-like portion 4b. (4) When a high-level switching speed is not required, a connection conductor having a relatively large resistance is connected to the first base contact opening 6 and a resistance having a relatively high resistance is connected to the second base contact opening 8. May be connected to thereby further reduce the loss variation between cells. (5) The distance between the second base contact opening 8 and the emitter contact opening 7 is changed to the emitter contact opening 7.
And the distance between the second base contact opening 6 and the second base contact opening 6 may be made smaller to further improve the carrier accumulation and extraction effect of the peripheral cell. (6) The effect can be obtained even when applied to a transistor in which the area of the opening 7 for the emitter contact is formed non-uniformly. (7) The plurality of second base contact openings 8 arranged along the direction in which the base connection conductor 10 extends may be continuous with each other. That is, instead of the nine second base contact openings 8 in the uppermost row and the lowermost row in FIG.
It can be a longitudinal opening extending in two strips.

[0014]

As described above, according to the present invention, the reverse bias ASO can be widened.

[Brief description of the drawings]

FIG. 1 is a plan view showing a surface of a semiconductor substrate of a transistor according to an embodiment of the present invention.

FIG. 2 is an enlarged sectional view of a portion corresponding to line AA in FIG.

FIG. 3 is a plan view showing a state in which an insulating film having an opening is provided in the semiconductor substrate of FIG. 1;

FIG. 4 is a diagram showing the relationship between the breakdown current and the number of breakdowns of the transistor of this embodiment and the conventional transistor.

[Explanation of symbols]

 3a island-shaped base region 3b annular base region 4 emitter region 4a frame-shaped portion 4b net-shaped portion 6 first base contact opening 7 emitter contact opening 8 second base contact opening

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/331 H01L 29/73

Claims (3)

(57) [Claims] 1. A collector region (2), a base region (3) adjacent to said collector region (2), and a base region (3) adjacent to said collector region (2) on the side opposite to said collector region (2). A mesh-type emitter region (4) disposed and exposed on the surface of the semiconductor substrate (1);
The mesh type emitter region (4) has a frame-like portion (4a).
And a net-like portion (4b) therein, wherein the base region (3) is an island-like portion (3a) exposed in an island shape in the mesh type emitter region (4) on the surface of the semiconductor substrate (1). ) And an annular portion (3b) exposed to surround the mesh-type emitter region (4), and the width (W1) of the frame-shaped portion (4a) of the mesh-type emitter region (4) is the same A transistor having a width (W2) smaller than the width (W2) of the mesh portion (4b) of the mold emitter region (4). 2. An insulating film (5) is formed on a surface of said semiconductor substrate (1), said insulating film (5) being an emitter for partially exposing said mesh type emitter region (4). A first base contact opening (6) and the base region (3) for partially exposing the contact opening (7) and the island portion (3a) of the base region (3).
A second base contact opening (8) for partially exposing the annular portion (3b) of the first base contact opening (8), wherein the second base contact opening (8) is the first base contact opening (6). The mesh-type emitter region (4) is electrically connected to the emitter connection conductor (9) through the emitter contact opening (7), and has an opening area larger than that of the base region (3). Island (3
a) and the annular portion (3b) are electrically connected to the base connection conductor (10) through the first base contact opening (6) and the second base contact opening (8), respectively. The transistor according to claim 1, wherein: 3. A collector region (2), a base region (3) adjacent to the collector region (2), and a base region (3) arranged adjacent to the base region (3) on the side opposite to the collector region (2). And a mesh-type emitter region exposed on the surface of the semiconductor substrate (1). The mesh-type emitter region (4) has a frame-like portion (4a) and a mesh-like portion (4b) therein. The base region (3) is an island-shaped portion (3a) exposed in the mesh-type emitter region (4) on the surface of the semiconductor substrate (1).
And an annular portion (3b) exposed so as to surround the mesh type emitter region (4). An insulating film (5) is formed on a surface of the semiconductor substrate (1). (5) An emitter contact opening (7) for partially exposing the mesh-type emitter region (4) and a first base contact for partially exposing the island-shaped portion (3a) of the base region (3). And a second base contact opening (8) for partially exposing the annular portion (3b) of the base region (3), and the second base contact opening (8). Has an opening area larger than the first base contact opening (6),
The mesh type emitter region (4) is connected to the emitter connection conductor (9) through the emitter contact opening (7).
And the island-shaped portion (3a) and the annular portion (3b) of the base region (3) are respectively connected to the first region.
Through the base contact opening (6) and the second base contact opening (8).
0) electrically connected to the transistor.