JPS58158965A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58158965A
JPS58158965A JP57040799A JP4079982A JPS58158965A JP S58158965 A JPS58158965 A JP S58158965A JP 57040799 A JP57040799 A JP 57040799A JP 4079982 A JP4079982 A JP 4079982A JP S58158965 A JPS58158965 A JP S58158965A
Authority
JP
Japan
Prior art keywords
base
emitter
substrate
comb
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57040799A
Other languages
Japanese (ja)
Inventor
Fujihiko Inomata
猪又 藤彦
Yukio Hayashi
幸雄 林
Ryoichi Ono
小野 良一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57040799A priority Critical patent/JPS58158965A/en
Publication of JPS58158965A publication Critical patent/JPS58158965A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain a transistor of ultrafine size and high performance by forming an external terminal of electrodes as bonding pad on a pair of diagonal lines of a substrate and forming a pectinated active part and ohmic electrodes along the periphery of the substrate. CONSTITUTION:Diffused pattern of base and emitter and electrodes 4, 5 are formed at both sides along X- and Y-directions of a chip, and bonding pads 6, 7 lead from the electrodes have centers on a pair of diagonal lines of the chip. That is, the OF line of the substrate is used as a reference line, the main lines of the base and emitter are disposed perpendicularly or in parallel with the side of the pellet with matching seals AT1, AT2 formed at both ends of the substrate, and an interval P is formed in small size. The resistance between the base and the emitter is reduced due to the reduction of the interval P, the noise is reduced, power gain is raised, and a base area is reduced, thereby reducing the bonding capacity between the base the collector, high frequency characteristics are improved, and the improper shortcircuit between the emitter and the base can be reduced.

Description

【発明の詳細な説明】 本発明は高周波用のトランジスタに関する。[Detailed description of the invention] The present invention relates to a high frequency transistor.

高周波用のトランジスタにおいては、第1図。Fig. 1 shows a high frequency transistor.

第1A図に示1ように例えばコレクタとなるNWS−基
板の主表面にP型ベース2とN+ Julエミッタ3の
細長形の拡散領域を交互にクシの歯状に形成し、各ベー
ス領域と各エミッタ領域に対しオーミック接触させた人
!膜等からなる電極4,5を基板の対角線方向に導いて
ボンディングパット6゜7 としている。これまでの構
造では同図のようにり/の歯を構成するベース乃至エミ
ッタのパターンを基板の対角線方向にそって、又はこれ
と直角方向に配置していた。
As shown in FIG. 1A, elongated diffusion regions of a P-type base 2 and an N+ Jul emitter 3 are alternately formed in the shape of a comb on the main surface of an NWS-substrate that becomes a collector, and each base region and each The person who made ohmic contact with the emitter region! Electrodes 4 and 5 made of films or the like are guided diagonally across the substrate to form bonding pads 6.7. In the conventional structure, as shown in the same figure, the base and emitter patterns constituting the teeth have been arranged along the diagonal direction of the substrate or in the direction perpendicular thereto.

これIエベレノト(半導体基板)の面積を有効に活用す
るためになるべく小さいペレットサイズにトランジスタ
の能動領域とポンディングパッドをむだなく配置し、製
造コストの低減を図ることに主眼を置いてなされたから
である。
This was done with the main focus on reducing manufacturing costs by arranging the active area of the transistor and the bonding pad in the smallest possible pellet size in order to effectively utilize the area of the semiconductor substrate. be.

しかし最近開発されている高周波トランジスタのように
装置容量を小さくする目的でベース・エミッタ間隔をせ
まく、したがって(しの歯状に形成したベース・エミッ
タ電極の間隔(ピッチP)をせまくシ、ホトレジストマ
スクの位置合せ精度(ベースクラフトベース−エミッタ
・ベースコンタクト)が要求される半導体装置では、基
板辺に対して斜め(45°)のクシの歯状電極間隔の充
分な精度を出すことは困難である。
However, in order to reduce the device capacitance in recently developed high-frequency transistors, the distance between the base and emitter is narrowed. In semiconductor devices that require alignment accuracy (base craft base - emitter base contact), it is difficult to achieve sufficient accuracy in the spacing of comb-shaped electrodes diagonal (45°) to the substrate side. .

本発明は上記の欠点を取り除くべくなさtたものであり
、その目的はより高い周波数特性をもちかつ高い信頼性
をもつトランジスタの開発にある。
The present invention has been made to eliminate the above-mentioned drawbacks, and its purpose is to develop a transistor with higher frequency characteristics and higher reliability.

以下本発明を実施例にそって詳述する。The present invention will be described in detail below with reference to Examples.

11i2図に本発明による高周波トランジスタの電極配
置を示す平面パターンが示さnる。このトランジスタに
おいては、クシの書状電極を構成するベース4及びエミ
ッタ5の電極パターンは基板チップをウェハより切断す
るためのスクライブ方向、すなわちチップの両辺X、Y
方向にそりて又はこれと直角方向に形成されている。図
示されないがベース・エミッタの拡散パターンも当然基
板表面にX、Y方向に形成されている。一方、ベース−
エミッタ電極より導出されたポンディングパッド6.7
は基板チップの一つの対角線上にその中心上記実施例で
述べた本発明によれば下記の理由で前記発明の目的が達
成で挿るつ 半導体基板にベース・エミッタの拡散領域、電極バター
/を形成するにあたっては、半導体ウェハの形態でホト
レジスト処理による選択拡散1部分蒸着が成される。こ
のホトレジストのマスク合せ(アライメント)の際に第
3図に示すように半導体ウェハをオリエンテーシ嘗ンフ
ラット(OF)を基準線に合せておき、ウェハの両端位
置に設けたアライメントターゲット(AT、、AT、)
を見て合せるようにしている。このときの合せ精度が出
るのは左右上下は合せやすくずれが見やすい。
Figure 11i2 shows a plane pattern showing the electrode arrangement of the high frequency transistor according to the present invention. In this transistor, the electrode patterns of the base 4 and emitter 5, which constitute the letter electrodes of the comb, are arranged in the scribing direction for cutting the substrate chip from the wafer, that is, on both sides of the chip, X and Y.
It is formed warped in the direction or perpendicular to the direction. Although not shown, base-emitter diffusion patterns are naturally formed on the substrate surface in the X and Y directions. On the other hand, the base
Ponding pad 6.7 derived from emitter electrode
According to the invention described in the above embodiments, the object of the invention is achieved for the following reasons: By inserting the base-emitter diffusion region and the electrode butter into the semiconductor substrate, the center is located on one diagonal of the substrate chip. The formation involves selective diffusion single-portion deposition with photoresist treatment in the form of a semiconductor wafer. During this photoresist mask alignment, the orientation flat (OF) of the semiconductor wafer is aligned with the reference line as shown in Figure 3, and alignment targets (AT,... AT,)
I look at it and try to match it. At this time, the alignment accuracy is achieved because it is easy to align the left, right, top, and bottom, and it is easy to see discrepancies.

第1図のようにパターンの主線が斜め方向の場合は合せ
に<<、ずれの判別がつぎにくい。したがって、第4図
t8) 、 (b)に示すように、アライメントのずれ
の方向(blと能動部パターンのずれの方向tl)とが
一致せず、下記の問題点が発生する。(II  エミッ
J(電極パターン)とベース(E?パターン)が重なっ
て短絡する。(2)上記(1)のずれを考慮してエミッ
タとベースの間隔(P)を広げて設計することにより、
rbb′(ベース・エミッタ間抵抗)が上昇しNF(雑
音)、PG(パヮードイン)の低下となり、又ベース面
積の拡大からC8b(ペースコレクタ間接合容量)の上
昇、ひいては高周波特性の低下となった。
When the main lines of the pattern are diagonal as shown in FIG. 1, it is difficult to distinguish between << and deviation. Therefore, as shown in FIG. 4 t8), (b), the direction of alignment deviation (bl and the direction of deviation tl of the active part pattern) do not match, and the following problem occurs. (II. The emitter J (electrode pattern) and the base (E? pattern) overlap and cause a short circuit. (2) Taking into consideration the deviation in (1) above, by widening the spacing (P) between the emitter and the base,
rbb' (resistance between base and emitter) increased, NF (noise) and PG (padded in) decreased, and due to the expansion of the base area, C8b (junction capacitance between pace collector) increased, and high frequency characteristics deteriorated. .

しかし本発明のように能動部ベース・エミッタの主線を
ペレットの辺と直角又は平行に配置することによりパタ
ーンすれとアライメントずれが第4図(b)に一致し、
合せ精度を向上させることができ、エミッタ・ベース耐
圧シ目−トの低減ができるとともにベース・エミッタ間
隔Pを小さくしてNFの低下、PGの上昇、Cobの低
減が可能となる結果より高い周波性のトランジスタの開
発製造が可能となった。又、ポンディングパッドは基板
チップの対角線上に配置するから、基板表面を有効に利
用しチップ寸法の縮小を図ることができる。
However, by arranging the main lines of the active part base and emitter perpendicularly or parallel to the sides of the pellet as in the present invention, the pattern misalignment and misalignment match those shown in FIG. 4(b).
It is possible to improve the alignment accuracy, reduce the emitter-base breakdown voltage gap, and reduce the base-emitter spacing P to lower NF, increase PG, and reduce Cob, resulting in higher frequencies. This made it possible to develop and manufacture a transistor with a wide range of characteristics. Further, since the bonding pads are arranged diagonally on the substrate chip, the substrate surface can be effectively utilized and the chip size can be reduced.

本発明は特に微細系高周波トランジスタの歩留り向上に
極めて有効である。
The present invention is particularly effective in improving the yield of fine high-frequency transistors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は高周波トランジスタの一例の平面図、第1A図
は第1図におけるA−A視拡大断面図である。第2図は
本発明による高周波トランジスタの実施例を示す平面図
、第3図はホトレジストマスクアライメント時の半導体
ウェハを示す平面図、第4 Eta) 、 (b)はパ
ターンずれとアライメントスれを示す原理説明図である
。 1・・・Nm&、2・・・Pベース、3・・・N+ エ
キツタ、4・・・ベース電極、5・・・エミッタ電極、
6 、7・・・ポンディングパッド。 代理人 弁理士  薄 1)利 幸 第  1  図 第1A図 第  2  図 第  3f’4      第  4  図(と2−) θl
FIG. 1 is a plan view of an example of a high-frequency transistor, and FIG. 1A is an enlarged sectional view taken along line AA in FIG. FIG. 2 is a plan view showing an embodiment of a high-frequency transistor according to the present invention, FIG. 3 is a plan view showing a semiconductor wafer during photoresist mask alignment, and 4th Eta) and (b) show pattern deviation and alignment deviation. It is a principle explanatory diagram. 1...Nm&, 2...P base, 3...N+ emitter, 4...base electrode, 5...emitter electrode,
6, 7...ponding pad. Agent Patent Attorney Susuki 1) Toshiyuki 1 Figure 1A Figure 2 Figure 3f'4 Figure 4 (and 2-) θl

Claims (1)

【特許請求の範囲】 1、半導体基板の一生表面に導電製の異なる領域が交互
にクシの歯状となった能動部を形成し、上記領域に七粁
ぞnオーミック接触するクシ歯状の電極を形成した半導
体装置において、各電極の外端子をポンディングパッド
として基板の一つの対角線上に設ける一方、上記クシの
歯状の能動部及びこnに接触する電極を半導体基板の周
辺方向にそって形成したことを特徴とする半導体装置。 2、上記交互にクシの歯状に形成した能動領域はトラン
ジスタを構成するベース及びエミッタである特許請求の
範囲第1項に記載の半導体装置。 3、上記交互にクシの歯状に形成した能動領域は電界効
果トランジスタを構成するソース及びドレインである特
許請求の範囲第1項に記載の半導体装置。
[Scope of Claims] 1. A comb-toothed electrode in which different conductive regions alternately form a comb-toothed active part on the surface of a semiconductor substrate, and the comb-toothed electrode is in ohmic contact with the above regions. In the semiconductor device in which the outer terminal of each electrode is provided as a bonding pad on one diagonal line of the substrate, the comb-like active portion and the electrode in contact therewith are placed along the periphery of the semiconductor substrate. A semiconductor device characterized in that it is formed by 2. The semiconductor device according to claim 1, wherein the active regions formed alternately in the shape of comb teeth are a base and an emitter constituting a transistor. 3. The semiconductor device according to claim 1, wherein the active regions formed alternately in a comb-like shape are a source and a drain constituting a field effect transistor.
JP57040799A 1982-03-17 1982-03-17 Semiconductor device Pending JPS58158965A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57040799A JPS58158965A (en) 1982-03-17 1982-03-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57040799A JPS58158965A (en) 1982-03-17 1982-03-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58158965A true JPS58158965A (en) 1983-09-21

Family

ID=12590669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57040799A Pending JPS58158965A (en) 1982-03-17 1982-03-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58158965A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6239074A (en) * 1985-08-13 1987-02-20 Matsushita Electronics Corp Semiconductor device
US6046493A (en) * 1996-07-03 2000-04-04 U.S. Philips Corporation Semiconductor device with special emitter connection

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55117271A (en) * 1979-02-28 1980-09-09 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55117271A (en) * 1979-02-28 1980-09-09 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6239074A (en) * 1985-08-13 1987-02-20 Matsushita Electronics Corp Semiconductor device
US6046493A (en) * 1996-07-03 2000-04-04 U.S. Philips Corporation Semiconductor device with special emitter connection

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