JPH11330469A - Insulated gate type of semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformly embed gate electrode without increasing on-resistance. SOLUTION: Chain-shaped active regions 10 are made by coupling insular active regions 1 adjacent in one direction, in the oblique direction of the insular active regions arranged in matrix form one row by one row through narrow coupling parts 2, and the grooves 23 made between these chain-shaped active regions 10 are made roughly parallel striped patterns along the shape of the chained active regions 10. The island active region 1 exposes its n<+> -type source region 27 in annular form on the surface, and exposes its p-type base region 26 at this center. The contour 3 is a region, where the source electrode is brought to ohmic contact with the source region 27 and the base region 26 at the surface of the semiconductor body. The coupling part 2 exposes the n<+> -type semiconductor region 27' as being the same layer as the source region 27 over the entire surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a vertical MOSFET or IGBT (Ins) having a gate electrode formed inside a groove.
ullated Gate Bipolar Transi
Stor) or the like.

[0002]

2. Description of the Related Art A power MOSFET as a typical example of this type of insulated gate semiconductor device generally has a structure in which a number of unit cells having a transistor function are connected in parallel. In this MOSFET, the channel is formed in the groove direction of the semiconductor body, and the unit cell can be highly integrated compared to a gate planar type MOSFET in which the channel is formed in the surface direction of the semiconductor body. It is known that a large channel width can be obtained, which is very effective in reducing the on-resistance of the device. This MOS
The gate electrode of the FET is buried in the trench through a gate oxide film, and the source electrode is formed on the surface of the semiconductor body on the base region formed on the surface layer and on the source region formed on the surface layer by leaving a part of the base region. Are connected in ohmic contact, but this source electrode is also formed continuously on the interlayer insulating film covering the gate electrode in order to electrically insulate and separate from the gate electrode. A part of the source electrode is used as a source pad for external electrical connection. The gate electrode is generally connected to a gate pad for electrical connection to the outside via a gate wiring formed in a predetermined pattern on the chip at the end of the groove. This MOS
The planar pattern of the trench of the FET includes a lattice pattern and a stripe pattern. The former is advantageous in that the channel width per unit area can be increased.

[0003]

By the way, in the case of a lattice pattern, a square lattice means that the groove crosses the groove width between adjacent unit cells in the horizontal and vertical directions in a cross-shaped manner. The groove width between adjacent unit cells in the oblique direction is about 1.4 times. For this reason, at the intersection of the grooves, the gate electrode and the interlayer insulating film are likely to be insufficiently buried, and when a metal wire, for example, a gold wire is bonded to the source pad formed thereon, the uniformity is obtained under the source pad at that time. Pressure is not applied, stress is partially concentrated, and cracks may occur in the gate oxide film under the source pad, the semiconductor body, etc., and the ratio of non-defective electrical characteristics in the manufacturing process and the reliability of the product are increased. Could be a problem in doing so. Further, when the groove pattern is a lattice pattern, a large number of unit cells are independent of each other in the lattice pattern, so that even one unit cell has insufficient ohmic contact between the source electrode and the base region. The unit cell has a problem that the withstand voltage is reduced and as a result, the withstand voltage is destroyed, and the electrical characteristics of the entire chip become poor. Further, when the groove pattern is a lattice pattern, the groove has a corner at the inner wall, and when a channel is formed at this corner, the thickness and film quality of the gate oxide film at the corner vary with respect to the linear portion, There is a problem that it affects the electrical characteristics. The present invention has been made in view of the above-described problems, and its object is to secure a low on-resistance of a product and to reduce the defect rate of electrical characteristics in a manufacturing process and to increase the reliability of the product. An insulated gate semiconductor device is provided.

[0004]

According to the present invention, there is provided an insulated gate semiconductor device comprising: a first semiconductor layer of one conductivity type;
A semiconductor body having island-like active regions arranged in a matrix on a semiconductor layer and having a groove extending to the first semiconductor layer between the island-like active regions, and a gate electrode formed in the groove with a gate oxide film interposed therebetween. In the insulated gate type semiconductor device provided,
A narrow connecting portion formed on the first semiconductor layer connects between the island-shaped active regions obliquely adjacent to the island-shaped active region in one direction.
It is characterized in that a chain-like active area is formed by connecting the rows, and the plane pattern of the groove is a parallel or substantially parallel stripe pattern along the plane pattern of the chain-like active area between the chain-like active areas. In the above-described insulated gate semiconductor device according to the present invention, the island-shaped active region includes a second semiconductor layer of another conductivity type and a third semiconductor layer of one conductivity type formed on this surface layer, and the connecting portion is formed of the second semiconductor layer. The fourth of the other conductivity type which is the same layer as the semiconductor layer
It is characterized by including a semiconductor layer and a fifth semiconductor layer of one conductivity type which is formed on the surface layer and is the same layer as the third semiconductor layer.
In the above insulated gate semiconductor device according to the present invention,
The planar pattern of the island-shaped active area is an octagon in which the corners of a square are cut into inclined sides, and the planar pattern of the connecting portion is a diagonally opposite side of the opposite inclined side of the island-shaped active area adjacent in one direction in one direction. In the shape, the inclined side may have a dimension such that the width of the groove is substantially constant. Further, the planar pattern of the island-shaped active region has a shape obtained by cutting a corner of a square with an arc inscribed at two sides forming the corner with a predetermined radius, and the plane pattern of the connecting portion is formed in the oblique direction of the island-shaped active region by one. A shape surrounded by two arcs facing each other in the island-like active region adjacent in the direction and arcs circumscribing the ends of these arcs may be used. At this time, the plane pattern of the island-shaped active region can be made circular by setting the predetermined radius to half the size of one side of the square. In the above insulated gate semiconductor device according to the present invention, the semiconductor body may be an epitaxial layer formed on the semiconductor substrate, or may be only the semiconductor substrate. In the above-described insulated gate semiconductor device according to the present invention, when the semiconductor body is an epitaxial layer formed on a semiconductor substrate and the semiconductor substrate is of a high-concentration one conductivity type, the insulated gate semiconductor device is specifically a MOSFET. When the semiconductor substrate is of a high-concentration other conductivity type, this insulated gate semiconductor device is specifically an IGBT.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The most significant feature of this embodiment is that, unlike the conventional example in which the island-shaped active regions constituting the unit cell are independently arranged in a matrix by grooves of a grid-like pattern, one conductive layer is formed. The island-shaped active regions arranged in a matrix on the first semiconductor layer of the mold are connected one by one at a connecting portion to the island-shaped active regions adjacent to each other in one direction in a diagonal direction to form a chain-shaped active region. Is that the plane pattern of the grooves formed between the chain-like active areas is a parallel or substantially parallel stripe pattern along the plane pattern of the chain-like active area. Here, the island-shaped active region includes a second semiconductor layer of another conductivity type and a third semiconductor layer of one conductivity type formed on this surface layer, and the connecting portion is another conductivity type of the same layer as the second semiconductor layer. 4th of
The semiconductor device includes a semiconductor layer and a fifth semiconductor layer of one conductivity type formed on the surface layer and the same layer as the third semiconductor layer.

[0006] With this configuration, the channel width equivalent to that of the conventional example in which the island-shaped active regions are independently arranged in the form of a matrix by the grooves of the lattice-shaped pattern is secured,
The groove width can be made constant or almost constant, the gate electrode and interlayer insulating film can be buried uniformly in the groove, and cracks occur in the gate oxide film and semiconductor body under the electrode pad when bonding to the electrode pad. The risk of occurrence is reduced. Also,
Even if the ohmic contact between the connection electrode with the first and second semiconductor layers and the second semiconductor layer in one unit cell is insufficient, the second semiconductor in the island-shaped active region constituting this unit cell The fourth layer of the same layer of the connection part is in the same chain active area.
The semiconductor layer is connected to the second semiconductor layer of the island-shaped active region constituting another unit cell, and if ohmic contact is established with the second semiconductor layer, the breakdown voltage does not decrease and as a result, the breakdown voltage does not occur and the entire chip does not occur. The product has excellent characteristics. Further, there is no right-angled corner on the inner wall surface of the groove, and the thickness and quality of the gate oxide film in the portion where the channel is formed are reduced. As a result, it is possible to obtain an insulated gate semiconductor device having a low rate of defective electrical characteristics in a manufacturing process and a high product reliability while ensuring a low on-resistance of the product.

Hereinafter, a MOSFET as a first embodiment of an insulated gate semiconductor device using the present invention will be described with reference to FIGS. First, a planar structure will be described. FIG. 1 shows the surface of a semiconductor body (a source electrode and an interlayer insulating film are not shown), 1 is arranged in a matrix, and a planar pattern is formed by inclining a square corner by 45 degrees. An octagonal island-shaped active region which is cut off on sides a and b, and a quadrilateral having the island-shaped active region 1 as a diagonal and the opposite inclined side b of the island-shaped active region 1 adjacent in one direction in an oblique direction. In the present embodiment, the chain-shaped active regions 10 are connected one by one by the rectangular narrow connecting portion 2. Note that the inclined side need not be 45 degrees.
A groove 23 is formed between these chain-like active regions 10,
By setting the dimensions of the inclined sides a and b of the island-shaped active region 1 to predetermined values, a substantially parallel stripe-shaped plane pattern is formed along the plane pattern of the chain-shaped active region 10 and has a substantially constant groove width. A gate electrode 29 is buried in the groove 23 via a gate oxide film (not shown). Island active area 1
Is formed on a p-type base region 26, which is a second semiconductor layer of another conductivity type, on an n @-type drain region, which is a first semiconductor layer of low concentration one conductivity type, not shown in FIG. 1, and a surface layer of this base region 26. And an n @ + -type source region 27, which is a third semiconductor layer of high-concentration one conductivity type. The source region 27 is divided into approximately four parts so that the base region 26 is exposed in a cross-shaped pattern. It is exposed in a pattern separated by a predetermined constant width. Reference numeral 3 denotes a contour of a region where the source electrode makes ohmic contact with the source region 27 and the base region 26 on the surface of the semiconductor body. The connecting portion 2 is the same layer as the p-type base region 26 on the n − -type drain region not shown in FIG.
Here, a p-type semiconductor layer, which is a fourth semiconductor layer of another conductivity type (not shown), and a fifth semiconductor layer of high concentration one conductivity type, which is the same layer as the source region 27 and is formed on the surface layer of this p-type semiconductor layer. and an n + type semiconductor layer 27 'is exposed on the entire surface. In the island-shaped active region 1, the surface pattern of the drain region and the source region is not limited to the first embodiment, but may be another pattern. At this time, in order for the fourth semiconductor layer to function as a channel, it is desirable that the source region and the fifth semiconductor layer are connected as a layer.

Next, a sectional structure will be described. (1) The AA cross section of FIG. 1 will be described with reference to FIG. 2
Reference numeral 1 denotes a semiconductor body having an n + type semiconductor substrate 22 and an epitaxial layer 24 provided on the semiconductor substrate 22 and having a groove 23 formed on the surface. The epitaxial layer 24 is an initial layer of the epitaxial layer 24 and is a low-concentration one conductivity type first layer.
An n − -type drain region 25 which is a semiconductor layer, and drain regions 25 on both sides of the groove 23 reaching the drain region 25.
And a p-type base region 26 provided on the drain region 25 and an n @ + -type source region 2 provided on the surface layer of the base region 26.
7 is included. A gate oxide film 28 is provided on the inner surface of the groove 23, and a polysilicon gate electrode 29 is buried in the groove 23 via the gate oxide film 28. An interlayer insulating film 30 is provided on the epitaxial layer 24 so as to cover the gate electrode 29, and is further electrically connected to the surfaces of the source region 27 and the base region 26 by ohmic contact within the outline of 3 shown in FIG. A source electrode 31 is provided. On the back surface of the semiconductor substrate 22, a drain electrode 32 is provided.

(2) A section taken along line BB of FIG. 1 will be described with reference to FIG. The same parts as those in FIG. The connection part 2 is provided on the drain region 25 between the grooves 23. The connecting portion 2 includes a p-type semiconductor layer 26 ′ which is a fourth semiconductor layer continuously formed in the same layer as the base region 26, and an n + type semiconductor layer formed in the same layer as the source region 27 over the entire surface layer. 27 '.
The surface of the connecting portion 2 has an interlayer insulating film 3 covering the gate electrode 29.
0.

According to the above configuration, the groove width is made substantially constant while the channel width equivalent to that of the conventional example in which the island-shaped active regions are independently arranged in the form of a matrix in the form of a lattice pattern is secured. The gate electrode 29 and the interlayer insulating film 30 can be uniformly buried in the groove 23, and the gate oxide film 2 under the source pad at the time of bonding to the source pad can be formed.
8 and the possibility that cracks occur in the semiconductor body 21 and the like are reduced. Even if the ohmic contact between the source electrode 31 and the base region 26 is insufficient in one unit cell, the base region 26 of the island-like active region 1 constituting this unit cell is in the same chain-like active region. At 10, p of the same layer of the connecting portion 2
The semiconductor region 26 'is connected to the base region 26 of the island-shaped active region 1 constituting another unit cell. If ohmic contact is established with the base region 26, the breakdown voltage does not decrease and as a result, the breakdown voltage does not occur. The chip as a whole has excellent characteristics. In addition, there is no right-angled corner on the inner wall surface of the groove 23, and the thickness and quality of the gate oxide film 28 at the portion where the channel is formed are reduced. As a result, while ensuring a low on-resistance of the product, a MOSFET with a low electrical characteristic failure rate in the manufacturing process and a high product reliability
Is obtained.

Next, a MOSFET as a second embodiment of the insulated gate semiconductor device using the present invention will be described with reference to FIG. Since the sectional structure is the same as that of the first embodiment, only the planar structure will be described. FIG. 4 shows the surface of the semiconductor body (a source electrode and an interlayer insulating film are not shown). Reference numeral 41 denotes a matrix which is arranged in a matrix and whose plane pattern has a square corner with two corners forming the corner at a predetermined radius. This is an island-shaped active area having a shape cut off by arcs a and b in contact with each other. The island-shaped active area 41 is formed by two opposite arcs b of the island-shaped active area 41 adjacent in one direction in an oblique direction and these arcs b Are connected one by one by a narrow connecting portion 42 having a shape surrounded by a circular arc c circumscribing at the end of the active region 50. A groove 63 is formed between the chain-like active regions 50 along the shape of the chain-like active region 50, and the width of the curved groove between the island-like active region 41 and the connecting portion 42 is concentric arcs a and c. , That is, the width of the linear groove between the island-shaped active regions 41 is equal to the width of the linear groove, and the groove width is constant and a continuous parallel stripe-shaped plane pattern is formed. A gate electrode 69 is buried in the groove 63 via a gate oxide film (not shown). The island-shaped active region 41 has a p-type base region 66 as a second semiconductor layer of another conductivity type and an n-type drain region as a first semiconductor layer of low concentration one conductivity type, not shown in FIG. And an n @ + -type source region 67, which is a high-concentration one-conductivity type third semiconductor layer formed on the surface layer of the semiconductor device. The source region 67 is formed on this surface so that the base region 66 is exposed in a cross-shaped pattern. It is divided into approximately four equal parts and is exposed in a pattern separated by a predetermined constant width. Reference numeral 43 denotes an outline of a region where the source electrode makes ohmic contact with the source region 67 and the base region 66 on the surface of the semiconductor body. The connecting portion 2 is not shown in FIG.
The p-type semiconductor layer, which is the same layer as the p-type base region 66 and is not shown in FIG. 4, is a fourth semiconductor layer of another conductivity type, and the same layer as the source region 67 on the type drain region. An n + -type semiconductor layer 67 ′ is exposed on the entire surface, including an n + -type semiconductor layer 67 ′ which is a high-concentration one conductivity type fifth semiconductor layer formed on the surface layer. Incidentally, the island-shaped active area 41
In the above, the surface patterns of the drain region and the source region are not limited to the second embodiment, but may be other patterns. At this time, in order for the fourth semiconductor layer to function as a channel, it is desirable that the source region and the fifth semiconductor layer are connected as a layer.

According to the above configuration, the groove width is made constant while the channel width equivalent to that of the conventional example in which the island-shaped active regions are independently arranged in the form of a matrix in the form of a lattice pattern is secured. The gate electrode 69 and the interlayer insulating film can be uniformly buried in the groove 63, and the risk of cracks occurring in the gate oxide film and the semiconductor body under the source pad during bonding to the source pad is reduced, and A MOSFET with a high characteristic non-defective rate and high reliability can be obtained. Also, 1
Even if the ohmic contact between the source electrode and the base region 66 is insufficient in each of the island-shaped active regions 41, the base region 66 of the island-shaped active regions 41 constituting this unit cell must be within the same chain-shaped active region 50. The island-shaped active region 41 which forms another unit cell by the same p-type semiconductor layer of the connecting portion 42
If ohmic contact is made with the base region 66, the withstand voltage does not decrease and as a result, breakdown does not occur, and the chip as a whole has excellent characteristics.
In addition, since the planar pattern of the groove 63 is straight and circular and does not have corners like a lattice pattern, there is no problem of variation in the film thickness or film quality of the gate oxide film in the portion where the channel is formed. As a result, a MOSFET having a high non-defective product ratio and high electrical characteristics can be obtained.

Next, a MOSFET as a third embodiment of the insulated gate semiconductor device according to the present invention will be described with reference to FIG. Since the sectional structure is the same as that of the first embodiment, only the planar structure will be described. This embodiment is different from the second embodiment in that the side of the island-shaped active region 41 is eliminated and only the arc is formed. The arc 71 is arranged in a matrix and the plane pattern inscribes the square corner with a half radius of the side. (Quarter circle) A shape cut off by a and b, that is, a circular island-shaped active region. Arcs b and arcs circumscribing at the ends of these arcs b (1/4
1) by a narrow connecting portion 72 having a shape surrounded by a circle c).
The chain-like active regions 80 are formed by connecting the columns. A groove 93 is formed between the chain-like active regions 80 along the plane pattern of the chain-like active region 80, and the width of the curved groove between the island-like active region 71 and the connecting part 72 is concentric arc a, It is a plane pattern of a continuous parallel stripe having a constant groove width equal to the radius difference of c. A gate electrode 99 is embedded in the groove 93 via a gate oxide film (not shown). The island-shaped active region 71 has a p-type base region 96 as a second semiconductor layer of another conductivity type and an n-type drain region as a first semiconductor layer of low concentration one conductivity type, not shown in FIG. And an n + -type source region 97 which is a high-concentration one-conductivity third semiconductor layer formed on the surface layer of the semiconductor device. The source region 97 is formed on this surface so that the base region 96 is exposed in a cross-shaped pattern. It is divided into approximately four equal parts and is exposed in a pattern separated by a predetermined constant width. Reference numeral 73 denotes an outline of a region where the source electrode makes ohmic contact with the source region 97 and the base region 96 on the surface of the semiconductor body. The connecting portion 72 has a p-type base region 9 on an n − -type drain region not shown in FIG.
6 and a p-type semiconductor layer which is a fourth semiconductor layer of another conductivity type (not shown in FIG. 5), and a high-concentration one conductive layer which is the same layer as the source region 96 and is formed on the surface layer of the p-type semiconductor layer. An n + type semiconductor layer 97 ′ that is a fifth semiconductor layer of
The n + type semiconductor layer 97 'is exposed on the entire surface. still,
In the island-shaped active region 71, the surface pattern of the drain region and the source region is not limited to the third embodiment, but may be another pattern. At this time, in order for the fourth semiconductor layer to function as a channel, it is desirable that the source region and the fifth semiconductor layer are connected as a layer.

According to the above structure, the groove width is made constant while the channel width equivalent to that of the conventional example in which the island-shaped active regions are independently arranged in the form of a matrix in the form of a lattice pattern is secured. The gate electrode 99 and the interlayer insulating film can be uniformly buried in the groove 93, and the risk of cracks occurring in the gate oxide film and the semiconductor body under the source pad during bonding to the source pad is reduced. A MOSFET with a high characteristic non-defective rate and high reliability can be obtained. Also, 1
Even if the ohmic contact between the source electrode and the base region 96 is insufficient in the island-shaped active regions 71, the base region 96 of the island-shaped active regions 71 constituting the unit cell is within the same chain-shaped active region. At 80, the island-shaped active region 7 constituting another unit cell by the same p-type semiconductor layer of the connecting portion 72 is formed.
1 base region 96 and the base region 96
And ohmic contact is obtained, and a reduction in withstand voltage and, as a result, no withstand voltage breakdown occur, and the chip as a whole has excellent characteristics. In addition, since the planar pattern of the groove 93 is arc-shaped and has no corners, there is no problem of variation in the film thickness or film quality of the gate oxide film in the portion where the channel is formed, and the electrical characteristic non-defective rate and reliability are improved. A MOSFET having high performance can be obtained.

Next, the MO of the first to third embodiments will be described.
The method of manufacturing the SFET will be described, except that the plane pattern is different. Therefore, only an example of the method of manufacturing the MOSFET of the first embodiment will be described with reference to FIGS. 6 (a) to 6 (d). 6 (a) to 6 (d) show process changes in the AA section of FIG. First, a first step is to form an n- type initial layer of an epitaxial layer on an n + type semiconductor substrate 22, as shown in the sectional view of FIG. Layer is selectively etched to form an epitaxial layer 24 having a plurality of grooves 23 (only one is shown) in the plane pattern shown in FIG.
a is formed.

Next, in the second step, as shown in FIG. 6 (b), a cross-sectional view after the completion of this step, the gate oxide film 2 is formed on the inner surface of the groove 23 and the surface of the epitaxial layer 24a by thermal oxidation.
8 is formed, and a polysilicon film 33 is coated thereon by the CVD method. At the same time, the trench 23 is filled with the polysilicon film 34.

Next, in a third step, as shown in FIG. 6 (c), a cross-sectional view after the completion of this step, the polysilicon film 33 in the trench 23 is replaced with the polysilicon layer 33a by the dry etching method. The gate electrode 29 is formed in the groove 23 by etching back to a predetermined depth with respect to the surface.

Thereafter, in a fourth step, as shown in FIG.
a) The gate oxide film 28 exposed on the surface is removed by a wet etch method, and a silicon oxide film 34 is formed on the exposed surface by a thermal oxidation method. Then, boron is ion-implanted and thermally diffused using the gate electrode 29 as a mask. Thus, a p-type base region 26 shallower than the groove 23 is formed on both sides of the groove 23. Although not shown, the groove 23 at the time of the BB section in FIG.
A p-type semiconductor layer 26 'in the same layer as the base region 26 is formed in the epitaxial layer between the groove 23 and the epitaxial layer. Base area 2
6 is masked with a photoresist film at the gate electrode 29 and PR, arsenic is ion-implanted, and the photoresist is removed.
7 is formed. Although not shown, at this time FIG.
An n @ + -type semiconductor layer 27 'in the same layer as the source region 27 is formed in the p-type semiconductor layer between the grooves 23 in the BB section of FIG. As a result, the epitaxial layer 24a shown in FIGS. 6A to 6D has an n @-type drain region 25 having a groove 23 formed on the surface and an initial layer of the epitaxial layer, and a base region 2a.
6, an epitaxial layer 24 including a source region 27, a p-type semiconductor layer 26 ', and an n-type semiconductor layer 27'.
Thereafter, the surface of the epitaxial layer 24 that has undergone the above steps is coated with an interlayer insulating film 30 by a CVD method.

Next, in a fourth step, a part of the surface of the source region 27 and the surface of the base region 26 are within the contour 3 shown in FIG. After a contact window is formed in the interlayer insulating film 30 and the oxide film 34 (not shown in FIGS. 2 and 3) so as to be exposed, the surface of the epitaxial layer 24 that has undergone the above steps is covered with an aluminum film by sputtering. Then, the aluminum film is selectively removed by PR and dry etching to form a source electrode 31 which is electrically connected to the base region 26 and the source region 27 by ohmic contact within the contour shown in FIG. On the back surface of the semiconductor substrate 22, a drain electrode 32 is formed. Although not shown, the gate electrode 29 is connected to a gate pad for electrical connection to the outside via a gate wiring formed in a predetermined pattern on the chip at the end of the groove 23.

In the above embodiment, the semiconductor body has been described as being composed of the epitaxial layer formed on the semiconductor substrate. However, the semiconductor body may be composed of only the semiconductor substrate. in this case,
The semiconductor substrate in which the groove is formed includes a drain region, a base region, a source region, a semiconductor layer of one conductivity type and a semiconductor layer of another conductivity type, and a back surface side of the semiconductor substrate includes a high-concentration one conductivity type layer. Further, in the case where the semiconductor body is an epitaxial layer formed on a semiconductor substrate, the semiconductor substrate has been described as a high-concentration one-conductivity type. In this case, it can be used for IGBT. When the semiconductor body is only a substrate, it can be used for an IGBT when the back side of the semiconductor substrate is of a high-concentration and other conductivity type. Also, the n-type is described as one conductivity type and the p-type as another conductivity type, but the p-type may be used as one conductivity type and the n-type may be used as another conductivity type.

[0021]

According to the present invention, while maintaining the same channel width as in the conventional example, the island-shaped active regions constituting the unit cell are independently arranged in a matrix by grooves of a lattice pattern. The groove width can be made substantially constant, the gate electrode and the interlayer insulating film can be uniformly buried in the groove, and the connection electrodes to the first and second semiconductor layers and the second semiconductor layer can be formed in one unit cell. Even if the ohmic contact with the layer is inadequate, the second semiconductor layer of the island-shaped active region constituting this unit cell is separated by the fourth semiconductor layer of the same layer of the connection portion in the same chain-shaped active region. Is connected to the second semiconductor layer of the island-shaped active region constituting the unit cell of the above, and an ohmic contact can be established with the second semiconductor layer, and further, the channel is formed without the right-angled corner on the inner wall surface of the groove. Thickness of the gate oxide film The variation in the quality is reduced. As a result, it is possible to obtain an insulated gate semiconductor device having a low rate of defective electrical characteristics in a manufacturing process and a high product reliability while ensuring a low on-resistance of the product.

[Brief description of the drawings]

FIG. 1 is a plan view of a main part of a MOSFET according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG. 1;

FIG. 4 is a plan view of a main part of a MOSFET according to a second embodiment of the present invention.

FIG. 5 is a plan view of a main part of a MOSFET according to a third embodiment of the present invention.

FIG. 6 is a main-portion cross-sectional view showing a manufacturing step of the MOSFET shown in FIG. 1;

[Explanation of symbols]

 1, 41, 71 Island-shaped active region 2, 42, 72 Connecting portion 10, 50, 80 Chain-shaped active region 21 Semiconductor body 22 Semiconductor substrate 23, 63, 93 Groove 24 Epitaxial layer 25 First semiconductor layer (drain region) 26 , 66, 96 Second semiconductor layer (base region) 27, 67, 97 Third semiconductor layer (source region) 26 ′ Fourth semiconductor layer (p-type semiconductor layer) 27, 67, 97 ′ Fifth semiconductor layer (n-type Semiconductor layer) 28 Gate oxide film 29, 69, 99 Gate electrode

Claims (8)

[Claims] A semiconductor having a first semiconductor layer of one conductivity type and island-shaped active regions arranged in a matrix on the first semiconductor layer, and a groove extending to the first semiconductor layer between the island-shaped active regions. An insulated gate semiconductor device comprising a main body and a gate electrode formed in a trench with a gate oxide film interposed therebetween, wherein the first semiconductor is disposed between the island-shaped active regions in one direction obliquely adjacent to the island-shaped active regions. Concatenated active areas are formed by connecting one row at a time by narrow connecting portions formed on the layers, and the plane pattern of the grooves is parallel between the chained active areas along the plane pattern of the chained active areas. Alternatively, an insulated gate semiconductor device having a substantially parallel stripe pattern. 2. The island-shaped active region includes a second semiconductor layer of another conductivity type and a third semiconductor layer of one conductivity type formed on the surface layer, and the connection portion is in the same layer as the second semiconductor layer. 2. The insulated gate according to claim 1, further comprising a fourth semiconductor layer of another conductivity type and a fifth semiconductor layer of one conductivity type formed on the surface layer and the same layer as the third semiconductor layer. Type semiconductor device. 3. The planar pattern of the island-shaped active region is an octagon in which a square corner is cut into an inclined side, and the plane pattern of the connecting portion is such that an opposite inclined side of the adjacent island-shaped active region is defined as an opposite side. 2. The insulated gate semiconductor device according to claim 1, wherein said inclined side has a dimension such that a width of said groove is substantially constant. 4. A planar pattern of the island-shaped active region has a shape obtained by cutting a corner of a square with a circular arc inscribed at two sides forming the corner with a predetermined radius, and the planar pattern of the connecting portion is formed on the adjacent island-shaped. 2. The insulated gate semiconductor device according to claim 1, wherein the semiconductor device has a shape surrounded by two opposing arcs of the active region and arcs circumscribing the ends of these arcs. 5. The insulated gate semiconductor device according to claim 4, wherein said predetermined radius is set to a half size of one side of said square, whereby a plane pattern of said island-shaped active region is made circular. 6. The insulated gate semiconductor device according to claim 1, wherein said semiconductor body is an epitaxial layer formed on a semiconductor substrate. 7. The insulated gate semiconductor device according to claim 6, wherein said semiconductor substrate is of a high concentration one conductivity type. 8. The insulated gate semiconductor device according to claim 6, wherein said semiconductor substrate is of a high concentration and other conductivity type.