JP2009224734A - Mos semiconductor device having trench gate structure, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MOS semiconductor device having a trench gate structure capable of directly and definitely detecting the presence or absence of the wire severance of a gate electrode immediately after the formation process of the gate electrode, and its manufacturing method. <P>SOLUTION: One zigzag trench 5 is formed on an n semiconductor substrate 1. The gate electrode 7 is formed by embedding polysilicon in the trench 5. Disconnection determination electrodes a, b are formed at the end of the one gate electrode 7. The presence or absence of the wire severance of the gate electrode 7 can be detected by investigating electric continuity between the disconnection determination electrodes a, b. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a MOS semiconductor device having a trench gate structure and a method of manufacturing the same in a vertical structure MOS semiconductor device that can determine whether or not a gate electrode is disconnected during the manufacturing process.

As a MOS type semiconductor device having a trench gate structure as a vertical type power device, there are a power MOSFET, an IGBT (insulated gate type bipolar transistor) and the like.
10 to 14 are configuration diagrams of a conventional MOS type semiconductor device having a trench gate structure. FIG. 10 is a plan view of a principal part of a semiconductor chip. FIG. 11 is a detailed view of a portion B in FIG. 11 is a cross-sectional view of the main part cut along line XX in FIG. 11, FIG. 13 is a cross-sectional view of the main part cut along line YY in FIG. 11, and FIG. 14 is a cross-sectional view of the main part cut along line ZZ in FIG. It is. These figures are schematic views, and this MOS type semiconductor device is exemplified by an IGBT 200. In addition, although the example in which the planar shape of the trench 55 is a loop shape is given here, there may be a linear shape having a plurality of ends.
10 and 11, a plurality of loop-like trenches 55 are formed, and a gate electrode 57 is formed on the inner wall of each trench 55 via a gate insulating film 56 (see FIG. 12). A p-well region 54 is formed inside and outside the loop-shaped trench 55, and a high-concentration p-region 68 is formed in the surface layer of the p-well region 54 inside the loop. The p region 68 is shown as being formed over the entire surface layer of the p well region 54 inside the loop, but may be selectively formed.
An n emitter region 58 and a p contact region 59 are formed on the surface layer of the p well region 54 sandwiched between the trenches 55 outside the loop-shaped trench 55. The high-concentration p region 68 inside the loop is connected to the disconnection determination electrode c through a contact hole 62 formed in the interlayer insulating film 61.
Each n emitter region 58 and each p contact region 59 formed outside the loop are connected to the emitter electrode 63 through a contact hole 62 formed in the interlayer insulating film 61. A lead electrode 60 connected to the gate electrode 57 at the end (curvature portion) of the loop-shaped trench 55 is formed at the same time as the gate electrode 57, and a gate liner 64 connected to the lead electrode 60 via a contact hole 62, The gate pad 67 to be connected is formed simultaneously with a metal film such as aluminum.
12 to 14, a p-well region 54 is formed in the surface layer of an n semiconductor substrate 51, and a plurality of loop-shaped trenches 55 that penetrate the p-well region 54 and reach the n semiconductor substrate 51 are formed. A high-concentration p region 68 is formed in the surface layer of the p-well region 54 inside the loop-shaped trench 55, and an n-emitter region 58 is formed on the surface layer of the p-well region 54 sandwiched by the trench 55 outside the loop-shaped trench 55. A p contact region 59 is formed. A gate insulating film 56 is formed on the inner wall of the trench 55, and the trench 55 is filled with polysilicon serving as the gate electrode 57 through the gate insulating film 56. Interlayer insulating film 61 is formed on the surface, contact hole 62 is formed in interlayer insulating film 61 on n emitter region 58, p contact region 59, and high concentration p region 68, and emitter electrode 63 and disconnection are formed thereon. A determination electrode c is formed. A gate electrode 57 formed inside the loop-shaped trench is connected to a lead electrode 60 made of polysilicon, the lead electrode 60 is connected to a gate liner 64 through a contact hole 62, and the gate liner 64 is connected to a gate pad 67. Connecting.
A p collector region 65 is formed on the back side of the n semiconductor substrate 51, and a collector electrode 66 is formed on the p collector region 65. In the figure, 52 is a p-resurf region, and 53 is a field oxide film. These are formed in the breakdown voltage structure portion of FIG.
A predetermined voltage is applied between the emitter electrode 63 and the disconnection determination electrode c, and it is determined whether or not the trench 55 penetrates the p-well region 54 based on the presence or absence of conduction. If not conducting, the trench 55 penetrates the p well region 54 (conduction is prevented by a pn junction formed by the p well region 54 and the n semiconductor substrate 51), and all the trenches 55 are formed normally. You can see that. If the trench 55 is formed normally, it is determined that the gate electrode 57 embedded in the trench 55 is also formed normally without disconnection.
On the other hand, if conduction is established, any one of the numerous trenches 55 does not penetrate the p-well region 54, and there is a trench 55 that is not normally formed. If the trench 55 is formed shallowly without penetrating the p-well region 54, the thickness of the gate electrode 57 formed therein is also reduced, and the resistance value is increased. Further, if there is a portion where the trench 55 is not formed, the gate electrode 57 is not formed at that portion, and it is determined that the wire is disconnected. These contents are also disclosed in Patent Document 1.
JP 2005-150426 A

However, when the disconnection determination electrode c is formed as described above, a dedicated space is required for this purpose, and the chip size increases.
In addition, since the quality of the disconnection is determined at the final stage of the process, even if the disconnection occurs in the gate electrode formation process, the process flows to the final process, so that the cost spent during that time is wasted and the manufacturing cost is increased. In addition, since the disconnection of the gate electrode is determined at the final stage, it takes time to feed back to the gate electrode formation process.
Further, in the conventional method, since the depth of the trench 55 is shallow, the disconnection of the gate electrode 57 is judged, so that the trench 55 is normally formed and some abnormality occurs in the process of forming the gate electrode 57. When the gate electrode 57 is not formed normally and a disconnection occurs, there is a problem that the presence or absence of the disconnection cannot be determined.
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a MOS type semiconductor device having a trench gate structure that can directly and reliably determine the presence or absence of disconnection of the gate electrode immediately after the gate electrode forming step, and a method for manufacturing the same. Is to provide.

In order to achieve the above object, a second conductivity type first semiconductor region (well region) disposed in a surface layer of a first conductivity type semiconductor substrate, and the first semiconductor region (well region) are penetrated. A meandering trench that reaches the semiconductor substrate, and a second semiconductor region of a first conductivity type that is selectively disposed on a surface layer of the first semiconductor region (well region) in contact with the sidewall of the trench. An emitter region), and a meandering gate electrode buried in the trench through a gate insulating film disposed on the inner wall of the trench.
The planar shape of the meandering gate electrode may be composed of a parallel straight portion and a meandering curvature portion connected to the straight portion, and both ends of the meandering gate electrode may be a curvature portion. .
Also, a second conductivity type first semiconductor region well region disposed in a surface layer of the first conductivity type semiconductor substrate, and a single meandering meander that passes through the first semiconductor region well region and reaches the semiconductor substrate. A trench, a second semiconductor region emitter region of a first conductivity type selectively disposed in a surface layer of the first semiconductor region well region in contact with a sidewall of the trench, and a gate insulation disposed on an inner wall of the trench In a manufacturing method of a MOS type semiconductor device having a trench gate structure comprising a meandering gate electrode embedded in the trench through a film, a predetermined voltage is applied across the meandering gate electrode. And a predetermined current flows to determine whether or not the gate electrode is disconnected.

  Further, it is preferable to add a step of applying a voltage between one end of the meandering gate electrode and the second semiconductor region emitter region to determine the presence or absence of withstand voltage.

According to this invention, a gate electrode is formed in one meandering trench, and a disconnection determination electrode is formed at an end of the one gate electrode, thereby forming a dedicated disconnection determination electrode as in the conventional structure. Therefore, the chip size can be reduced.
In addition, since the presence or absence of the disconnection of the gate electrode can be determined immediately after forming the gate electrode, the determination information can be quickly fed back to the process before the gate electrode forming process.
In addition, since defective products can be selected after forming the gate electrode, it is not necessary to send defective products to subsequent processes, so that the manufacturing cost can be reduced.
In addition, the presence / absence of disconnection of the gate electrode is not indirectly determined from the depth of the trench as in the prior art, but is determined by examining the disconnection of the gate electrode itself.

  Embodiments will be described in the following examples.

1 to 3 are configuration diagrams of a MOS type semiconductor device having a trench gate structure according to an embodiment of the present invention. FIG. 1 is a plan view of a main part of a semiconductor chip, and FIG. 2 is a plan view of a trench and a gate electrode. 3A is a detailed view of the portion A in FIG. 1, FIG. 3B is a cross-sectional view taken along line XX in FIG. 3A, and FIG. 3C is FIG. It is principal part sectional drawing cut | disconnected by the YY line | wire of (). As this MOS type semiconductor device, IGBT 100 is taken as an example. In this IGBT 100, the case where the pressure-resistant structure portion has the RESURF structure is shown, but there may be other structures such as a guard ring structure. The gate liner 14 is actually very narrow, but here the width is exaggerated for the sake of clarity.
In FIG. 1 to FIG. 3A, a single meandering trench 5 is formed through the p-well region 4 to reach the n semiconductor substrate 1, and the meandering 1 is formed in the trench 5 via the gate insulating film 8. A striped gate electrode 9 is formed. The meandering trench 5 is composed of a straight line portion that runs in parallel and a curvature portion of the folded portion, and a plurality of p-well regions 4 sandwiched between adjacent straight-line trenches are formed. 4, an n emitter region 8 and a p contact region 9 are formed.
Contact holes 12 are opened in interlayer insulating films 11 on each n emitter region 8 and each p contact region 9, and emitter electrodes connected to each n emitter region 8 and each p contact region 9 through this contact hole 12. 13 is formed. A lead electrode 10 connected to the gate electrode 7 in the curvature portion of the meandering trench 5 is formed. The lead electrode 10 is connected to the gate liner 13 through the contact hole 12, and the gate pad 17 is connected to the gate liner 13. Instead of forming the gate pad 17 and the gate liner 17 separately as described above, the gate pad 17 may be deleted by making the gate liner 13 also function as the gate pad 17. Then, the area occupied by the gate pad 17 becomes unnecessary, and the chip area can be reduced. The gate liner 13 and the gate pad 17 are formed of a metal film such as aluminum.
Further, the outer peripheral portion of the p well region 4 is connected to the p RESURF region 2, and a field oxide film 3 is formed on the p RESURF region 2 (see FIG. 3C).
Although the interval between the straight portions of the trench 5 is shown as an equal interval, the p well region where the n emitter region 8 is not formed more than the interval between the trenches 5 sandwiching the p well region 4 where the n emitter region 8 is formed. In some cases, the interval between the trenches 5 sandwiching 4 is wider.
3B and 3C, p-resurf region 2 is formed on the surface layer of the outer peripheral portion of n semiconductor substrate 1, and field oxide film 3 is formed thereon. Further, p well region 4 is formed using field oxide film 3 as a mask, and a meandering trench 5 penetrating through p well region 4 and reaching n semiconductor substrate 1 is formed. The p-well region 4 is in contact with the p-resurf region 2, and the p-resurf region 2 is formed on the outer periphery of the chip and constitutes the breakdown voltage structure shown in FIG.
An n emitter region 8 and a p contact region 9 are formed on the surface layer of the p well region 4 between two trenches 5 which are adjacent to each other and run parallel to each other as a pair. Is done. By forming the n emitter regions 8 every other group, the current limited by the channel is suppressed, and the short-circuit load resistance is increased.
A single gate electrode 7 is formed on the inner wall of the trench 5 through the gate insulating film 6. Interlayer insulating film 11 is formed on the surface, contact hole 12 is formed in interlayer insulating film 11 on n emitter region 8 and p contact region 9, and emitter electrode 13 is formed thereon. The lead electrode 10 formed simultaneously with the gate electrode 7 is connected to the gate liner 14 and the gate pad 17 through the contact hole 12. Here, the gate pad 17 also serves as the gate liner 14, but may be formed individually without serving as the gate liner 14.
A p collector region 15 and a collector electrode 16 are formed on the back side of the n semiconductor substrate 1.

4 to 8 are manufacturing methods of the MOS type semiconductor device having the trench gate structure shown in FIGS. 1 to 3, and are main part manufacturing process diagrams shown in the order of processes. This MOS type semiconductor device is the IGBT shown in FIGS. (A) of each figure is a figure equivalent to FIG.3 (b), (b) is a figure equivalent to FIG.3 (c).
First, as shown in FIG. 4, the p-resurf region 2 is formed on the outermost surface layer of the n semiconductor substrate 1 using a mask (not shown). Subsequently, a field oxide film 3 is formed thereon, and a p-well region 4 is formed in contact with the p-resurf region 2 using this as a mask.
Next, as shown in FIG. 5, a meandering trench 5 that penetrates the p-well region 4 and reaches the n semiconductor substrate 1 is formed based on the trench pattern. As shown in FIG. 2, this trench is composed of a straight line portion that runs in parallel and a curvature portion at a turn-back portion. The reason why the curvature portion is provided is to prevent electric field concentration. Further, both ends of the single trench 5 are also provided with a curvature portion in order to suppress electric field concentration.
Next, as shown in FIG. 6, after removing the damaged layer by trench etching, a gate insulating film 6 is formed on the inner wall of the trench 5, polysilicon is buried in the trench 5, and the surface is covered with this polysilicon. Subsequently, patterning is performed using a pattern (not shown) to form a meandering gate electrode 7 embedded in the trench 5, the extraction electrode 10 exposed on the surface, and the disconnection determination electrodes a and b by etching. Lead electrodes 10 are formed on the straight and curved portions of the trench 5, and disconnection determination electrodes a and b are formed on both ends of the trench 5 simultaneously with the gate electrode 7. The extraction electrodes 10 formed on the straight portions of the trench 5 are formed so as not to contact each other.
Here, an initial evaluation for determining whether or not the gate electrode 7 is disconnected is performed. The evaluation is performed using disconnection determination electrodes a and b (PCM: Pattern Check Monitor) formed at both ends of the single trench. Specifically, a predetermined voltage is applied between the disconnection determination electrodes a and b, and when the conducting current is equal to or less than a predetermined value, the disconnection is determined.
In accordance with this evaluation, in order to determine that the depth of the trench 5 is shallower than the depth of the p-well region 4, a pulse voltage signal is applied to the disconnection determination electrodes a and b. It is also possible to exchange pulse voltage signals between them and determine the depth of the trench 5 based on the degree of signal reflection / attenuation.
Next, as shown in FIG. 7, the gate insulating film 6 is removed, a sacrificial oxide film (not shown) is formed, and an n emitter region 8 and a p contact region 9 are formed using a mask (not shown). Thereafter, the sacrificial oxide film is removed. However, another circuit such as a temperature sense may be incorporated before that. The p well region 4 sandwiched between the trenches 5 where the n emitter region 8 is not formed is floating in terms of potential. For reference, the position of the n emitter region 8 is indicated by a dotted line as shown in FIG.
Finally, as shown in FIG. 8, an interlayer insulating film 11 is formed on the surface, a contact hole 12 is opened in the interlayer insulating film 11, an emitter electrode 13 connected to the n emitter region 8 and the p contact region 9, and a lead The gate liner 14 connected to the electrode 10 and the gate pad 17 connected to the electrode 10 are formed, the p collector region 15 is formed on the back surface, the collector electrode 16 connected to the p collector region 15 is formed, and the wafer process of the IGBT 100 is completed. To do. Then, it is completed as a product through an assembly process and a test process. The p-resurf region 2 and the p-well region 4 have been described as being connected. However, the p-resurf region 2 and the p-well region 4 may be formed separately as shown in FIG.
In the present invention, as shown in FIGS. 1 and 2, all the gate electrodes 7 are formed in a meandering line (one line), and after the gate electrode 7 is formed, the gate electrode 7 is disconnected. Judgment is made. As described above, the presence / absence of disconnection is determined by applying a voltage between the disconnection determination electrodes a and b formed at both ends of the gate electrode 7.
As described above, since the voltage is applied to both ends of the gate electrode 7 to directly check the conduction, the presence / absence of disconnection can be determined more reliably than in the conventional method.
Further, when a voltage is applied between one of the disconnection determination electrodes a and b and the n emitter region 8, the gate breakdown voltage can also be evaluated. Thus, by evaluating the presence or absence of disconnection and the gate breakdown voltage in the middle of the process (before the formation of the n emitter region 8), the manufacturing cost can be reduced compared to the case of performing the final process, and the process of forming the gate electrode 7 Feedback can be made quickly.
Note that the gate liner 13 connected to the extraction electrode 10 and the gate pad 17 connected thereto are formed of a metal such as aluminum after the gate electrode 7 formation step. When the area of the IGBT chip is increased, as shown in FIGS. 1 and 2, the extraction electrode 10 is formed in the middle of the straight portion of the gate electrode (the straight portion of the trench 5), and the gate runner 13 and the contact hole 12 are formed. By connecting via, the gate resistance of the IGBT 100 can be lowered.
The present invention can also be applied to an IGBT in which an n emitter region 8 is formed in all locations of the p well region 4 sandwiched between the trenches 5. The present invention can also be applied to a power MOSFET having a trench gate structure. Further, in FIG. 3, when the p-well region 4 where the n-emitter region 8 is not formed is wider than the p-well region 4 where the n-emitter region 8 is formed at a portion sandwiched between the straight portions of the trench 5. The present invention can also be applied to an IGBT in which a loop-shaped trench reaching the n semiconductor substrate 1 is newly formed in the wider p-well region 4 and the intervals between the straight portions of the trench are made uniform. It is expected to improve the device breakdown voltage by equalizing the trench interval.

The principal part top view of the semiconductor chip of the MOS type semiconductor device which has a trench gate structure in one Example of this invention Plan view of trench and gate electrode in FIG. It is a block diagram of the MOS type semiconductor device which has a trench gate structure of one Example of this invention, (a) is detail drawing of the A section of FIG. 1, (b) was cut | disconnected by the XX line of (a) Cross-sectional view of the main part, (c) is a cross-sectional view of the main part taken along line YY of (a). Manufacturing process diagram of main part of MOS type semiconductor device having trench gate structure of FIGS. FIG. 4 is a manufacturing process diagram of a main part of the MOS semiconductor device having the trench gate structure of FIGS. FIG. 5 is a manufacturing process diagram of a main part of the MOS type semiconductor device having the trench gate structure of FIGS. FIG. 6 is a manufacturing process diagram of a main part of the MOS type semiconductor device having the trench gate structure of FIGS. FIG. 7 is a manufacturing process diagram of a main part of the MOS type semiconductor device having the trench gate structure of FIGS. The principal part sectional view at the time of forming p resurf field 2 and p well field 4 apart. Plan view of relevant part of a semiconductor chip of a MOS type semiconductor device having a conventional trench gate structure Detailed view of part B in FIG. Sectional drawing of the principal part cut | disconnected by the XX line of FIG. Sectional drawing of the principal part cut | disconnected by the YY line of FIG. Sectional drawing of the principal part cut | disconnected by the ZZ line of FIG.

Explanation of symbols

1 n semiconductor substrate 2 p RESURF region 3 field oxide film 4 p well region 5 trench (one)
6 Gate insulation film 7 Gate electrode (1 item)
8 n emitter region 9 p contact region 10 lead electrode 11 interlayer insulating film 12 contact hole 13 emitter electrode 14 gate liner 15 p collector electrode 16 collector electrode 17 gate pad a, b disconnection judgment electrode

Claims (4)

A second conductivity type first semiconductor region disposed in a surface layer of the first conductivity type semiconductor substrate; a meandering trench that penetrates the first semiconductor region and reaches the semiconductor substrate; and A second semiconductor region of a first conductivity type that is selectively disposed on a surface layer of the first semiconductor region in contact with a side wall, and a meander embedded in the trench via a gate insulating film disposed on an inner wall of the trench A MOS type semiconductor device having a trench gate structure. The planar shape of the meandering gate electrode is composed of parallel straight portions and meandering curvature portions connected to the straight portions, and both end portions of the meandering gate electrode form curvature portions. A MOS semiconductor device having a trench gate structure according to claim 1. A first semiconductor region of a second conductivity type disposed in a surface layer of the semiconductor substrate of the first conductivity type; a meandering trench that penetrates the first semiconductor region and reaches the semiconductor substrate; and A second semiconductor region of a first conductivity type that is selectively disposed on a surface layer of the first semiconductor region in contact with a side wall, and a meander embedded in the trench via a gate insulating film disposed on an inner wall of the trench In the method of manufacturing a MOS type semiconductor device having a trench gate structure comprising:
A MOS having a trench gate structure comprising a step of applying a predetermined voltage to both ends of the meandering gate electrode to determine whether or not the gate electrode is disconnected by flowing a predetermined current. Type semiconductor device manufacturing method. 4. The trench gate structure according to claim 3, further comprising a step of applying a voltage between one end of the meandering gate electrode and the second semiconductor region to determine the presence or absence of a withstand voltage. A method for manufacturing a MOS semiconductor device having the same.

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