JP2021072360A - Semiconductor device - Google Patents

Abstract

To provide an SiC semiconductor device capable of suppressing generation of leakage caused by an injection defect while relaxing the electric field stress to a trench bottom part by an electric field relaxation layer.SOLUTION: A semiconductor device comprises an electric field relaxation layer 3 which includes: a p-type first region 3a which is formed at a position deeper than a trench 7 in an n-type drift layer 2; a p-type second region 3b which is arranged away from the side surface of the trench 7 between a plurality of trenches 7 using the same direction as the longitudinal direction of the trench 7 as the longitudinal direction and connects the first region 3a and a p-type base region 4. Both first region 3a and second region 3b are constituted of an ion implantation layer, the second region 3b is formed in a broken line shape and has a partially thinned structure, the thinned portion is used as the thinned area, and only the first region 3a is formed in the thinned area in a normal direction to the surface of n+ type semiconductor substrate 1.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device made of a material having a high dielectric breakdown strength such as silicon carbide (hereinafter referred to as SiC) having a trench gate structure, GaN, and GaO.

Conventionally, there is a SiC semiconductor device having a trench gate structure as a structure in which the channel density is increased so that a large current can flow. In a SiC semiconductor device having such a trench gate structure, high electric field stress is applied to the bottom of the trench, so that dielectric breakdown may occur. Therefore, as shown in Patent Document 1, dielectric breakdown is prevented by forming p-type electric field relaxation layers on both sides of the trench gate so that a high electric field is suppressed from being applied to the bottom of the trench. Is being done. The electric field relaxation layer has a two-layer structure consisting of a high concentration region located below and a low concentration region located above, and these are formed by ion implantation or the like.

Japanese Patent No. 6428489

However, when a p-type electric field relaxation layer having a two-layer structure as in Patent Document 1 is provided, if each layer is formed by ion implantation, a portion where ion implantation is performed twice occurs. In this overlapping portion, the impurity concentration becomes high and injection defects also occur. This injection defect becomes a carrier generation factor when the drain voltage is applied, and causes a problem that it becomes a leak source.

In view of the above points, it is an object of the present invention to provide a semiconductor device capable of suppressing the occurrence of leaks due to injection defects while relaxing the electric field stress on the bottom of the trench by the electric field relaxation layer.

In order to achieve the above object, the semiconductor device according to claim 1 is formed on a substrate (1) made of a first or second conductive type semiconductor and a substrate, and has a lower impurity concentration than the substrate. A drift layer (2) made of a first conductive type semiconductor, a base region (4) made of a second conductive type semiconductor formed on the drift layer, and a base region formed on the upper layer of the base region, from the drift layer. Also consists of a source region (5) composed of a high-concentration first conductive semiconductor and a second conductive semiconductor formed at a position different from the source region in the upper layer of the base region and having a higher concentration than the base region. A gate is formed through a gate insulating film (8) in a trench (7) formed from the surface of the contact region (6) and the source region to a depth deeper than the base region and in which a plurality of conductors are arranged in parallel with one direction as the longitudinal direction. A trench gate structure formed by forming an electrode (9), a source electrode (10) electrically connected to a source region and a contact region, and a drain electrode (12) formed on the back surface side of a substrate. In each of the first region (3a) of the second conductive type formed in the drift layer and deeper than the trench and between the plurality of trenches with the same direction as the longitudinal direction of the trench as the longitudinal direction. It has a second conductive type second region (3b) that is arranged away from the side surface of the trench and connects the first region and the base region, and an electric field relaxation layer (3) that includes the second region. Both the first region and the second region are composed of an ion implantation layer, and the second region has a broken line shape and has a partially thinned structure, and the thinned portion is thinned out. As a region, in the thinned-out region, only the first region is formed in the normal direction with respect to the surface of the substrate.

In this way, the structure is provided with an electric field relaxation layer deeper than the trench, and the electric field relaxation layer is composed of a first region and a second region, and a thinning region is provided in the second region. .. As a result, it is possible to reduce injection defects included in the double injection region (3c), that is, point defects that cause carrier generation when the drain voltage is applied, and it is possible to suppress the occurrence of leaks. Therefore, it is possible to obtain a semiconductor device capable of suppressing the occurrence of leaks due to injection defects while relaxing the electric field stress on the bottom of the trench by the electric field relaxation layer.

The reference numerals in parentheses of each of the above means indicate an example of the correspondence with the specific means described in the embodiment described later.

It is a figure which shows the cross-sectional structure of the SiC semiconductor device which concerns on 1st Embodiment. It is a top layout view of the SiC semiconductor device shown in FIG. It is sectional drawing which showed the equipotential distribution of the SiC semiconductor device in the part provided with the 2nd region. It is sectional drawing which showed the equipotential distribution of the SiC semiconductor device in the thinning-out region which does not have a 2nd region. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device shown in FIG. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device which follows FIG. 4A. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device which follows FIG. 4B. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device which follows FIG. 4C. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device which follows FIG. 4D. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device which follows FIG. 4E. It is sectional drawing which showed the manufacturing process of the SiC semiconductor device which follows FIG. 4F. It is a figure which shows the cross-sectional structure of the SiC semiconductor device which concerns on 2nd Embodiment. It is a top layout view of the SiC semiconductor device which concerns on 3rd Embodiment. It is a top layout view of the SiC semiconductor device which concerns on the modification of 3rd Embodiment. It is a top layout view of the SiC semiconductor device which concerns on the modification of 3rd Embodiment. It is a perspective sectional view of the SiC semiconductor device which concerns on 4th Embodiment. It is a top layout view of the SiC semiconductor device shown in FIG. It is a top layout view of the SiC semiconductor device which concerns on the modification of 4th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, parts that are the same or equal to each other will be described with the same reference numerals.

(First Embodiment)
The first embodiment of the present invention will be described. First, a SiC semiconductor device having a vertical MOSFET having an inverted trench gate structure according to the present embodiment will be described with reference to FIGS. 1 and 2. Although only one cell of the vertical MOSFET is shown in FIG. 1, a plurality of cells having the same structure as the vertical MOSFET shown in FIG. 1 are arranged adjacent to each other.

As shown in FIG. 1, a vertical MOSFET is formed by using ^{an n + type semiconductor substrate 1.} The n ⁺ type semiconductor substrate 1 is a SiC single crystal having a thickness of about 300 μm, which is doped with an n-type impurity such as phosphorus or nitrogen at a high concentration, for example, ^{an impurity concentration of 1 × 10 19} to 1 × 10 ²⁰ cm ^-3. It is configured. On the n ⁺ type semiconductor substrate 1, n-type impurities are doped, for example, 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^-3, which is lower in impurity concentration than the n ⁺ type semiconductor substrate 1, and has a thickness of about 5 to 15 μm. The n-type drift layer 2 made of the above SiC is formed.

An electric field relaxation layer 3 doped with p-type impurities such as boron or aluminum is formed in the n-type drift layer 2. In the present embodiment, the electric field relaxation layer 3 is extended with one direction as the longitudinal direction, and a plurality of electric field relaxation layers 3 are arranged in a stripe shape. The electric field relaxation layer 3 is arranged on both sides of the trench gate structure described later, and the bottom portion of the electric field relaxation layer 3 is formed to a position deeper than the bottom portion of the trench gate structure.

More specifically, the electric field relaxation layer 3 is ^{formed from a position separated from the n +} type semiconductor substrate 1 by a predetermined distance to the surface of the n-type drift layer 2, and is ^{located on the lower side, that is, on the n +} type semiconductor substrate 1. It is composed of one region 3a and a second region 3b located above the first region 3a. As shown in FIGS. 1 and 2, the first region 3a is formed linearly with the same direction as the longitudinal direction of the trench gate structure as the longitudinal direction, and the second region 3b is also formed with a broken line with the same direction as the longitudinal direction. It is formed in a shape. The electric field relaxation layer 3 is formed by connecting the first region 3a and the second region 3b. Therefore, in the case of the present embodiment, when the electric field relaxation layer 3 is viewed as a whole, it has a linear shape with one direction as the longitudinal direction.

That is, in the SiC semiconductor device of the present embodiment, the second region 3b, which has conventionally been linear like the first region 3a, is partially thinned out by making it into a broken line shape. Then, using this thinned-out portion as a thinned-out region, only the first region 3a is formed in the normal direction with respect to the surface ^{of the n + type semiconductor substrate 1.} In the case of the present embodiment, as shown in FIG. 2, the second regions 3b are formed so as to line up on both sides of the trench gate structure in the direction perpendicular to the longitudinal direction of the trench gate structure, and the thinning regions are also in the same direction. It is laid out so that it is lined up. The second regions 3b arranged adjacent to each other on both sides of the trench gate structure have the same length in the longitudinal direction of the trench gate structure, and the respective tip positions are also the same. Further, the thinning regions arranged adjacent to each other on both sides of the trench gate structure also have the same length in the longitudinal direction of the trench gate structure, and the respective tip positions are also the same.

Even if the widths of the first region 3a and the second region 3b, that is, the dimensions in the plane direction parallel to the substrate plane in the direction perpendicular to the longitudinal direction of the trench gate structure are the same, one of them is wider than the other. It does not matter if it is said. In the present embodiment, the first region 3a is wider than the second region 3b, and the first region 3a protrudes from both sides of the second region 3b. For example, the width of the first region 3a is 1.3 μm, the width of the second region 3b is 0.7 μm, and the amount of protrusion of the first region 3a from the second region 3b is 0.3 μm on one side. With such a configuration, the JFET region can be prevented from expanding between the adjacent electric field relaxation layers 3, and the shortest current path between the trench gate structure and the drain electrode 12 described later can be secured, and the on-resistance can be secured. Can be suppressed from rising.

The first region 3a is formed at a position about 1.0 to 2.0 μm away from the surface of the n-type drift layer 2, for example, the p-type impurity concentration is 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ^-3. The degree and depth are about 1.0 to 2.0 μm. On the other hand, the second region 3b is formed from the surface of the n-type drift layer 2 to a position having a depth of about 1.0 to 2.0 μm. The p-type impurity concentration in the second region 3b and the impurity concentration in the first region 3a may be the same or different, but here, the p-type impurity concentration is set higher than that in the first region 3a. For example, the second region 3b has a p-type impurity concentration of about 6 × 10 ¹⁷ to 1 × 10 ²⁰ cm ^-3 and a depth of about 1.0 to 2.0 μm.

Further, as will be described later, both the first region 3a and the second region 3b are composed of an ion implantation layer formed by ion-implanting a p-type impurity, and the first region 3a and the second region 3b are partially formed. The double implantation region 3c is configured by overlapping with. Since it is sufficient that the first region 3a and the second region 3b are in contact with each other and there are few injection defects, it is preferable that the double injection region 3c has almost no thickness. Therefore, the thickness of the double injection region 3c is set to 0 to 0.3 μm. The first region 3a and the second region 3b are made uniform with the above-mentioned impurity concentration in the entire region other than the double injection region 3c.

Further, a p-type base region 4 is formed on the surfaces of the n-type drift layer 2 and the electric field relaxation layer 3. The p-type base region 4 is a layer that constitutes a channel of a vertical MOSFET, and is formed so as to be in contact with the side surface of the trench 7 on both sides of the trench 7 that constitutes the trench gate structure described later.

^{The n +} type source region 5 in which n-type impurities are heavily doped so as to be in contact with the trench gate structure on the trench gate structure side of the surface layer portion of the p-type base region 4 from the position corresponding to the electric field relaxation layer 3. Is formed. In the case of the present embodiment, for example, the n ⁺ type source region 5 is formed with an impurity concentration of ^{about 1 × 10 20} cm ^-3 and a thickness of about 0.3 μm. Further, in the surface layer portion of the p-type base region 4, a ^{position different from the n +} type source region 5, specifically, a position corresponding to the electric field relaxation layer 3, is a p ⁺ type in which p-type impurities are heavily doped. The contact region 6 is formed. In the case of the present embodiment, for example, the p ⁺ type contact region 6 is formed with an impurity concentration of ^{about 1 × 10 20} cm ^-3 and a thickness of about 0.3 μm.

Further, in the cross section of FIG. 1, at the central position of the electric field relaxation layers 3 arranged adjacent to each other, the p-type base region 4 and the n ⁺ -type source region 5 are penetrated to reach the n-type drift layer 2 and the electric field is reached. A trench 7 is formed that is shallower than the bottom of the relaxation layer 3. The trench 7 may have an arbitrary depth as long as it is formed deeper than the bottom of the p-type base region 4 and shallower than the electric field relaxation layer 3, but for example, 0.3 μm from the bottom of the p-type base region 4. It protrudes to some extent and is shallower than the double injection region 3c.

^{The p-type base region 4 and the n +} -type source region 5 are arranged so as to be in contact with the side surface of the trench 7. The inner wall surface of the trench 7 is covered with a gate insulating film 8 made of an oxide film or the like, and the inside of the trench 7 is formed by a gate electrode 9 made of doped Poly-Si formed on the surface of the gate insulating film 8. Is filled up. As described above, the trench gate structure is formed by the structure provided with the gate insulating film 8 and the gate electrode 9 in the trench 7.

The trench gate structure has a strip shape with the direction perpendicular to the paper surface in FIG. 1, the left-right direction on the paper surface in FIG. 2, that is, the same direction as the longitudinal direction of the electric field relaxation layer 3 as the longitudinal direction. Then, a plurality of trench gate structures are arranged in stripes at equal intervals in the left-right direction of the paper surface of FIG. 1, so that the structure is provided with a plurality of cells.

Further, a source electrode 10 is formed on the surfaces of the n ⁺ type source region 5 and the p ^{+ type contact region 6.} The source electrode 10 is made of a plurality of metals such as Ni / Al, and is insulated from the gate electrode 9 via an interlayer insulating film 11. Specifically, the ^{portion connected to the n +} type source region 5 is made of a metal that can make ohmic contact with the n-type SiC, and the portion connected to the p-type base region 4 via the ^{p + type contact region 6 is.} It is composed of a metal that can make ohmic contact with p-type SiC. Although not shown, a gate wiring electrically connected to the gate electrode 9 is formed at a position different from the source electrode 10. The gate wiring and the source electrode 10 are formed so as to be separated from each other so that they are electrically separated from each other. Then, at the position where the interlayer insulating film 11 is not formed, the source electrode 10 is ^{electrically contacted with the n +} type source region 5 and the p ⁺ type contact region 6, and the gate wiring is electrically contacted with the gate electrode 9. Have been made to.

Further, on the back side of the n ⁺ -type semiconductor substrate 1 n ⁺ -type semiconductor substrate 1 and electrically connected to the drain electrode 12 are formed. With such a structure, a vertical MOSFET having an n-channel type inverted trench gate structure is configured.

In the vertical MOSFET configured in this way, when a gate voltage is applied to the gate electrode 9 in a state where the source voltage is 0 and the drain voltage is, for example, 10 V, the side surface of the trench 7 in the p-type base region 4 The part in contact with is the inverted channel area. Then, a current is passed between the source electrode 10 and the drain electrode 12 through the channel region.

On the other hand, when the gate voltage is not applied, a high voltage such as 1400V is applied as the drain voltage when the gate voltage and the source voltage are 0. In SiC, which has an electric field breaking strength nearly 10 times that of a silicon device, an electric field nearly 10 times that of a silicon device is applied to the gate insulating film 8 due to the influence of this voltage, and the gate insulating film 8, especially the trench 7 of the gate insulating film 8 is applied. Electric field concentration can occur at the bottom of the.

However, in the present embodiment, the structure is provided with the electric field relaxation layer 3 deeper than the trench 7. Therefore, the depletion layer at the PN junction between the electric field relaxation layer 3 and the n-type drift layer 2 in the electric field relaxation layer 3 extends significantly toward the n-type drift layer 2, and the high voltage due to the influence of the drain voltage is gated. It becomes difficult to enter the insulating film 8. In particular, since the first region 3a is wider than the second region 3b and the distance between the first regions 3a is narrowed, it becomes more difficult for a high voltage due to the influence of the drain voltage to enter the gate insulating film 8. ..

Therefore, it is possible to alleviate the electric field concentration in the gate insulating film 8, particularly the electric field concentration in the bottom of the trench 7 in the gate insulating film 8. As a result, it becomes a high withstand voltage SiC semiconductor device capable of preventing the gate insulating film 8 from being destroyed.

Further, in the present embodiment, the second region 3b is not formed in the entire area on the first region 3a, but is partially thinned out as a broken line so that the thinned out region is provided. Therefore, since the thinning region is provided, the double injection region where the first region 3a and the second region 3b overlap is compared with the case where the second region 3b is formed over the entire area on the first region 3a. The area ratio of 3c can be reduced. As a result, it is possible to reduce the injection defects included in the double injection region 3c, that is, the point defects that cause carrier generation when the drain voltage is applied, and it is possible to suppress the occurrence of leaks. Therefore, it is possible to obtain a SiC semiconductor device capable of suppressing the occurrence of leaks due to injection defects while relaxing the electric field stress on the bottom of the trench by the electric field relaxation layer 3.

The first region 3a of the electric field relaxation layer 3 plays a major role in the electric field relaxation based on the suppression of the entry of high voltage due to the influence of the drain voltage. However, in comparison with this, in the second region 3b, the electrical connection between the first region 3a and the p-type base region 4 plays a main role, and the contribution to the electric field relaxation is not large. Therefore, even if the thinning region is provided in the second region 3b, the role of the electric field relaxation by the electric field relaxation layer 3 can be sufficiently fulfilled.

As a reference, when the equipotential distribution when the gate electrode 9 and the source electrode 10 were set to 0 V and the drain voltage was set to a high voltage was investigated, as shown in FIGS. 3A and 3B, the portion provided with the second region 3b was investigated. The distribution was almost the same as when the thinned area was used. From this, it can be seen that even if the second region 3b is not provided in the entire area on the first region 3a, the role of electric field relaxation is sufficiently played.

Next, a method of manufacturing the trench gate type vertical MOSFET shown in FIG. 1 will be described with reference to FIGS. 4A to 4H.

[Step shown in FIG. 4A]
First, an epi substrate in which an n-type drift layer 2 is epitaxially grown on the surface of an n ⁺ -type semiconductor substrate 1 made of a SiC single crystal doped with n-type impurities at a high concentration is prepared. However, at this time, not all of the n-type drift layer 2 is formed, and a part of the n-type drift layer 2 on the surface side is not yet formed.

[Step shown in FIG. 4B]
An ion implantation mask (not shown) is placed on the n-type drift layer 2, and the p-type impurities are ion-implanted into the surface layer portion of the n-type drift layer 2 using the mask. Then, the first region 3a is formed by activating the impurities injected by heat treatment or the like.

[Step shown in FIG. 4C]
After removing the mask for ion implantation, the rest of the n-type drift layer 2 is epitaxially grown again. Further, an ion implantation mask (not shown) is arranged, and the p-type impurity is ion-implanted into the newly formed portion of the n-type drift layer 2 using the mask. At this time, the p-type impurities are injected only into the region to be formed in the second region 3b, and are not injected into the thinned region. Then, the second region 3b is formed by activating the impurities injected by heat treatment or the like, and then the ion implantation mask is removed. As a result, the electric field relaxation layer 3 in which the first region 3a and the second region 3b are connected is formed.

[Step shown in FIG. 4D]
The p-type base region 4 is epitaxially grown on the surfaces of the n-type drift layer 2 and the electric field relaxation layer 3.

[Step shown in FIG. 4E]
An etching mask (not shown) that opens the region where the trench 7 is to be formed is arranged while covering the surface of the p-type base region 4. Then, after anisotropic etching using an etching mask, isotropic etching and sacrificial oxidation steps are performed as necessary to form the trench 7. As a result, it is arranged so as to be shallower than the electric field relaxation layer 3 and separated from the second region 3b between the adjacent second regions 3b while penetrating the p-type base region 4 and reaching the n-type drift layer 2. The trench 7 can be formed.

Next, the gate insulating film 8 is formed by removing the etching mask and then performing a gate oxidation step. Further, a polysilicon layer doped with impurities is formed on the surface of the gate insulating film 8 and then patterned to form the gate electrode 9. As a result, a trench gate structure is formed.

[Step shown in FIG. 4F]
After forming a mask (not shown) on the surface of the p-type base region 4 in which the region to be formed of the n ⁺ -type source region 5 opens, an n-type impurity is ion-implanted at a high concentration from above to form the n ⁺ -type source region 5 To form. ^{Similarly, after forming a mask (not shown) in which the region to be formed of the p +} type contact region 6 opens on the surface of the p-type base region 4, p-type impurities are ion-implanted at a high concentration from above to form the p ⁺ type. The contact region 6 is formed.

[Step shown in FIG. 4G]
After the interlayer insulating film 11 is formed, the interlayer insulating film 11 is patterned to ^{expose the n +} type source region 5 and the p-type base region 4, and the contact hole for exposing the gate electrode 9 is a cross section different from the cross section shown in the drawing. Form in. Then, after forming an electrode material so as to embed the inside of the contact hole, the source electrode 10 and a gate wiring (not shown) are formed by patterning the electrode material.

After that, ^{by forming the drain electrode 12 on the back surface side of the n +} type semiconductor substrate 1, the vertical MOSFET shown in FIG. 1 is completed.

As described above, in the present embodiment, the structure is provided with the electric field relaxation layer 3 deeper than the trench 7, and the electric field relaxation layer 3 is composed of the first region 3a and the second region 3b. A thinning area is provided in the two areas 3b. As a result, it is possible to reduce the injection defects included in the double injection region 3c, that is, the point defects that cause carrier generation when the drain voltage is applied, and it is possible to suppress the occurrence of leaks. Therefore, it is possible to obtain a SiC semiconductor device capable of suppressing the occurrence of leaks due to injection defects while relaxing the electric field stress on the bottom of the trench by the electric field relaxation layer 3.

(Second Embodiment)
The second embodiment will be described. This embodiment is different from the first embodiment because the relationship between the trench gate structure and the electric field relaxation layer 3 is changed from that of the first embodiment, and the other parts are the same as those of the first embodiment. Will be described only.

As shown in FIG. 5, in the present embodiment, the depth of the bottom surface of the trench 7 is made to coincide with the boundary position between the first region 3a and the second region 3b. That is, the upper end position of the first region 3a and the bottom surface of the trench 7 are made to be flush with each other.

As described above, by providing the electric field relaxation layer 3, the depletion layer at the PN junction between the electric field relaxation layer 3 and the n-type drift layer 2 is greatly extended to the n-type drift layer 2 side, and is high due to the influence of the drain voltage. The voltage is made difficult to enter the gate insulating film 8. As a result, the electric field concentration at the bottom of the trench 7 can be relaxed, but if the trench 7 is too shallow, it is pulled by the potential of the gate electrode 9 which has become the ground potential, and the depletion layer becomes more at the bottom of the trench 7. It penetrates deeply to the side and deeply into the double injection region 3c. On the other hand, when the bottom surface of the trench 7 is aligned with the upper end position of the first region 3a as in the present embodiment, the trench 7 is positioned downward and is pulled to the potential of the gate electrode 9 which has become the ground potential. It becomes difficult for the depletion layer to enter. Therefore, it is possible to suppress the depletion layer from entering the double injection region 3c, and to prevent the double injection region 3c from becoming a carrier generation factor and becoming a leak source.

(Third Embodiment)
The third embodiment will be described. This embodiment is a modification of the layout of the electric field relaxation layer 3 with respect to the first and second embodiments, and is the same as the first and second embodiments except for the first and second embodiments. Only the part different from the form will be described.

As shown in FIG. 6, in the present embodiment, the second region 3b is staggered so that the portion where the first region 3a and the second region 3b are connected is staggered. Specifically, the second regions 3b provided in the electric field relaxation layers 3 located on both sides of the trench gate structure are arranged so as to be offset in the longitudinal direction. As a result, the second regions 3b located on both sides of the trench gate structure are arranged so as not to be lined up in the direction perpendicular to the longitudinal direction of the trench gate structure. Similarly, the thinned-out regions are not lined up in the direction perpendicular to the longitudinal direction of the trench gate structure, but are provided at offset positions.

Here, on both sides of the trench gate structure, the length of the second region 3b and the length of the thinned-out region in the longitudinal direction of the trench gate structure are made the same. Then, as shown by the broken line in the figure, one end of the second region 3b provided in one electric field relaxation layer 3 sandwiching the trench gate structure and the other second region 3b provided in the other electric field relaxation layer 3 The edges are aligned.

In this way, when the second region 3b is arranged in a staggered manner, the second region 3b is uniformly arranged over a wide range as compared with the case where the second region 3b is arranged in a straight line as in the first embodiment. Will be. Therefore, it is possible to make the electric field relaxation effect uniform in the entire chip on which the SiC semiconductor device is formed.

(Modified example of the third embodiment)
In the third embodiment, the length of the second region 3b and the length of the thinning region in the longitudinal direction of the electric field relaxation layer 3 are made the same, but they may be different. For example, as shown in FIG. 7, the second region 3b is made longer than the thinning region, and the electric field relaxation layers 3 located on both sides of the trench gate structure in the direction perpendicular to the longitudinal direction of the trench gate structure. The second regions 3b provided in the above may partially overlap each other. Further, as shown in FIG. 8, the thinning region is made longer than the second region 3b, and the electric field relaxation located on both sides of the trench gate structure in the direction perpendicular to the longitudinal direction of the trench gate structure. A gap may be provided between the second regions 3b provided in the layer 3.

(Fourth Embodiment)
A fourth embodiment will be described. This embodiment is a modification of the layout of the electric field relaxation layer 3 with respect to the first and second embodiments, and is the same as the first and second embodiments except for the first and second embodiments. Only the part different from the form will be described. Although the case where the structure of the present embodiment is applied to the first embodiment is given as an example here, it can also be applied to the second embodiment.

In the present embodiment, as shown in FIGS. 9 and 10, the second region 3b has the same direction as the trench gate structure as the longitudinal direction, but the first region 3a has a direction intersecting the second region 3b, here. Then, the vertical direction is the longitudinal direction.

In this way, even if the longitudinal direction of the first region 3a and the longitudinal direction of the second region 3b are different, the double injection region 3c is formed at the intersecting portion. Therefore, also in this case as well, instead of forming the first region 3a and the second region 3b so as to overlap all of them, a thinning region is provided in the second region 3b so that the portion that does not overlap with the first region 3a is provided. Make sure to provide. That is, a thinning region is provided in the second region 3b at least at least a part of the intersection of the straight line along the longitudinal direction of the first region 3a and the straight line along the longitudinal direction of the second region 3b.

Specifically, as shown in FIG. 10, one side of the second region 3b arranged on both sides of the trench gate structure, here, the second region 3b on the upper side in the drawing is made linear. , It overlaps with each of the orthogonal first regions 3a. In the region where the first region 3a and the second region 3b overlap, a double injection region 3c as shown by a broken line in the figure is formed. On the other hand, the other side of the second region 3b arranged on both sides of the trench gate structure, here, the second region 3b on the lower side in the drawing is formed in a broken line shape, and the portion where the first region 3a is arranged is thinned out. By making it a region, the second region 3b does not overlap with each first region 3a.

In this way, even when the structure is such that the first region 3a and the second region 3b intersect, the area ratio of the double injection region 3c can be reduced by providing the thinning region in the second region 3b. .. As a result, it is possible to obtain the same effect as in the first and second embodiments.

Since the second region 3b located below the paper surface of FIG. 10 does not overlap with the first region 3a, it does not play a role of connecting the first region 3a and the p-type base region 4. Therefore, it is possible not to form the second region 3b of this portion. However, if the second region 3b of this portion is not formed, the region in which the p-type layer is not formed will be formed in a wide range, and the equipotential lines will penetrate closer to the surface side, and the withstand voltage reliability. May decrease. Therefore, even in the case where the second region 3b is not electrically connected to the first region 3a as in the present embodiment, it is possible to ensure the withstand voltage reliability by providing the second region 3b. It becomes.

(Modified example of the fourth embodiment)
In the case where the first region 3a and the second region 3b intersect with each other as in the fourth embodiment, the portions where the first region 3a and the second region 3b are connected may be arranged in a staggered manner. it can. For example, as shown in FIG. 11, the second regions 3b located on both sides of the trench gate structure can be configured to be alternately connected to the adjacent first regions 3a, respectively. Specifically, the second region 3b located above the paper surface in FIG. 11 is connected at a portion overlapping the first region 3a on the right side of the paper surface at the upper right of the paper surface, and a thinning area is provided at the upper left of the paper surface. It is designed so that it does not overlap with the first region 3a on the left side of the paper. Further, the second region 3b located below the paper surface is connected at a portion overlapping the first region 3a on the left side of the paper surface at the lower left of the paper surface, and a thinning area is provided at the lower right of the paper surface to provide the first region on the right side of the paper surface. It is designed so that it does not overlap with 3a. With such a configuration, the portions where the first region 3a and the second region 3b are connected can be arranged in a staggered manner.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and can be appropriately modified within the scope of the claims.

For example, the portion of the n-type drift layer 2 located above the first region 3a, that is, the portion where the second region 3b is formed, is n more than the other portion of the n-type drift layer 2. The type impurity concentration may be increased. As a result, the portion of the n-type drift layer 2 located between the second regions 3b functions as a current dispersion layer having a higher n-type impurity concentration than the portion located below it, and flows from the channel. The current can be dispersed over a wider area and flow, which can contribute to low on-resistance.

Further, in the above embodiment, the second region 3b is arranged in a broken line shape and the space between them is a thinned out region. However, the second region 3b does not necessarily have to be in a broken line shape, and a part of the second region 3b is cut out. Any structure may be used as long as it is a thinned area. Although the size of the thinning region is arbitrary, the cross-sectional area of the second region 3b, which is the current path when the avalanche breakdown occurs, becomes narrower due to the formation of the thinning region. It is advisable to determine the dimensions of the thinning area in consideration of the withstand voltage when down.

Further, in each of the above embodiments, an n-channel type MOSFET in which the first conductive type is an n-type and the second conductive type is a p-type has been described as an example, but the conductive type of each component is inverted p. The present invention can also be applied to channel type MOSFETs. Further, in the above description, although the MOSFET having a trench gate structure has been described as an example, the present invention can be applied to an IGBT having a similar trench gate structure. The IGBT only changes the conductive type of the substrate 1 from the n type to the p type for each of the above embodiments, and is the same as each of the above embodiments in terms of other structures and manufacturing methods. Further, although the SiC semiconductor device has been described as an example of the semiconductor device made of a material having high dielectric breakdown strength, a semiconductor device using another material such as GaN or GaO may be used.

1 n ⁺ type semiconductor substrate 2 n type drift layer 3 Electric field relaxation layer 3a 1st region 3b 2nd region 4 p type base region 5 n ⁺ type source region 7 Trench 8 Gate insulating film 9 Gate electrode

Claims (7)

A substrate (1) made of a first or second conductive type semiconductor,
A drift layer (2) formed on the substrate and made of a first conductive type semiconductor having a lower impurity concentration than the substrate,
A base region (4) made of a second conductive type semiconductor formed on the drift layer and
A source region (5) formed in the upper layer of the base region and composed of a first conductive type semiconductor having a higher concentration than the drift layer,
In the upper layer of the base region, a contact region (6) formed at a position different from the source region and composed of a second conductive type semiconductor having a higher concentration than the base region,
A gate electrode (9) is formed via a gate insulating film (8) in a trench (7) formed from the surface of the source region to a depth deeper than the base region and in which a plurality of electrodes are arranged in parallel with one direction as the longitudinal direction. A trench gate structure constructed by being formed,
A source electrode (10) electrically connected to the source region and the contact region,
A drain electrode (12) formed on the back surface side of the substrate and
Between the first region (3a) of the second conductive type, which is arranged in the drift layer and formed at a position deeper than the trench, and a plurality of the trenches with the same direction as the longitudinal direction of the trench as the longitudinal direction. Each has an electric field relaxation layer (3) that is arranged away from the side surface of the trench and includes a second conductive type second region (3b) that connects the first region and the base region. ,
Both the first region and the second region are composed of an ion implantation layer, and the second region has a broken line shape and a partially thinned structure, and the thinned portion is interleaved. As a thinning region, a semiconductor device in which only the first region is formed in the thinning region in the normal direction with respect to the surface of the substrate. The first region is formed linearly on both sides of the trench gate structure with the same direction as the longitudinal direction of the trench gate structure as the longitudinal direction.
The semiconductor device according to claim 1, wherein the second region is arranged in a broken line shape on the first region. A claim that the second regions located on both sides of the trench gate structure are staggered in the longitudinal direction, and portions connecting the first region and the second region are staggered. 2. The semiconductor device according to 2. The semiconductor device according to claim 1, wherein the first region is formed with a direction intersecting the longitudinal direction of the trench gate structure as a longitudinal direction. A claim that the thinning region is provided in the second region at least in a part of a portion where a straight line along the longitudinal direction of the first region and a straight line along the longitudinal direction of the second region intersect. 4. The semiconductor device according to 4. In a plurality of portions where a straight line along the longitudinal direction of the second region intersects the first region, a portion where the second region and the first region overlap and the thinning region are alternately arranged.
For each of the second regions located on both sides of the trench gate structure, the portion to be the thinned-out region is shifted in the longitudinal direction, so that the portion connecting the first region and the second region is formed. The semiconductor device according to claim 5, which is arranged in a staggered pattern. The semiconductor device according to any one of claims 1 to 6, wherein the bottom surface of the trench is flush with the upper end surface of the first region.

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