JP2001352066A - Insulated-gate power ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent decrease in the non-defective rate, simplify the processing of a lead frame, reduce the size of a package, even if the chip size is increased, and to make an IC applicable even to a device of such a structure as to be cooled from the surface of a chip. SOLUTION: This insulated-gated power IC comprises a plurality of cell blocks 12 formed on a chip 1, a plurality of independent gate electrodes formed on the cell blocks 12 respectively, a plurality of gate pads 18 connected to the gate electrodes formed on the chip 1 respectively, and a plurality of pads 19, having the emitter potential formed on the chip 1 which are formed so as to be adjacent to the gate pads 18. Due to this structure, gate pads 18 of cell blocks 12 of defective products can be wire-bonded to pads 19 having emitter potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an insulated gate power IC having a gate electrode for current control on a surface of a semiconductor substrate.

[0002]

2. Description of the Related Art For example, an IGBT (Insulated Gate Bipolar Transistor) which is a power IC for high breakdown voltage and large current
In the above, when the chip size is increased, the ratio of the area occupied by a pressure-resistant structure (eg, a guard ring structure) provided on the outer peripheral portion of the chip can be reduced. Further, since the number of parts can be reduced, it is possible to obtain an effect that the assembly structure can be simplified and the cost can be reduced. For this reason, it is desirable to make a large chip.
In the case of the A type IGBT module, the required chip size is about 20 mm square.

On the other hand, in a semiconductor wafer process for manufacturing an IGBT, a defect such as a short circuit between a gate and an emitter may occur due to a defect caused by, for example, particles. And IGBT
Field-effect transistors control the current flowing between the collector and the emitter by controlling the voltage applied to the gate electrode. However, the gate-emitter short circuit and insulation can be maintained even at one place on the chip. Otherwise, normal control cannot be performed and the chip cannot be used. Further, the above-mentioned defects are more likely to occur as the chip size becomes larger, and there is a problem that the yield rate (i.e., the yield) decreases.

As a technique for solving such a problem,
There is a method of manufacturing an IGBT described in JP-A-8-191145. This method proposes that the IGBT is divided into a plurality of cell blocks (gate blocks), and that wiring extraction from each gate block to a gate bonding pad common to each block has a two-layer wiring structure. In the case of the above method, during the semiconductor wafer process, that is, after forming the first layer gate wiring set individually for each block, for a plurality of cell blocks, whether or not each gate-emitter is short-circuited, Pass / fail judgment is made. Then, an interlayer insulating film is formed, and according to the result of the pass / fail determination, a polyimide solution is dropped on a via hole of each block provided in the interlayer insulating film by a dispenser or the like, and only the first-layer gate wiring of a non-defective cell block is formed. Is connected to the second-layer gate wiring, and the first-layer gate wiring of the defective cell block is cut off from the second-layer gate wiring to form a two-layer wiring that is short-circuited to the source electrode.

According to this method, even when a defective block exists in a plurality of cell blocks, an IGBT can be constituted only by non-defective cell blocks.
The BT operates normally. Therefore, it is possible to prevent the non-defective product rate from decreasing.

[0006]

However, according to the method disclosed in the above publication, pass / fail judgment is made for a plurality of cell blocks in the course of a semiconductor wafer process, and then only non-defective cell blocks are selected and applied to the gate bonding pads. Since a semiconductor wafer process for forming a multi-layer wiring structure to be connected must be performed, there is a disadvantage that the process becomes very complicated. Also, it is actually quite difficult to measure the electrical characteristics and determine the quality of the cell block during the semiconductor wafer process (the above publication does not disclose any specific method). At the same time, it is considered that it is almost impossible to actually use the method of the above-mentioned publication because the manufacturing equipment is contaminated.

On the other hand, the applicant of the present invention has invented a configuration for solving the drawbacks of the method disclosed in the above publication, and has filed an application (Japanese Patent Application No. Hei.
No. 1-288250). This application is not yet published. In the configuration of the above-mentioned application, independent gate electrodes are provided for each of the plurality of cell blocks, and a plurality of gate pads respectively connected to these gate electrodes are provided.

[0010] According to this configuration, by using the plurality of gate pads, it is possible to easily determine the quality of the plurality of cell blocks using a known inspection device. In this configuration, only the gate pads of the non-defective cell blocks are connected to external gate terminals by, for example, wire bonding. For this reason, even when there is a defective product in a plurality of cell blocks, a semiconductor device (insulated gate type power IC) can be constituted only by non-defective cell blocks, and the semiconductor device can operate normally. Therefore, it is possible to prevent the non-defective product rate (yield) from decreasing.

In the above configuration, the number of semiconductor wafer processes is the same as in the conventional configuration. Therefore,
Even when the chip size of the semiconductor device is increased, it is possible to prevent the yield rate from lowering and prevent the semiconductor wafer process from becoming complicated.

FIGS. 17 and 18 show examples of the configuration of the above-mentioned application. In the example shown in FIG. 17, a plurality of gate pads 102a to 102g are provided on the upper side of the surface of the IGBT chip 101.
102f are provided, and these gate pads 102f are provided.
a to 102f are connected to respective gate electrodes (not shown) of a plurality of cell blocks (not shown). A plurality of emitter pads 103a are provided on the surface of the chip 101.
〜１０103f are provided.

In this configuration, the gate pads 102a, 102c to 102f connected to the gate electrodes of the non-defective cell blocks of the plurality of cell blocks are connected to the external gate terminals 104 by wire bonding, and the defective cells are removed. The gate pad 102b connected to the gate electrode of the cell block is connected to the external ground terminal 105 by wire bonding. The emitter pads 103a to 103f are connected to the external emitter terminal 106 by wire bonding.

However, in the case of the above configuration, the ground terminal 105 must be separately formed almost in parallel with the gate terminal 104 as an external electrode (ie, lead frame) of the chip 101, so that the processing of the lead frame becomes complicated. And the manufacturing cost may increase accordingly. In addition, there is also a problem that the package size becomes large because the lead frame becomes large. Further, since the bonding wire connecting the gate pad 102b of the defective cell block and the ground terminal 105 becomes longer, there is a possibility that this bonding wire may come into contact with another bonding wire.

On the other hand, in the example shown in FIG. 18, the ground terminal 105 is not provided outside, and the gate pad 102b connected to the gate electrode of the defective cell block is connected to the emitter pad 103b by wire bonding. It is composed. In this configuration, it is not necessary to provide the ground terminal 105 on the lead frame.
The processing of the lead frame is simplified, and the manufacturing cost is correspondingly reduced. Further, the package size does not increase, and the bonding wire does not contact another bonding wire.

However, in the configuration of FIG.
01 to cool from the surface
That is, in the case of a configuration in which a flat emitter terminal for a heat sink is soldered to the surface of the chip 101 so as to be connected to the emitter pads 103a to 103f, the gate pad 102b of the defective cell block is connected to the emitter pad 10b.
Therefore, the flat-shaped emitter terminal cannot be soldered to the surface of the chip 101. Therefore, the chip shown in FIG. 18 has a disadvantage that it cannot be applied to a device having a structure for cooling from the surface of the chip 101.

That is, in the case of the configuration of the above-mentioned application (see FIG. 17 and FIG. 18), some of the above-mentioned problems are problems to be improved.

Accordingly, an object of the present invention is to prevent a decrease in the non-defective product rate even when the chip size is increased, and to prevent the semiconductor wafer process from becoming complicated, and furthermore, to process a lead frame. To reduce the package size, prevent the bonding wire from contacting other bonding wires, and
An object of the present invention is to provide an insulated gate power IC that can be applied to a device having a structure that cools from the surface of a chip.

[0017]

According to the first aspect of the present invention, a plurality of cell blocks are provided on a surface of a semiconductor substrate, and gate electrodes independent of each other are provided on the cell blocks. Since a plurality of gate pads connected to each other are provided, even if the chip size is increased, it is possible to prevent the yield rate from decreasing and to prevent the semiconductor wafer process from becoming complicated. In the case of the first aspect of the present invention, since a plurality of pads having an emitter potential are provided on the semiconductor substrate so as to be adjacent to the gate pad, the gate pad connected to the gate electrode of the defective cell block is set to the emitter potential. It becomes possible to connect to the pad by wire bonding. This eliminates the need to provide the ground terminal on the lead frame, thereby simplifying the processing of the lead frame and lowering the manufacturing cost accordingly. Further, the package size does not increase, and the bonding wire does not contact another bonding wire. Further, since the pad having the emitter potential is only arranged adjacent to the gate pad, it becomes possible to solder the emitter terminal for the heat sink to the surface of the chip. Therefore,
The present invention can also be applied to a device having a structure that cools from the surface of the chip 1.

According to the second aspect of the present invention, a gate pad connected to a gate electrode of a non-defective cell block of the plurality of cell blocks is connected to an external gate terminal and a gate of a defective cell block is connected. Since the gate pad connected to the electrode is connected to the pad having the emitter potential, even when the chip size is increased, it is possible to prevent the non-defective product rate from decreasing and to prevent the semiconductor wafer process from becoming complicated. it can.

According to the third aspect of the present invention, the gate pad connected to the gate electrode of the cell block having the uniform threshold voltage Vth among the plurality of cell blocks is connected to an external gate terminal and is not uniform. The gate pad connected to the gate electrode of the cell block having the threshold voltage Vth is connected to the pad having the emitter potential. According to this configuration, the insulated gate power IC
Since the threshold voltage Vth of each cell block in the
The current flows uniformly in each cell block, and it is possible to prevent a reduction in the breakdown strength of the chip. By the way, if the threshold voltage Vth of one cell block in the insulated gate power IC is lower than that of the other, the current will flow intensively in the one cell block, so that the chip withstand voltage will be less. descend.

According to a fourth aspect of the present invention, the semiconductor device further comprises an emitter pad provided on a front surface of the semiconductor substrate and connected to an emitter electrode; a collector electrode provided on a back surface of the semiconductor substrate; A collector terminal for a heat sink soldered to be connected to the collector electrode; and an emitter terminal for a heat sink soldered to be connected to the emitter pad on a surface of the semiconductor substrate; and The semiconductor substrate, the gate terminal, the collector terminal, and the emitter terminal are provided with a resin for molding. This configuration is a device capable of cooling from both sides of the chip via the emitter terminal and the collector terminal for the heat sink.

According to a fifth aspect of the present invention, there is provided an emitter pad provided on a surface of the semiconductor substrate and connected to an emitter electrode, an external emitter terminal connected to the emitter pad, and Executing the connection between the pad and the gate terminal by wire bonding;
It is preferable that the connection between the gate pad and the pad having the emitter potential is performed by wire bonding, and the connection between the emitter pad and the emitter terminal is performed by wire bonding.

Further, according to the invention of claim 6, further comprising a plurality of first gate pads provided on the semiconductor substrate and respectively connected to the plurality of gate electrodes, and an emitter pad provided on the semiconductor substrate and connected to the emitter electrode And a plurality of second gate pads provided in the emitter pad arrangement region and connected to the plurality of gate electrodes, respectively, and connected to a gate electrode of a non-defective cell block of the plurality of cell blocks. And an insulating layer provided so as to cover the formed second gate pad. According to this configuration, when soldering the flat heat sink terminal for the heat sink to the emitter pad of the chip, the second gate pad connected to the gate electrode of the defective cell block can be connected to the emitter pad. Therefore, substantially the same effects as those of the first aspect can be obtained.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment in which the present invention is applied to an IGBT (insulated gate bipolar transistor) will be described below with reference to FIGS.
First, FIG. 3 is a schematic vertical cross-sectional view schematically showing a vertical cross-sectional structure of the IGBT chip 1 of the present embodiment. As shown in FIG. 3, the IGBT of this embodiment is a trench gate type IGB.
T. The IGBT chip 1 includes, for example, a p + substrate (p + silicon substrate) 2 which is a semiconductor substrate, and an n + buffer layer 3 and an n− drift layer 4 are sequentially formed on the p + substrate 2 by an epitaxial growth method. Is formed.

On the upper surface of the n-drift layer 4, p
A base layer 5 is formed. This p base layer 5 includes
A large number of trenches 6 are formed so as to penetrate the p base layer 5 and reach the n-drift layer 4. Trench 6
, A gate electrode 8 is formed via a gate insulating film 7. The gate insulating film 7 is formed of, for example, a silicon oxide film or an ONO film, and the gate electrode 8 is formed of, for example, polycrystalline silicon.

Further, a high-concentration n + emitter layer 9 is selectively formed in a portion of the surface of the p base layer 5 which is in contact with the upper part of the trench 6. An emitter electrode 10 is formed on the upper surface of p base layer 5 so as to be in contact with p base layer 5 and n + emitter layer 9. A collector electrode 11 is formed on the back surface (lower surface) of the p + substrate 2.

Here, the surface of the IGBT chip 1 having the above-described configuration, that is, the surface of the semiconductor substrate 2 is a plurality of (ie, two or more) cell blocks 12 (12a, 12a,
12b, 12c,...) (See also FIG. 2). That is, a plurality of cell blocks 12 (12a, 12b, 1) are provided on the surface of the IGBT1 chip.
2c,...) Are provided. In addition, cell block 1
The preferred number of 2 changes depending on the size of the IGBT 1 chip.
As shown in the above, for example, six are provided, but the number is not limited to this, and it is preferable to provide about 10 to 20.

Then, each cell block 12 (12a, 1a,
2b, 12c,...)
Are independent of each other for each cell block (ie, electrically
Separated). Where adjacent
Schematic vertical cross-section of the boundary between two cell blocks 12, 12
The figure is shown in FIG. As shown in FIG. 4, two cells
An oxide film for isolation is provided at the boundary between the blocks 12 and 12.
(Si0₂Film 13 is formed, and the oxide film 13
The gate electrodes 8a and 8b which are electrically separated from each other
Has been established. On the gate electrodes 8a, 8b, 8
Insulation film (Si0 ₂A film 14 is formed. Soshi
The left gate electrode 8a is located in the left cell block 12.
Of the right gate electrode 8
b is applied to all the gate electrodes 8 in the right cell block 12.
It is connected.

The number of MOSFET cells provided in one cell block 12 (ie, the number of gate electrodes 8 or trenches 6) varies depending on the cell pitch and cell area size (cell block size). , For example, about several hundred to several thousand. This is because the cell pitch is usually about several μm, and the size of the cell area is about several mm square. Then, one cell block 1
As shown in FIG. 3, the gate electrode 8 in
Are all connected to each other. In addition, the emitter electrodes 10 in one cell block 12 are all connected to each other by a wiring layer 16 as shown in FIG.

FIG. 2 is a schematic plan view schematically showing the planar structure of the IGBT chip 1 described above. As shown in FIG. 2, the chip 1 of the IGBT is formed in a substantially rectangular flat plate shape, and the surface thereof has a portion corresponding to a plurality of cell blocks 12 (12a, 12b, 12c,...). , A plurality of emitter pads 17 having substantially the same shape (or a slightly smaller shape) as the cell block 12.
a, 17b, 17c,...).

Further, a plurality of gate pads 18 (18a, 18b, 18c,...) Having a substantially square shape are provided on the upper side in FIG. 2, which is one side of the surface of the IGBT 1 chip.
..) Correspond to the emitter pads 17 (17a, 17b, 1).
7c,...).

Further, the gate pads 18 (18a, 18b, 18c,...) On the surface of the chip of the IGBT 1 are formed.
..), A plurality of substantially square pads 19 are provided.
(19a, 19b, 19c,...) Are provided, for example, every other one. These pads 19 (19a, 19
, b) are connected to the emitter pad 17 (17a, 17b, 17c,...) by a wiring 20, and have an emitter potential. In the case of this configuration, the pads 19 (19a, 19a) having the emitter potential
b, 19c,...) are provided on the surface of the chip 1 so as to be adjacent to the gate pads 18 (18a, 18b, 18c,...).

The emitter pads 17 (17)
a, 17b, 17c,...) are formed so as to be connected to a large number of emitter electrodes 10 in each cell block 12 as shown by a two-dot chain line in FIG. It also has the function of Each emitter pad 17 is for establishing electrical conduction with the outside of the chip 1. In the case of this embodiment, the emitter pad 21 is provided outside the chip 1 (see FIGS. 1, 5, and 6). )
Are connected by, for example, soldering.

The emitter terminal 21 is an external electrode (for example, a lead frame), and as shown in FIG. 6, is composed of a substantially L-shaped conductor plate as a whole. In this case, the emitter terminal 21 has a rectangular portion 21a and a rectangular extension 21b. In the case of the present embodiment, the emitter terminal 21 is provided with a heat sink (that is, a heat sink).
It also has a function as That is, the emitter terminal 2
Reference numeral 1 denotes an emitter terminal for a heat sink;
Is cooled from its surface.

Each of the gate pads 18 (18a, 18a,
18b, 18c,...) Are connected to a number of gate electrodes 8 in each cell block 12 via the wiring layer 15. In this case, the wiring layer 15 is drawn out in a horizontal direction, and is arranged along a vertical side portion of the emitter pad 17 in FIG. 2 (that is, a portion between the two emitter pads 17). 18.

Each gate pad 18 is for establishing electrical continuity with the outside of the IBGT chip 1. In the case of this embodiment, each gate pad 18 is provided with a gate terminal 2 provided outside the chip 1.
2 (see FIG. 1) by, for example, wire bonding. Here, the gate pad 18 connected to the gate terminal 22 is connected to the gate electrode 8 of the non-defective cell block 12.
(For example, the gate pads 18a and 18c to 18f). Thereby, the gate electrode 8 (gate pad 18) of the non-defective cell block 12 is formed.
a, 18 c to 18 f) and the gate terminal 22 are connected by a bonding wire 23. As a result, a signal for gate control is externally supplied to the gate terminal 2.
2, the signal is transmitted to a non-defective cell block 12
, And the elements in the non-defective cell block 12 operate.

On the other hand, the defective cell block 12
The gate pad 18 (for example, the gate pad 18b) connected to the gate electrode 8 is connected to a pad 19a having an emitter potential on the chip 1 by, for example, wire bonding, as shown in FIG. This allows
The defective gate pad 18 (18b) and the pad 19a are connected by the bonding wire 23. As a result, the gate electrode 8 (gate pad 18b) of the defective cell block 12 is fixed at the emitter potential (that is, GND potential).

Thus, no gate control signal is applied to the gate electrode 8 of the defective cell block 12, so that the elements in the defective cell block 12 do not operate. Incidentally, the gate terminal 22 is an external electrode, and is constituted by, for example, a lead frame (a part thereof).

The collector electrode 11 provided on almost the entire back surface of the chip 1 also has a function as a pad for establishing electrical conduction with the outside of the chip 1, and in the case of this embodiment, The collector terminal 24 (see FIGS. 5 and 6) provided outside the chip 1 is connected by, for example, soldering. The collector terminal 24 is an external electrode (for example, a lead frame), and as shown in FIG. 6, is composed of a substantially L-shaped conductor plate as a whole. In this case, the collector terminal 24 has a rectangular portion 24a and a rectangular extension 24b (see FIGS. 5 and 6).

The collector terminal 24 also has a function as a heat sink (ie, a heat sink). That is, the collector terminal 24 is a collector terminal for a heat sink, and cools the chip 1 from its back surface. Therefore, in the case of the present embodiment, the chip 1 is configured to be cooled (heat radiated) from both surfaces thereof via the emitter terminal 21 and the collector terminal 24.

The chip 1 has a built-in temperature sensor and current sensor (both not shown), and a plurality of control pads (not shown) connected thereto are provided on the surface of the chip 1. Have been. Each of the above-mentioned control pads is for establishing electrical conduction with the outside of the chip 1. In the case of the present embodiment, for example, the control pads 25 to 28 (see FIG. 1) provided outside the chip 1 They are connected by wire bonding. The control terminals 25 to 28
Is an external electrode, which is composed of, for example, a lead frame (a part thereof).

As described above, after external terminals (lead frames) are soldered to the chip 1 and wire-bonded, as shown in FIGS. 5 and 6,
The chip 1 and each external terminal (lead frame) are
Mold with. Thus, one resin-molded IGBT 30 is manufactured. In the case of the IGBT 30, each of the rectangular extending portions 21 b and 24 b of the emitter terminal 21 and the collector terminal 24 is formed of a molded body 31 of resin 29.
6 project upward from the upper end surface in FIG.

The right side of the molded body 31 of the IGBT 30 in FIG.
a is exposed. Similarly, a rectangular portion 24a (see FIG. 5) of the collector terminal 24 is exposed on the left side surface of the molded body 31 of the IGBT 30 in FIG. Note that a chip (not shown) of a freewheel diode is embedded inside the mold body 31 of the IGBT 30. The anode pad (electrode) of the free wheel diode chip is soldered, for example, to the emitter terminal 21 and the cathode pad (electrode) is soldered, for example, to the collector terminal 24.

In this embodiment, as shown in FIGS. 7 and 8, a 6-in-1 type IGBT module 32 was manufactured by using six IGBTs 30 described above. The IG
An example in which a 6-in-1 type IGBT module (this is an IGBT module having substantially the same configuration as the IGBT module 32 of the present embodiment) using six IGBTs having substantially the same configuration as that of the BT 30 is used. The present applicant has previously filed an application (Japanese Patent Application No. 11-134809).
issue). Therefore, here, the IGBT module 32
Will be described briefly, and detailed description will be omitted.

As shown in FIG. 7 and FIG.
The module 32 includes a cooling block 33 and an IGBT 3 housed in an element housing portion 33 a of the cooling block 33.
0 and radiating blocks 34 and 35 that press the IGBT 30 against the cooling block 33. 7 and 8, only two IGBTs 30 are shown, and illustration of the remaining four IGBTs 30 is omitted. The structure in which these remaining four IGBTs 30 are attached to the cooling block 33 is the same as the two I
The configuration is the same as that of attaching the GBT 30 to the cooling block 33.

In the case of the above configuration, each IGBT 30 is sandwiched between two insulating substrates 36 and 37. These insulating substrates 36 and 37 are high thermal conductive substrates and are made of, for example, aluminum nitride or the like. In this case, the two insulating substrates 36 and 37 are, for example, fused or soldered to the emitter terminal 21 and the collector terminal 24 of the IGBT 30. Although not shown, the gate terminal 22 of the IGBT 30 is, for example, fused or soldered to one of the insulating substrates 36 and 37, and is configured to be connectable to an external terminal.

The IGBT 30 sandwiched between the insulating substrates 36 and 37 is
a is held so as to be in contact with the inner surface of the element a, further pressed by the heat radiation blocks 34 and 35, and pressed against the inner surface of the element housing portion 33a. In this case, the heat-dissipating block 35 is configured to be fixed to the cooling block 33 by screws 38 so as to maintain the above-mentioned press-contact state.

The heat radiating blocks 34 and 35 are made of a material having good heat conductivity such as aluminum. The cross-sectional shape of the heat radiation block 34 is a shape having a hypotenuse portion 34a in a part of a rectangle. The cross-sectional shape of the heat dissipation block 35 is substantially trapezoidal, and has oblique sides 35a, 35a. The heat dissipation block 35 has a through hole through which the screw 38 is inserted.

In this configuration, when the heat dissipating block 35 is moved downward in FIG. 8 by tightening the screw 38, the oblique side 35a of the heat dissipating block 35 hits the oblique side 34a of the two heat dissipating blocks 34 and is pressed. , 2
The heat radiation blocks 34 are pushed in the left-right direction in FIG. Thereby, the two IGBTs 30 are configured to be pressed against the inner surface of the element housing portion 33a of the cooling block 33 to be pressed.

The cooling block 33 is formed of a material having good heat conductivity such as aluminum. The cooling block 33 is provided with three element accommodating portions 33a accommodating two IGBTs 30, and a total of six IGBTs 30 are provided.
The BT 30 can be accommodated and fixed. As shown in FIG. 8, a coolant flow path 39 for flowing a coolant W such as water is formed inside the cooling block 33. In this case, the coolant W is externally supplied to the coolant channel 3.
9 and the refrigerant W flowing through the refrigerant flow path 39
Is configured to be able to be taken out.
Thereby, the cooling block 33 and thus the IGBT 30 can be sufficiently cooled.

Next, the steps of manufacturing the chip 1 of the IGBT 30 having the above configuration will be briefly described. First, a step of forming devices is performed by executing a known semiconductor wafer process on the wafer. By performing this step, a large number of IGBT chips 1 having the configuration shown in FIGS. 2 to 4 are formed on the wafer.

After performing the device forming step, a step of inspecting each chip 1 on the wafer is executed. In this case, first, a known test element group wafer acceptance test (TEGWAT) is executed. Subsequently, a well-known wafer acceptance test (WAT) is executed. Then, at the time of executing the WAT, each chip 1 is configured to judge whether each of the plurality of cell blocks 12 is good or bad. The quality of each cell block 12 is determined using a well-known inspection device that measures the breakdown voltage between the gate and the emitter.

More specifically, since the emitter pad 17 and the gate pad 18 corresponding to each cell block 12 are formed on the IGBT chip 1, the inspection needle of the above-described inspection apparatus is used for the emitter of the first cell block 12a. Pad 1
The breakdown voltage between the gate electrode 8 and the emitter electrode 10 is measured while standing (connected) to the gate pad 7a and the gate pad 18a. At this time, if the withstand voltage is, for example, 20 V or more, the cell block 12a is determined to be a non-defective product; otherwise (if the withstand voltage is less than 20V), the cell block 12a is determined to be a defective product. It has become. Subsequently, the withstand voltage between the gate electrode 8 and the emitter electrode 10 is similarly measured in the same manner for the second and subsequent cell blocks 12b.

Then, with respect to all the cell blocks 12, the breakdown voltage between the gate electrode 8 and the emitter electrode 10 is measured, and when the pass / fail judgment is completed, the pass / fail judgment data is stored. Similarly, the quality of each cell block 12 is determined, and the determination data of the quality is stored. Hereinafter, the pass / fail judgment of each cell block 12 is similarly performed for all the chips 1 on the wafer, and the pass / fail judgment data is stored.

After the WAT is performed, a dicing step for cutting the wafer is performed. Thereafter, a step of connecting the cut chip 1 to an external electrode (such as a lead frame) is performed.

In this case, first, the emitter terminal 21 for the heat sink is soldered to the emitter pad 17 of the chip 1 and the collector terminal 24 for the heat sink is soldered to the collector electrode 11 of the chip 1. Thereafter, based on the result of the quality inspection described above, the non-defective cell block 1
Gate pad 18 connected to the second gate electrode 8
(18a, 18c to 18f) are connected to the gate terminals 22 of the lead frame outside the chip 1 by wire bonding. At the same time, the gate pad 18 (18b) connected to the gate electrode 8 of the defective cell block 12 is replaced with the chip 1 based on the result of the above-mentioned inspection.
The pad 19a having the upper emitter potential is connected by wire bonding.

After the completion of the soldering and the wire bonding, as shown in FIGS.
Then, a step of molding each external terminal (lead frame) with the resin 29 is performed. Thereby, the IGBT 30 molded with the resin 29 is manufactured.

Next, in this embodiment, as shown in FIGS. 7 and 8, a 6-in-1 type IGBT module 32 is manufactured by using the six IGBTs 30 described above. First, each IG
The BT 30 is sandwiched between two insulating substrates 36 and 37. In this case, two insulating substrates 36 and 37 are attached to both surfaces of the IGBT 30 by fusion or soldering. Subsequently, the IGBT 30 sandwiched between the insulating substrates 36 and 37 is housed so as to be in contact with the inner surface of the element housing portion 33 a of the cooling block 33, and further pressed down by the heat radiation blocks 34 and 35. In this case, the heat dissipating block 35 is
Is fastened to the cooling block 33 to secure I
The GBT 30 is pressed against the inner surface of the element housing portion 33a of the cooling block 33, and the pressed state is maintained. This allows
The assembly of the IGBT module 32 is completed.

According to this embodiment having such a structure, a plurality of cell blocks 12 are provided on the surface of one IGBT chip 1 (semiconductor substrate), and a plurality of gate electrodes 8 independent of each other are provided on the cell blocks 12. And a plurality of bonding gate pads 18 connected to the respective gate electrodes 8 are provided on the IGBT chip 1. Thus, by using the plurality of gate pads 18, it is possible to easily determine the quality of each of the plurality of cell blocks 12 using a known inspection device.

In the above configuration, only the gate pad 18 of the non-defective cell block 12 can be connected to the external gate terminal 22. For this reason, even when there are defective cells in the plurality of cell blocks 12, an IGBT (insulated gate power IC) can be constituted only by the non-defective cell blocks 12, and the IGBT operates normally. . As a result, even if the chip size of the IGBT is increased, it is possible to prevent the non-defective product rate from decreasing.

In addition, in the case of the above configuration, since it is not necessary to adopt a multi-layer wiring configuration, the number of steps of the semiconductor wafer process can be the same as that of a normal IGBT. I mean,
The reason that the gate pad 18 is provided for each cell block 12 is that it can be easily realized by changing the pattern design of the photomask. Therefore, even when the chip size of the IGBT is increased, it is possible to prevent the non-defective product rate from being lowered (that is, to increase the yield), and to achieve the same structure as that disclosed in Japanese Patent Application Laid-Open No. 8-191145. In contrast, the semiconductor wafer process can be prevented from becoming complicated.

In the above embodiment, since a plurality of pads 19 having an emitter potential are provided on the surface of the chip 1 so as to be adjacent to the gate pad 18, the gate connected to the gate electrode 8 of the defective cell block 12 is provided. The pad 18 can be connected to the pad 19 having an emitter potential by wire bonding. This eliminates the need to provide the ground terminal on the lead frame, thereby simplifying the processing of the lead frame and lowering the manufacturing cost accordingly. In addition, it is possible to prevent the package size from increasing, and to prevent the bonding wire from contacting another bonding wire.

Furthermore, in the above embodiment, since the pad 19 having the emitter potential is arranged adjacent to the gate pad 18, the gate pad 18 of the defective cell block 12 is wire-bonded to the pad 19 having the emitter potential. With this configuration, the emitter terminal 21 for the heat sink can be soldered to the surface of the chip 1. Therefore, the chip 1 of the IGBT 30 of this embodiment is
The present invention can also be applied to a device having a structure that cools from the surface of the chip.

In the above embodiment, the emitter terminal 21 for the heat sink is soldered to the emitter pad 17 on the front surface of the chip 1, and the collector terminal 24 for the heat sink is soldered to the collector electrode 11 on the back surface of the chip 1. With this configuration, it is possible to smoothly cool both surfaces of the chip 1 via the emitter terminal 21 and the collector terminal 24 for the heat sink.

FIG. 9 shows a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals. In the second embodiment, when connecting the pad 19 having an emitter potential to the emitter pad 17, the pads 19a to 19a having a plurality of emitter potentials are connected.
9 are connected to each other by a wiring 40, and the pad 19a at the left end in FIG. 9 among the pads 19a to 19c having the plurality of emitter potentials is connected to the emitter pad 17a at the left end by the wiring 41.

The configuration of the second embodiment other than that described above is the same as the configuration of the first embodiment. Therefore, in the second embodiment, substantially the same operation and effect as in the first embodiment can be obtained.

FIG. 10 shows a third embodiment of the present invention. In the third embodiment, a gate pad 1 connected to a gate electrode of a cell block 12 having a uniform threshold voltage Vth among a plurality of cell blocks 12
8 is connected to an external gate terminal 22, and a gate pad 18 connected to a gate electrode of the cell block 12 having an irregular threshold voltage Vth is connected to a pad 19 having an emitter potential.

Specifically, after the semiconductor wafer process of the IGBT chip 1 is completed, in the step of electrically testing each chip 1 on the wafer, a threshold for each of the plurality of cell blocks 12 in each chip 1 is set. All the value voltages Vth are measured. Note that the configuration of the chip 1 in a state where the semiconductor wafer process is completed may be the same as the configuration of the chip 1 of the first embodiment or the second embodiment.

When measuring the threshold voltage Vth of each cell block 12, for example, when measuring the threshold voltage Vth of the leftmost cell block 12a in FIG. 9, the gate pads 18b to 18f are connected to the emitter potential Vth. , And a gate bias is applied only to the gate pad 18a for measurement. Hereinafter, similarly, each cell block 12
What is necessary is just to measure each threshold voltage Vth.

Here, for example, it is assumed that the threshold voltage Vth of the cell block 12b is lower than the others, that is, the threshold voltage Vt is locally stored in the cell block 12b.
It is assumed that a cell region having a low h exists. Then, the threshold voltages Vt of the cell blocks 12 other than the cell block 12b are
The measurement result of h is as shown in FIG. 10A, and the measurement result of the threshold voltage Vth of the cell block 12b is as shown in FIG. 10B.

In FIGS. 10A and 10B, the horizontal axis is the gate bias (voltage) Vg, and the vertical axis is the logarithmic value of the collector current Ic. In this case, it can be seen that the threshold voltage Vth of FIG. 10B is lower than that of FIG.

Now, assuming that all (six) cell blocks 12 in the chip 1 (including the cell block 12b having a low threshold voltage Vth) are operated, the current becomes large when switching a large current. Since the threshold voltage Vth concentrates on the cell block 12b having a low threshold voltage, the breakdown strength of the chip 1 is reduced.

Therefore, in the third embodiment, the cell block 12b having a low threshold voltage Vth is connected so as not to operate. That is, the gate pad 18 (18a, 18c to 18f) connected to the gate electrode 8 of the cell block 12 having the uniform threshold voltage Vth is connected to the gate terminal 22 of the lead frame outside the chip 1 by, for example, wire bonding. Connecting. At the same time, the cell block 12 having a low (uneven) threshold voltage Vth.
a gate pad 18 connected to the gate electrode 8 of FIG.
(18b) is connected to a pad 19a having an emitter potential on the chip 1 by, for example, wire bonding.

With such a connection, the threshold voltage Vt
The cell block 12b with a low h stops operating, and the cell region with a locally low threshold voltage Vth in this cell block 12b is kept off. Therefore, at the time of switching of a large current, the current does not concentrate on the cell block 12b having the low threshold voltage Vth, and it is possible to prevent the breakdown strength of the chip 1 from being reduced.

The configuration of the third embodiment other than the above is the same as the configuration of the first embodiment or the second embodiment. Therefore, also in the third embodiment, the first embodiment
It is possible to obtain substantially the same operation and effect as the embodiment or the second embodiment.

Further, the third embodiment may be combined with the first embodiment or the second embodiment. That is, of the plurality of cell blocks 12, the gate pad 18 connected to the gate electrode of the non-defective cell block 12 and the gate pad 18 connected to the gate electrode of the cell block 12 having the same threshold voltage Vth. Are connected to the external gate terminal 22 and the gate pad 1 connected to the gate electrode of the defective cell block 12.
8 and a gate pad 18 connected to the gate electrode of the cell block 12 having an irregular threshold voltage Vth may be connected to a pad 19 having an emitter potential.

In each of the above embodiments, pads 19a to 19c having an emitter potential are provided on the surface of the chip 1 so as to be located alternately between the gate pads 18a to 18f. However, it is not necessary to dispose them between each of the gate pads 18a to 18f,
It may be configured to be disposed at an appropriate portion around each of the gate pads 18a to 18f. In addition, the size and shape of the pad 19 having the emitter potential can be appropriately changed.

In each of the above embodiments, the emitter terminal 21 for the heat sink is soldered to the emitter pad 17 of the chip 1. Alternatively, the emitter pad 17 may be replaced by an emitter terminal formed of a normal lead frame. May be configured to perform wire bonding.

FIGS. 11 to 16 show a fourth embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals. In the fourth embodiment, as shown in FIG. 13, similar to the first embodiment,
A plurality of gate pads 51 (51a, 51b, 51c,...) Are provided on one side of the surface of the IGBT chip 1, but no emitter pad is provided between the gate pads 51. In this case, the plurality of gate pads 51 (51a, 51b, 51c,...) Constitute a first gate pad of the present invention.

A plurality of emitter pads 17 (17a, 17b, 17c,...) Provided on the surface of the chip 1 are provided.
..), A substantially rectangular notch 52 is formed at the end on the first gate pad 51 side, as shown in FIG.
The notch 52 has no conductor (metal such as aluminum) pattern forming the emitter pad 17. In this case, the notch 52 is configured to be arranged in the area where the emitter pad 17 is provided. The notch 52 includes a rectangular portion 52a and a communicating portion 52b that communicates between the inside of the rectangular portion 52a and the outside of the emitter pad 17.

Then, a rectangular second gate pad 53 is provided inside each of the plurality of rectangular portions 52a. Thereby, the plurality of second gate pads 53
Are provided in a region where the emitter pad 17 is provided. In the case of this configuration, the second gate pad 53
The space between the gate and the emitter pad 17 is insulated. The plurality of second gate pads 53 are connected to the plurality of first gate pads 51 and the connection lines (conductor patterns) 54, respectively.
Connected through. The connection line 54 is provided in the notch 5
It is arranged to pass through the inside of the two communicating portions 52b. Thus, the plurality of second gate pads 53 are connected to the plurality of gate electrodes 8 via the connection lines 54 and the first gate pads 51, respectively. The surface of the chip 1 is covered with a passivation film except for the surface portions of the pads 17, 51, and 53.

Further, the plurality of second gate pads 53
Are each covered with an insulating layer 55 as shown in FIG. FIG. 13 shows an IGBT chip 1 in which the semiconductor wafer process has been performed up to the state where each second gate pad 53 is covered with the insulating film 55 in this manner.

In the fourth embodiment, the chip 1 in the state shown in FIG. 13 is inspected, and the quality of the plurality of cell blocks 12 is determined. When the defective cell block 12 exists, the defective cell block 1
The insulating layer 55 covering the second gate pad 53 connected to the second gate electrode is peeled off by a method such as laser trimming. FIG. 14 shows a case where the fourth cell block 12 from the left is defective, for example.
2 shows a state in which the insulating layer 55 covering the second gate pad 53 corresponding to FIG. In FIG. 14, the hatched area shows the second gate pad 53 from which the insulating layer 55 has been removed.

Thereafter, a step of connecting the chip 1 to an external electrode (such as a lead frame) is performed. in this case,
As shown in FIGS. 15 and 16, first, a heat sink 56 serving as a heat sink and an electrode is soldered to the emitter pad 17 of the chip 1. By the soldering of the heat sink 56, the second gate pad 53 connected to the gate electrode 8 of the defective cell block 12 is connected (short-circuited) to the emitter pad 17. The second gate pad 53 connected to the gate electrode 8 of the non-defective cell block 12 and the heat sink 56
Are insulated by an insulating layer 55.

Then, as shown in FIG. 16, an emitter terminal 57 for both a heat sink and an electrode is soldered to the heat sink 56. At the same time, a collector terminal 24 for both a heat sink and an electrode is soldered to the collector electrode 11 of the chip 1. Thereafter, as shown in FIG. 16, the first gate pad 51 connected to the gate electrode 8 of the non-defective cell block 12 is connected to the gate terminal 22 of the lead frame outside the chip 1 by wire bonding.

Subsequently, after the soldering and the wire bonding are completed, as shown in FIG. 16, the chip 1 and each external terminal (heat sink and lead frame) are
Step 9 of molding is performed. Thereby, the resin 2
9, the IGBT 30 molded is manufactured.

The configuration of the fourth embodiment other than the above is almost the same as the configuration of the first embodiment.
Therefore, in the fourth embodiment, substantially the same operation and effect as in the first embodiment can be obtained.

In particular, in the fourth embodiment, the chip 1
A plurality of first gate pads 51 and a plurality of second gate pads 53 in a region where the emitter pad 17 is provided, and a second gate pad of a non-defective cell block 12 of the plurality of cell blocks 12 is provided. The pad 53 was configured to be covered with the insulating layer 55. That is, the second gate pad 53 connected to the gate electrode of the defective cell block 12
The insulating layer 55 covering the substrate is peeled off.

According to this structure, when the heat sink 56 serving as a heat sink and an electrode is soldered to the emitter pad 17 of the chip 1, the second gate pad connected to the gate electrode 8 of the defective cell block 12 is formed. 53 is connected (short-circuited) to the emitter pad 17. Therefore, the operation of wire bonding the gate pad corresponding to the defective cell block 12 to the pad or the terminal of the source potential may be unnecessary.

In the fourth embodiment, the area where the plurality of second gate pads 53 are provided, that is, the area where the emitter pad 17 is provided, means that the heat sink 56 serving as a heat sink and an electrode is soldered to the emitter pad 17. When attached, the second gate pad 53 and the emitter pad 1 are
7 is a region that includes all positions where 7 can be short-circuited (connected).

In the fourth embodiment, after all the second gate pads 53 are covered with the insulating layer 55, the insulating layer covering the second gate pad 53 corresponding to the defective cell block 12 is formed. Although it was configured to peel off 55,
Instead, before the second gate pad 53 is covered with the insulating layer 55, the quality of the cell block 12 is determined, and the second gate pad 53 corresponding to the defective cell block 12 is determined.
May be configured to be covered only by the insulating layer 55. Note that it is preferable to use a solder resist or the like as the insulating layer 55.

In the fourth embodiment, a plurality of second
Although the gate pad 53 is configured to be provided in the cutout portion 52 of the emitter pad 17, the present invention is not limited to this. For example, the second gate pad is stacked on the upper surface of the emitter pad 17 via an insulating layer. You may. With such a configuration, substantially the same operation and effect can be obtained.

Further, in the fourth embodiment, the second gate pad 53 is connected to the gate electrode 8 by connecting the second gate pad 53 and the first gate pad 51 via the connection line 54. Instead of this, the second gate pad 53 may be connected to the gate electrode 8 without the first gate pad 51 interposed therebetween.

In each of the above embodiments, the IGBT 30 is
Although the 6-in-1 type IGBT module 32 is manufactured by using the IGBT module, the present invention is not limited to this, and a 2-in-1 type IGBT module, a 7-in-1 type IGBT module, an IGBT discrete package, or the like may be manufactured.

Furthermore, in each of the above embodiments, the plurality of gate pads 18 and 51 are arranged along one side of the surface of the chip 1 of the IGBT. However, the present invention is not limited to this. The arrangement position of the pad 18
What is necessary is just to design so that it may correspond to the connection form which connects the gate pad 18 to the external gate terminal 22. Further, in each of the above-described embodiments, an example in which the present invention is applied to an n-channel type IGBT is described.

In each of the above embodiments, the present invention is applied to an IGBT. However, the present invention is not limited to this.
The present invention may be applied to an insulated gate power IC having a gate electrode for current control on the surface of a semiconductor substrate, for example, a MOSFET or MOS type field effect element.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention, in which an IG
FIG. 2 is a plan view showing a state in which a BT chip and a gate terminal of a lead frame are wire-bonded.

FIG. 2 is a partial plan view of an IGBT chip;

FIG. 3 is a schematic longitudinal sectional view of an IGBT chip.

FIG. 4 is a schematic longitudinal sectional view of a boundary portion of a cell block of an IGBT chip.

FIG. 5 is a cross-sectional view of a state in which the IGBT chip is resin-molded.

FIG. 6 is a perspective view showing a state in which the IGBT chip is resin-molded.

FIG. 7 is a partial perspective view of the IGBT module.

FIG. 8 is a partial longitudinal sectional view of the IGBT module.

FIG. 9 is a view corresponding to FIG. 1, showing a second embodiment of the present invention.

FIG. 10 shows a third embodiment of the present invention, and is a diagram showing a relationship between a gate bias Vg of a cell block and a collector current Ic.

FIG. 11 is a partially enlarged plan view of an IGBT chip showing a fourth embodiment of the present invention.

FIG. 12 is a partially enlarged plan view of an IGBT chip;

FIG. 13 is a plan view of an IGBT chip.

FIG. 14 is a plan view of an IGBT chip.

FIG. 15 is a plan view showing a state in which a heat sink is soldered to an IGBT chip;

FIG. 16 is a diagram corresponding to FIG. 5;

FIG. 17 is a diagram corresponding to FIG. 1 showing a conventional configuration.

FIG. 18 is a diagram corresponding to FIG. 1 showing a different conventional configuration.

[Explanation of symbols]

1 is a chip, 2 is a p + substrate (semiconductor substrate), 6 is a trench, 7 is a gate insulating film, 8 is a gate electrode, 9 is an n + emitter layer, 10 is an emitter electrode, 11 is a collector electrode,
2 is a cell block, 13 is an oxide film, 14 is an interlayer insulating film,
17 is an emitter pad, 18 is a gate pad, 19 is a pad having an emitter potential, 20 is a wiring, 21 is an emitter terminal, 22 is a gate terminal, 23 is a bonding wire, 24 is a collector terminal, 25, 26, 27 and 28 are Control terminal, 29 is a resin, 30 is an IGBT, 31 is a molded body, 32 is an IGBT module, 33 is a cooling block,
34 is a heat dissipation block, 35 is a heat dissipation block, 36, 37
Is an insulating substrate, 51 is a first gate pad, 52 is a notch,
53 is a second gate pad, 54 is a connection line, 55 is an insulating layer, 56 is a heat sink, and 57 is an emitter terminal.

Continuing on the front page (72) Inventor Amonari Suzuki 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture, Japan Denso Co., Ltd. ) Inventor Akihisa Iseno 1-1-1, Showa-cho, Kariya-shi, Aichi, Japan Denso Corporation (72) Inventor Yoshimi Nakase 1-1-1, Showa-cho, Kariya-shi, Aichi prefecture, Denso Corporation

Claims (6)

[Claims] A plurality of cell blocks provided on a surface of a semiconductor substrate; a plurality of gate electrodes provided on the plurality of cell blocks, respectively; provided independently of each other; a plurality of gate electrodes provided on the semiconductor substrate; An insulated gate power IC comprising: a plurality of gate pads connected to each other; and a pad provided on the semiconductor substrate so as to be adjacent to the gate pad and having a plurality of emitter potentials. 2. A gate pad connected to a gate electrode of a non-defective cell block of the plurality of cell blocks, connected to an external gate terminal, and a gate pad connected to a gate electrode of a defective cell block. Is connected to a pad having the emitter potential.
C. 3. A gate pad connected to a gate electrode of a cell block having a uniform threshold voltage Vth of the plurality of cell blocks is connected to an external gate terminal, and an irregular threshold voltage Vth is provided. 3. The insulated gate power IC according to claim 1, wherein a gate pad connected to a gate electrode of the cell block having a gate electrode is connected to a pad having the emitter potential. 4. An emitter pad provided on a front surface of the semiconductor substrate and connected to an emitter electrode, a collector electrode provided on a back surface of the semiconductor substrate, and connected to the collector electrode on a back surface of the semiconductor substrate. Collector terminal for a heat sink soldered as described above, an emitter terminal for a heat sink soldered to a surface of the semiconductor substrate so as to be connected to the emitter pad, the semiconductor substrate, the gate terminal, and the collector terminal 4. The insulated gate power IC according to claim 2, further comprising a resin for molding the emitter terminal. 5. An emitter pad provided on a surface of the semiconductor substrate and connected to an emitter electrode, and an external emitter terminal connected to the emitter pad, wherein connection between the gate pad and the gate terminal is established. 3. The connection between the gate pad and the pad having the emitter potential is performed by wire bonding, and the connection between the emitter pad and the emitter terminal is performed by wire bonding. Or the insulated gate power IC according to 3. 6. A plurality of cell blocks provided on a surface of a semiconductor substrate; a plurality of gate electrodes provided in the plurality of cell blocks, respectively; and independent gate electrodes; and a plurality of gate electrodes provided on the semiconductor substrate. A plurality of first gate pads respectively connected to the plurality of gate electrodes; an emitter pad provided on the semiconductor substrate and connected to the emitter electrode; and a plurality of first gate pads provided in a region where the emitter pad is provided, and respectively connected to the plurality of gate electrodes. Gate type, comprising: a plurality of second gate pads; and an insulating layer provided to cover the second gate pad connected to a gate electrode of a non-defective cell block of the plurality of cell blocks. Power I
C.