DE10211831A1 - Power semiconductor components monitoring circuit e.g. for contact failure, has two mutually electrical isolated pads also isolated from power semiconductor element - Google Patents

Power semiconductor components monitoring circuit e.g. for contact failure, has two mutually electrical isolated pads also isolated from power semiconductor element

Info

Publication number
DE10211831A1
DE10211831A1 DE10211831A DE10211831A DE10211831A1 DE 10211831 A1 DE10211831 A1 DE 10211831A1 DE 10211831 A DE10211831 A DE 10211831A DE 10211831 A DE10211831 A DE 10211831A DE 10211831 A1 DE10211831 A1 DE 10211831A1
Authority
DE
Germany
Prior art keywords
power semiconductor
semiconductor component
circuit arrangement
connection
arrangement according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10211831A
Other languages
German (de)
Other versions
DE10211831B4 (en
Inventor
Reinhard Herzer
Jan Lehmann
Mario Netzel
Sascha Pawel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semikron Elektronik GmbH and Co KG
Original Assignee
Semikron GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semikron GmbH and Co KG filed Critical Semikron GmbH and Co KG
Priority to DE10211831A priority Critical patent/DE10211831B4/en
Publication of DE10211831A1 publication Critical patent/DE10211831A1/en
Application granted granted Critical
Publication of DE10211831B4 publication Critical patent/DE10211831B4/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Conversion In General (AREA)

Abstract

A circuit arrangement has a power semiconductor component (1) with at least one drive/control contact point (pad) (11) on its surface facing away from the substrate (17) . This circuit arrangement also has at least two mutually electrically isolated pads (33), also electrically isolated from the power semiconductor element, and the pad (11) is joined to the associated pads (33) of the substrate. An Independent claim is given for a method of monitoring a circuit.

Description

Die Erfindung beschreibt eine Schaltungsanordnung, sowie ein dazugehöriges Verfahren zur Überwachung des Kontakts der Bondverbindungen von Leistungshalbleiterschaltern, insbesondere bei IGBT- und MOSFET-Leistungshalbleiterbauelementen, nach den Merkmalen der Ansprüche 1 bzw. 5. The invention describes a circuit arrangement and an associated method for Monitoring the contact of the bond connections of power semiconductor switches, especially with IGBT and MOSFET power semiconductor components, according to the characteristics of claims 1 and 5, respectively.

Bondverbindungen als elektrisch leitende Verbindungen zwischen Substraten und Leistungshalbleiterbauelementen als dem Stand der Technik bekannt. Sie gewährleisten zusammen mit anderen Verbindungstechniken, z. B. Lötverbindungen, die elektrische Verbindung zwischen einem Leistungshalbleiterbauelement und einem Substrat, z. B. einer nach dem direct-copper-bonding hergestellten, meist beidseits kupferkaschierten Keramik (kurz: DCB-Substrat), innerhalb eines Leistungshalbleitermoduls, bzw. den Anschluss-Pins (kurz leadframe) eines diskreten Gehäuses. Bond connections as electrically conductive connections between substrates and Power semiconductor devices known as the prior art. You ensure along with other joining techniques, e.g. B. solder connections, the electrical Connection between a power semiconductor device and a substrate, for. B. one after the direct-copper-bonding ceramic, mostly copper-clad on both sides (in short: DCB substrate), within a power semiconductor module, or the connection pins (short leadframe) of a discrete housing.

Anhand der Fig. 1 und 2 wird der Stand der Technik eines Leistungshalbleitermoduls dargestellt. In Fig. 1 sind der prinzipielle Aufbau eines Leistungshalbleitermoduls im Querschnitt sowie gängige Verbindungstechniken gezeigt. Dargestellt ist beispielhaft ein Leistungshalbleiterbauelement (1), die diesem zugewandte und strukturierte erste Kupferfläche (2) des DCB-Substrats, die elektrisch isolierende Keramik (3), die einer Grundplatte oder einem Kühlkörper zugewandte zweite Kupferfläche (4) des DCB-Substrats, die Bodenplatte bzw. der Kühlkörper (5), die Lotverbindung (6) zwischen Leistungshalbleiterbauelement (1) und erster Kupferfläche (2), die Zwischenschicht (7) zwischen zweiter Kupferfläche (4) und Grundplatte oder Kühlkörper (5) und eine Drahtbondverbindung (8) zwischen der dem Substrat abgewandten Seite (Vorderseite) des Leistungshalbleiterbauelementes und einer Kupferfläche (2) des Substrats. Hierbei ist die Zwischenschicht (7) entweder eine stoffschlüssige Lotverbindung oder eine stoffbündige, wärmeleitende Schicht. Der Rückseitenkontakt (auf der dem Substrat zugewandten Seite) des Leistungshalbleiterbauelements, beispielhaft der Kollektor im Falle eines IGBTs als Leistungshalbleiterbauelement (1), mit der ersten Kupferfläche (2) kann mittels einer Lötung (6) realisiert werden. Die vorderseitigen Anschlüsse des Leistungshalbleiterbauelements, beispielhaft das Gate und der Emitter eines IGBT, werden mittels Bondverbindungen (8) mit einer oder mehreren zum Teil voneinander isolierten Anschlussgebieten der ersten Kupferfläche (2) des DCB-Substrats verbunden. Der mit Hilfe des Leistungshalbleiterbauelements zu schaltende Strom durchfließt sowohl die großflächige Lotverbindung (6) an der Rückseite des Leistungshalbleiterbauelements, als auch die Drahtbondverbindungen (8) an der Vorderseite des Leistungshalbleiterbauelements. Eine auch nur teilweise Zerstörung einer der beiden Verbindungstechniken führt zwangsläufig zum Verlust der Stromtragfähigkeit oder der Steuerbarkeit des Leistungshalbleiterbauelements und infolge dessen zum Ausfall des Leistungshalbleitermoduls. The prior art of a power semiconductor module is illustrated with the aid of FIGS. 1 and 2. In Fig. 1 the basic structure of a power semiconductor module in cross section and common connection techniques are shown. A power semiconductor component ( 1 ) is shown as an example, the structured and structured first copper surface ( 2 ) of the DCB substrate, the electrically insulating ceramic ( 3 ), the second copper surface ( 4 ) of the DCB substrate facing a base plate or a heat sink Base plate or the heat sink ( 5 ), the solder connection ( 6 ) between the power semiconductor component ( 1 ) and the first copper surface ( 2 ), the intermediate layer ( 7 ) between the second copper surface ( 4 ) and the base plate or heat sink ( 5 ) and a wire bond connection ( 8 ) between the side (front side) of the power semiconductor component facing away from the substrate and a copper surface ( 2 ) of the substrate. The intermediate layer ( 7 ) is either a cohesive solder connection or a flush, heat-conducting layer. The rear side contact (on the side facing the substrate) of the power semiconductor component, for example the collector in the case of an IGBT as a power semiconductor component ( 1 ), with the first copper surface ( 2 ) can be realized by means of soldering ( 6 ). The front connections of the power semiconductor component, for example the gate and the emitter of an IGBT, are connected by means of bond connections ( 8 ) to one or more connection regions of the first copper surface ( 2 ) of the DCB substrate, some of which are insulated from one another. The current to be switched with the aid of the power semiconductor component flows through both the large-area solder connection ( 6 ) on the back of the power semiconductor component and the wire bond connections ( 8 ) on the front of the power semiconductor component. Even a partial destruction of one of the two connection technologies inevitably leads to the loss of the current carrying capacity or the controllability of the power semiconductor component and, as a result, to the failure of the power semiconductor module.

Fig. 2 zeigt beispielhaft eine mögliche Strukturierung eines DCB-Substrats (9) nach dem Stand der Technik mit den erforderlichen Bondverbindungen und einem Leistungshalbleiterbauelement (1). Die Ansteuerung des Leistungshalbleiterbauelements erfolgt über Kontaktflächen auf dessen Oberfläche. Diese werden auch als Bond-Pads bezeichnet. Die Bond-Pads besitzen unterschiedliche Funktionen, zum einen die Funktion als Bezugsknoten für die Ansteuerschaltung, beispielhaft im Falle eines IGBT als Emitter-Pad bezeichnet, zum anderen die Funktion zur Steuerung des Leistungshalbleiters, beispielhaft im Falle eines IGBT als Gate- Pad (11) bezeichnet. Die Verbindungen zu den isolierten Kupferflächen (18) und (33) des DCB- Substrates werden mittels Bondverbindungen (12) realisiert. Die Bonddrähte besitzen dabei ebenfalls unterschiedliche Funktionen. Die zum Führen des Hauptstromes notwendigen Bonddrähte werden als Emitter-Bonddrähte bezeichnet, die zur Ansteuerung notwendigen Bonddrähte als Gate-Bonddraht (12) bzw. als Hilfsemitter-Bonddraht. Fig. 2 shows an example of a possible structure of a DCB substrate (9) according to the prior art with the necessary bonding connections and a power semiconductor component (1). The power semiconductor component is controlled via contact areas on its surface. These are also known as bond pads. The bond pads have different functions, on the one hand the function as a reference node for the control circuit, for example in the case of an IGBT referred to as an emitter pad, and on the other hand the function for controlling the power semiconductor, for example in the case of an IGBT as a gate pad ( 11 ) designated. The connections to the isolated copper surfaces ( 18 ) and ( 33 ) of the DCB substrate are realized by means of bond connections ( 12 ). The bond wires also have different functions. The bonding wires required to conduct the main current are referred to as emitter bonding wires, and the bonding wires required for control are referred to as gate bonding wires ( 12 ) or as auxiliary emitter bonding wires.

Nachteilig am Stand der Technik ist, dass ein Kontaktverlust eines Gate-Bonddrahtes (12) bereits zum Ausfall des Leistungshalbleitermoduls führen kann, da hierdurch die Steuerbarkeit des Leistungshalbleiters verloren geht. Leistungshalbleitermodule können insoweit redundant ausgelegt werden, dass erst der Kontaktausfall eines weiteren zur gleichen Kupferfläche (33) führenden Gate-Bonddrahtes (12) zum Verlust der Steuerbarkeit und somit zum Ausfall des Leistungshalbleitermoduls führen würde. A disadvantage of the prior art is that a loss of contact of a gate bonding wire ( 12 ) can already lead to the failure of the power semiconductor module, since the controllability of the power semiconductor is thereby lost. Power semiconductor modules can be designed redundantly in such a way that only the contact failure of another gate bonding wire ( 12 ) leading to the same copper surface ( 33 ) would lead to loss of controllability and thus to failure of the power semiconductor module.

Die vorliegende Erfindung hat die Aufgabe, eine Schaltungsanordnung sowie ein zugehöriges Verfahren vorzustellen, um den Kontaktausfall, der durch Ablösen eines Gate-Bonddrahtes von einer Kontaktfläche des Halbleiterbauelements und/oder des Substrates entsteht, festzustellen, wobei das Ablösen eines beliebigen Gate-Bonddrahtes zwischen dem Leistungshalbleiterbauelement und einer externen Kontaktfläche des Substrates festgestellt werden soll, und trotz dieses Kontaktausfalls weiterhin die Ansteuerbarkeit das Leistungshalbleiterbauelement zu erhalten. The present invention has the task of a circuit arrangement and an associated To introduce methods to the contact failure caused by peeling a gate bond wire from a contact surface of the semiconductor component and / or the substrate is established, detaching any gate bond wire between the Power semiconductor device and an external contact surface of the substrate determined should be, and despite this loss of contact the controllability continues Get power semiconductor device.

Die Aufgabe wird gelöst durch die Maßnahmen der Ansprüche 1 und 2. Weitere vorteilhafte Ausgestaltungen sind in den Unteransprüchen genannt. Die Erfindung wird beispielhaft an einem Leistungshalbleitermodul beschrieben. The object is achieved by the measures of claims 1 and 2. Further advantageous Refinements are mentioned in the subclaims. The invention is exemplary described a power semiconductor module.

Der grundlegende erfinderische Gedanke basiert auf einer besonderen Ausgestaltung der Schaltungsanordnung, wobei mindestens zwei Gate-Verbindungen pro Leistungshalbleiterbauelement zu mindestens zwei zugehörigen elektrisch voneinander isolierte Kontaktflächen auf dem Substrat angeordnet sind sowie auf einem Verfahren zur Überwachung dieser Schaltungsanordnung. The basic inventive idea is based on a special design of the Circuit arrangement, with at least two gate connections per Power semiconductor component to at least two associated electrically isolated from each other Contact areas are arranged on the substrate and on a method for monitoring this circuit arrangement.

Die erfinderische Ausgestaltung der Schaltungsanordnung besteht aus einem Leistungshalbleiterbauelement, das auf seiner dem Substrat abgewandten Seite mindestens eine Kontaktstelle (Gate-Bondpad) zur seiner Steuerung aufweist. Diese Kontaktstelle ist mittels mindestens zweier Drahtbondverbindungen (Gate-Bonddrähte) mit voneinander elektrisch isolierten, leitenden Flächen des Substrats verbunden. The inventive design of the circuit arrangement consists of a Power semiconductor component, at least on its side facing away from the substrate has a contact point (gate bond pad) for its control. This contact point is by means of at least two wire bond connections (gate bond wires) with each other electrically insulated, conductive surfaces of the substrate connected.

Das erfinderische Verfahren zur Überwachung derartiger Schaltungsanordnungen überwacht jeden dieser Gate-Anschlüsse in den Ansteuerstromkreisen der Ansteuerschaltung, sowie dessen Stromfluss mittels einer erweiterten schaltungstechnischen Funktionalität innerhalb der Ansteuerschaltung. The inventive method for monitoring such circuit arrangements is monitored each of these gate connections in the drive circuits of the drive circuit, and whose current flow by means of an extended circuit functionality within the Drive circuit.

Spezielle Ausgestaltungen der erfinderischen Lösungen werden an Hand der Fig. 3 bis 7 erläutert. Special configurations of the inventive solutions are explained with reference to FIGS. 3 to 7.

Fig. 3 zeigt beispielhaft ein gegenüber dem Stand der Technik verändertes erfinderisches DCB- Substrat. Fig. 3 shows an example of a comparison with the prior art modified inventive DCB substrate.

Fig. 4 zeigt wesentliche Elemente des erfinderischen elektrischen Netzwerkes der Ansteuerstromkreise für den Fall, dass kein Kontaktausfall vorliegt. Fig. 4 shows essential elements of the inventive electrical network of Ansteuerstromkreise for the case that no contact failure.

Fig. 5 zeigt die Veränderung des erfinderischen elektrischen Netzwerkes der Ansteuerstromkreise für den Fall, dass ein Kontaktausfall vorliegt. Fig. 5, the change of the inventive electrical network showing the Ansteuerstromkreise for the case where a contact failure.

Fig. 6 zeigt beispielhaft die Darstellung eines Ausschaltvorganges eines IGBT für den Fall, dass kein Kontaktausfall vorliegt. FIG. 6 shows an example of an IGBT switch-off procedure in the event that there is no contact failure.

Fig. 7 zeigt beispielhaft die Darstellung eines Ausschaltvorganges eines IGBT für den Fall, dass ein Kontaktausfall vorliegt. FIG. 7 shows an example of the switching off of an IGBT in the event that a contact failure occurs.

Fig. 3 zeigt ein gegenüber dem Stand der Technik in der Anzahl und Lage des kupferkaschierten Bereichs verändertes DCB-Substrat (17), wobei der Gate-Anschluss des Leistungshalbleiters (1) zwei separate Bonddrähte (12) aufweist. Entscheidend hierbei ist, dass diese redundant ausgeführten Gate-Bonddrähte keinen gemeinsamen Bondfuß, besitzen. Kommt es, z. B. infolge von Temperaturwechseln am Ende der Lebensdauer, zum Abheben eines Bondfußes eines Gate-Bonddrahtes, so verliert der betroffene Bonddraht seine Funktionalität und kann nicht mehr vom Gatelade- bzw. Gateentlade-Strom durchflossen werden. Damit unterscheidet sich der betroffene Ansteuerstromkreis hinsichtlich seiner Gatelade- bzw. Gateentladecharakteristik von dem Ansteuerstromkreis, dessen Kontakt korrekt angeschlossen ist. Die Steuerbarkeit des Leistungsschalters bleibt allerdings erhalten, da dessen Steuerung über den redundanten Bonddraht erfolgen kann FIG. 3 shows a DCB substrate ( 17 ) which has been changed in the number and position of the copper-clad area compared to the prior art, the gate connection of the power semiconductor ( 1 ) having two separate bonding wires ( 12 ). It is crucial here that these redundant gate bond wires do not have a common bond foot. Does it happen, e.g. B. due to temperature changes at the end of life, for lifting a bond foot of a gate bond wire, the affected bond wire loses its functionality and can no longer be flowed through by the gate charge or gate discharge current. The control circuit concerned thus differs in terms of its gate charging or gate discharge characteristic from the control circuit whose contact is correctly connected. However, the controllability of the circuit breaker is retained, since it can be controlled via the redundant bond wire

Fig. 4 und 5 stellen die elektrischen Netzwerke der Ansteuerstromkreise in einem Vergleich gegenüber, zum einen für den Fall (Fig. 4), dass alle Bondverbindungen vorhanden sind, zum anderen (Fig. 5), dass einer der Bondfüße abgehoben, also die elektrische Verbindung unterbrochen, ist. FIGS. 4 and 5 represent the electrical networks Ansteuerstromkreise in a comparison with respect to, on the one hand for the case (Fig. 4), all bonds are present, on the other hand (Fig. 5), that one of the bonding foot is lifted, so the electrical Connection is broken.

Die im Ansteuerstromkreis wirkenden Elemente sind in der Fig. 4 dargestellt, dazu zählen die Endstufe der Ansteuerschaltung (19), das Leistungshalbleiterbauelement (1) und im Detail die Gate-Vorwiderstände (20), die parasitäre Induktivität (24) des Hilfsemitter-Bonddrahtes, die parasitären Induktivitäten (21) der Emitter-Bonddrähte, die Emitter-Pads (10), die Gate-Pads (11) und die gemeinsame Kupferfläche (18) auf dem DCB-Substrat zum Anschluss der Emitter- Bonddrähte. The elements acting in the control circuit are shown in FIG. 4, including the output stage of the control circuit ( 19 ), the power semiconductor component ( 1 ) and in detail the gate series resistors ( 20 ), the parasitic inductance ( 24 ) of the auxiliary emitter bonding wire, the parasitic inductances ( 21 ) of the emitter bond wires, the emitter pads ( 10 ), the gate pads ( 11 ) and the common copper surface ( 18 ) on the DCB substrate for connecting the emitter bond wires.

Fig. 5 zeigt die Veränderung des elektrischen Netzwerkes im Falle des Abhebens eines Gate- Bonddrahtes. Der betroffene Bonddraht verliert seine direkte Verbindung zum Gate-Pad (11) des Leistungshalbleiterbauelements (1). Der betroffene Bonddraht, sowie der zugehörige Gate- Vorwiderstand (20) werden nicht mehr vom Strom der Ansteuerschaltung durchflossen. Fig. 5 shows the change in the electrical network in the case of lifting a gate bond wire. The bond wire concerned loses its direct connection to the gate pad ( 11 ) of the power semiconductor component ( 1 ). The affected bonding wire and the associated gate series resistor ( 20 ) are no longer flowed through by the current of the drive circuit.

Zur schaltungstechnischen Detektierung des Abhebens eines Gate-Bonddrahtes ist es daher notwendig, die Potentialverläufe an den Messpunkten (22) und (23) zu erfassen und miteinander zu vergleichen. Dabei entspricht der Messpunkt (22) dem elektrischen Knoten zwischen dem Gate-Vorwiderstand (20) und dem Gate-Pad (11) eines korrekt angeschlossenen Bonddrahtes und der Messpunkt (23) dem elektrischen Knoten zwischen dem Gate-Widerstand (20) und dem Gate-Bonddraht eines abgehobenen Gate-Bonddrahtes. Die nachfolgenden Abbildungen zeigen typische Messergebnisse, die die Wirksamkeit des beschriebenen Verfahrens aufzeigen. Beispielhaft wurde ein 25 A/1.2 kV IGBT-Chip mit entsprechender Freilaufdiode bei einer Zwischenkreisspannung von 600 V untersucht. Die Ansteuerschaltung wurde gegenüber Treibern nach dem Stand der Technik in der Art modifiziert, dass der ursprünglich einzelne Gate-Vorwiderstand (20) als eine Parallelschaltung von zwei Gate-Vorwiderständen ausgeführt wurde. Damit kann eine Separierung der einzelnen Ansteuerstromkreise realisiert werden. In order to detect the lifting of a gate bonding wire in terms of circuitry, it is therefore necessary to record and compare the potential curves at the measuring points ( 22 ) and ( 23 ). The measuring point ( 22 ) corresponds to the electrical node between the gate series resistor ( 20 ) and the gate pad ( 11 ) of a correctly connected bonding wire and the measuring point ( 23 ) corresponds to the electrical node between the gate resistor ( 20 ) and the gate -Bond wire of a lifted gate bond wire. The following figures show typical measurement results that demonstrate the effectiveness of the described method. A 25 A / 1.2 kV IGBT chip with a corresponding freewheeling diode at an intermediate circuit voltage of 600 V was examined as an example. The drive circuit was modified compared to prior art drivers in such a way that the originally single gate series resistor ( 20 ) was designed as a parallel connection of two gate series resistors. This enables the individual control circuits to be separated.

Fig. 6 zeigt beispielhaft die zeitliche Darstellung eines Ausschaltvorganges für den genannten IGBT und den Fall, dass beide Gate-Bonddrähte korrekt mit dem Gate-Pad (11) des Leistungshalbleiterbauelements (1) verbunden sind. Der zeitliche Ausschnitt des Ausschaltvorganges wurde so dargestellt, dass der Schaltvorgang des IGBT anhand der Kollektor-Emitter-Spannung (25), des Kollektor-Stromes (26), der Gate-Emitter-Spannung (27) am Messpunkt (22) und der Gate-Emitter-Spannung (28) am Messpunkt (23) sichtbar ist. Für den Fall, dass beide Gate-Bonddrähte (12) korrekt mit dem Gate-Bondpad (11) verbunden sind, ergibt sich kein signifikanter Potentialunterschied an den Messpunkten (22) und (23). Der zeitliche Verlauf der Potentialdifferenz zwischen den Messpunkten (22) und (23) ist als Kurve (29) dargestellt. Fig. 6, the time chart shows an example of an opening operation for said IGBT and the case that both the gate bonding wires are properly connected to the gate pad (11) of the power semiconductor component (1). The time section of the switch-off process was shown in such a way that the switching process of the IGBT was based on the collector-emitter voltage ( 25 ), the collector current ( 26 ), the gate-emitter voltage ( 27 ) at the measuring point ( 22 ) and the gate -Emitter voltage ( 28 ) at the measuring point ( 23 ) is visible. In the event that both gate bond wires ( 12 ) are correctly connected to the gate bond pad ( 11 ), there is no significant potential difference at the measurement points ( 22 ) and ( 23 ). The time course of the potential difference between the measuring points ( 22 ) and ( 23 ) is shown as a curve ( 29 ).

Für den Fall, dass einer der Gate-Bonddrähte (12) keine Verbindung mehr zum Gate-Bond- Pad (11) hat, zeigt Fig. 7 eine zu Fig. 6 vergleichende Messung. Dargestellt wird mit Hilfe von (30) der zeitliche Potentialverlauf am Messpunkt (22), dessen Gate-Bonddraht korrekt mit dem Gate-Pad (11) verbunden ist. Mit Hilfe von Kurve (31) wird der zeitliche Potentialverlauf am Messpunkt (23) dargestellt, hier ist der Gate-Bonddraht vom Gate-Pad (11) abgehoben. Der Potentialunterschied zwischen den Verläufen der Kurven (30) und (31) ist als Kurve (32) dargestellt. Bei der Gegenüberstellung der Ergebnisse aus Fig. 6 und 7 wird eine deutliche Erhöhung der Potentialdifferenz, dargestellt als Kurve (29) bzw. Kurve (32), zwischen den Messpunkten (22) und (23) im Falle des Abhebens eines Bonddrahtes sichtbar. Somit kann die Erhöhung der Potentialdifferenz zwischen den Messpunkten (22) und (23) als Sensorsignal für das Abheben eines Bonddrahtes benutzt werden. In the event that one of the gate bond wires ( 12 ) is no longer connected to the gate bond pad ( 11 ), FIG. 7 shows a measurement that compares to FIG. 6. The time potential curve at the measuring point ( 22 ), whose gate bonding wire is correctly connected to the gate pad ( 11 ), is shown with the aid of ( 30 ). With the help of curve ( 31 ) the temporal potential curve at the measuring point ( 23 ) is shown, here the gate bonding wire is lifted off the gate pad ( 11 ). The potential difference between the curves of curves ( 30 ) and ( 31 ) is shown as curve ( 32 ). When the results from FIGS. 6 and 7 are compared, a clear increase in the potential difference, shown as curve ( 29 ) or curve ( 32 ), between the measuring points ( 22 ) and ( 23 ) becomes apparent when a bond wire is lifted off. The increase in the potential difference between the measuring points ( 22 ) and ( 23 ) can thus be used as a sensor signal for lifting off a bonding wire.

Neben der schaltungstechnischen Auswertung der Potentialverläufe bzw. der Stromverläufe während der Schaltvorgänge, kann ein weiteres Verfahren zur Überwachung der Gate- Bonddrähte eingesetzt werden. Das Verfahren beruht auf der Tatsache, dass im Fall korrekt verbundener Gate-Bonddrähte die Messpunkte (22) und (23) niederohmsch und niederinduktiv über die Bonddrähte verbunden sind. Somit kann mittels zusätzlicher schaltungstechnischer Funktionalität in der Ansteuerstufe die Existenz dieser niederohmschen Verbindung zwischen den Messpunkten (22) und (23) überprüft werden und im Falle des Verlustes dieser niederohmschen Verbindung auf einen abgehobenen Gate-Bonddraht geschlossen werden. In addition to the technical evaluation of the potential curves or the current curves during the switching processes, another method for monitoring the gate bond wires can be used. The method is based on the fact that, in the case of correctly connected gate bonding wires, the measuring points ( 22 ) and ( 23 ) are connected via the bonding wires with low resistance and low inductance. Thus, the existence of this low-resistance connection between the measuring points ( 22 ) and ( 23 ) can be checked by means of additional circuitry functionality in the control stage and, in the event of loss of this low-resistance connection, a conclusion can be drawn about a lifted-off gate bonding wire.

Bestandteil des Verfahrens zur Überwachung der korrekten Verbindung der Gate-Bonddrähte ist im weiteren eine Funktionalität, die im Falle des Abhebens eines Bonddrahtes den Widerstandswert des Gate-Vorwiderstandes korrigiert. Durch die Trennung der Gate- Vorwiderstände in zwei oder mehr separate Ansteuerstromkreise führt das Abheben eines Gate- Bonddrahtes zur Entkopplung des betroffenen Gate-Vorwiderstandes. Der betroffene Gate- Vorwiderstand wird nicht mehr vom Gatelade- bzw. Gateentladestrom durchflossen und verliert somit seine Funktion. Die Folge ist, dass die Gate-Aufladung bzw. Gateentladung des Leistungshalbleiters über einen längeren Zeitraum erfolgen würde. Damit würden die Schaltzeiten und Schaltverluste ansteigen und im Falle der Parallelschaltung mehrerer Leistungshalbleiter wäre eine elektrische Desymmetrierung die Folge. Part of the process for monitoring the correct connection of the gate bonding wires is furthermore a functionality that the in the event of lifting a bond wire Corrected the resistance of the gate series resistor. By separating the gate Series resistors in two or more separate control circuits leads to the lifting of a gate Bond wire for decoupling the affected gate series resistor. The affected gate The series charging or gate discharge current no longer flows through the series resistor and loses it hence its function. The result is that the gate charge or discharge of the Power semiconductor would take place over a longer period. That would make them Switching times and switching losses increase and in the case of parallel connection of several Power semiconductors would result in electrical asymmetry.

Die vorgeschlagene Schaltungsanordnung mit dem dazugehörigen Verfahren bietet gegenüber dem Stand der Technik den Vorteil, mit Hilfe eines zusätzlichen, redundanten Gate- Bonddrahtes und zusätzlichen Auswerteschaltungen innerhalb der Ansteuerschaltung, die Steuerbarkeit des Leistungshalbleiters auch nach dem Verlust des Kontaktes aufrecht zu erhalten und das Abheben von Bonddrähten zu detektieren. Dieses Verfahren kann somit eingesetzt werden, um bevorstehende Ausfälle von Leistungshalbleitermodulen zum Ende der Lebensdauer nachzuweisen und stellt die Grundlage für eine Diagnosefunktion dar. Neben der zusätzlichen Auswerteschaltung müssen innerhalb der Ansteuerschaltung Schaltungskomponenten implementiert werden, die die mittels des beschriebenen Verfahrens gewonnene, zusätzliche Information speichern und das übergeordnete System über die detektierte Vorschädigung informieren. The proposed circuit arrangement with the associated method offers the advantage of the prior art, with the help of an additional, redundant gate Bond wire and additional evaluation circuits within the drive circuit, the Controllability of the power semiconductor upright even after loss of contact obtained and to detect the lifting of bond wires. This method can be used to anticipate upcoming failures of power semiconductor modules at the end of the Verify service life and represents the basis for a diagnostic function. In addition to the additional evaluation circuit must be within the control circuit Circuit components are implemented using the method described additional information obtained and the higher-level system via the Inform detected previous damage.

Claims (10)

1. Schaltungsanordnung bestehend aus einem Substrat (17), mindestens einem darauf angeordneten Leistungshalbleiterbauelement (1), wobei das Leistungshalbleiterbauelement (1) auf seiner dem Substrat (17) abgewandten Seite mindestens eine Kontaktstelle (11) zu seiner Ansteuerung aufweist, sowie diese Schaltungsanordnung mindestens zwei voneinander und von dem Leistungshalbleiterbauelement elektrisch isolierte Kontaktstellen (33) aufweist und die Kontaktstelle (11) des Leistungshalbleiterbauelements mit zugeordneten Kontaktstellen (33) des Substrates verbunden ist. 1. A circuit arrangement comprising a substrate (17), at least one disposed thereon power semiconductor component (1), wherein the power semiconductor component (1) has on its side facing the substrate (17) side facing away from at least one contact point (11) to its activation, and this circuit at least has two contact points ( 33 ) which are electrically insulated from one another and from the power semiconductor component and the contact point ( 11 ) of the power semiconductor component is connected to associated contact points ( 33 ) of the substrate. 2. Schaltungsanordnung nach Anspruch 1 wobei jede Verbindung der Kontaktstelle (11) des Leistungshalbleiterbauelements mit einer der Kontaktstellen (33) des Substrates als Drahtbondverbindung mit mindestens einem Bonddraht (12) ausgebildet ist. 2. Circuit arrangement according to claim 1, wherein each connection of the contact point ( 11 ) of the power semiconductor component with one of the contact points ( 33 ) of the substrate is designed as a wire bond connection with at least one bond wire ( 12 ). 3. Schaltungsanordnung nach Anspruch 2 wobei die Drahtbondverbindungen (12) der Kontaktstelle (11) des Leistungshalbleiterbauelements mit unterschiedlichen Kontaktstellen (33) des Substrates keinen gemeinsamen Bondfuß aufweisen. 3. Circuit arrangement according to claim 2, wherein the wire bond connections ( 12 ) of the contact point ( 11 ) of the power semiconductor component with different contact points ( 33 ) of the substrate do not have a common bond foot. 4. Schaltungsanordnung nach Anspruch 1 wobei die Leistungshalbleiterbauelemente (1) IGBT oder MOSFET Transistoren sind. 4. Circuit arrangement according to claim 1, wherein the power semiconductor components ( 1 ) are IGBT or MOSFET transistors. 5. Verfahren zur Überwachung einer Schaltungsanordnung nach Anspruch 1 wobei jede Verbindung zwischen der Kontaktstelle (11) des Leistungshalbleiterbauelements mit den unterschiedlichen Kontaktstellen (33) zur Ansteuerung des Leistungshalbleiterbauelements (1) in die Ansteuerstromkreise einbezogen wird und der Stromfluss zwischen der Kontaktstelle (11) des Leistungshalbleiterbauelements und den unterschiedlichen Kontaktstellen (33) mittels einer erweiterten schaltungstechnischen Funktionalität innerhalb der Ansteuerschaltung überwacht wird. 5. A method for monitoring a circuit arrangement according to claim 1, wherein each connection between the contact point ( 11 ) of the power semiconductor component with the different contact points ( 33 ) for controlling the power semiconductor component ( 1 ) is included in the control circuits and the current flow between the contact point ( 11 ) Power semiconductor component and the different contact points ( 33 ) is monitored by means of an expanded circuitry functionality within the control circuit. 6. Verfahren zur Überwachung einer Schaltungsanordnung nach Anspruch 5 wobei durch einen paarweisen Vergleich der zeitlichen Strom- und Spannungsverläufe innerhalb der Ansteuerstromkreise auf eine korrekte Funktion der Verbindung zur Ansteuerung geschlossen wird sowie bei abweichenden Verläufen auf einen Fehler, wie den fehlenden Kontakt einer Verbindung, innerhalb der Aufbautechnik geschlossen wird. 6. A method for monitoring a circuit arrangement according to claim 5 wherein by a pairwise comparison of the current and voltage curves within of the control circuits for a correct function of the connection to the control is concluded as well as in the case of deviating courses of an error such as the missing Contact of a connection within which the construction technology is closed. 7. Verfahren zur Überwachung einer Schaltungsanordnung nach Anspruch 5 wobei eine Ansteuerschaltung eingesetzt wird, die das Leistungshalbleiterbauelement mit verschiedenen Ansteuerstromkreisen ansteuert und zeitliche Strom- und Spannungsverläufe innerhalb der Ansteuerstromkreise überwacht. 7. A method for monitoring a circuit arrangement according to claim 5 wherein a control circuit is used which the power semiconductor component with controls different control circuits and current and voltage curves monitored within the control circuits. 8. Verfahren zur Überwachung einer Schaltungsanordnung nach Anspruch 5 wobei eine Ansteuerschaltung eingesetzt wird, die das Leistungshalbleiterbauelement mit verschiedenen Ansteuerstromkreisen ansteuert und die im Fall einer korrekten Verbindung vorhandene niederohmsche Verbindung der zur Ansteuerung benutzten Drahtbondverbindungen über das Gate-Pad des Leistungshalbleiterbauelements überwacht. 8. A method for monitoring a circuit arrangement according to claim 5 wherein a control circuit is used which the power semiconductor component with controls different control circuits and in the case of a correct connection existing low-ohmic connection of those used for control Wire bond connections via the gate pad of the power semiconductor component supervised. 9. Verfahren zur Überwachung einer Schaltungsanordnung nach Anspruch 5 wobei eine Ansteuerschaltung eingesetzt wird, die im Falle des Verlustes einer zur Ansteuerung des Leistungshalbleiters benötigten Verbindung den Gate-Vorwiderstand anpasst, um die Schaltzeiten und -verluste gegenüber dem fehlerfreien Betriebsfall konstant zu halten. 9. A method for monitoring a circuit arrangement according to claim 5 wherein a control circuit is used in the event of the loss of a control of the power semiconductor required adapts the gate series resistor to the To keep switching times and losses constant compared to fault-free operation. 10. Verfahren zur Überwachung einer Schaltungsanordnung nach Anspruch 5 wobei die Ansteuerschaltung auf der Grundlage unterschiedlicher Strom- und Spannungsverläufe in den Ansteuerstromkreisen oder auf der Grundlage des Verlustes der niederohmschen Verbindung zwischen den zur Ansteuerung benutzten Verbindungen auf einen Fehler in der Verbindungstechnik schließen kann und eine Warnung an das übergeordnete System abgibt. 10. A method for monitoring a circuit arrangement according to claim 5 wherein the control circuit based on different current and voltage profiles in the control circuits or based on the loss of the low-resistance Connection between the connections used for control for an error in the Connection technology can close and a warning to the higher-level system emits.
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