CN109994445A - Semiconductor element and semiconductor device - Google Patents
Semiconductor element and semiconductor device Download PDFInfo
- Publication number
- CN109994445A CN109994445A CN201711470436.7A CN201711470436A CN109994445A CN 109994445 A CN109994445 A CN 109994445A CN 201711470436 A CN201711470436 A CN 201711470436A CN 109994445 A CN109994445 A CN 109994445A
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- semiconductor element
- semiconductor
- gate pads
- semiconductor device
- pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
The embodiment of the present application provides a kind of semiconductor element and semiconductor device, the surface of the semiconductor element is in quadrangle, the semiconductor element has the gate pads for receiving control signal, wherein, the quantity of gate pads is at least two, wherein, at least two gate pads are separately positioned on the both ends on one side of the quadrangle.According to the application, when manufacturing semiconductor device, do not need to prepare the different semiconductor element in gate pads position, to reduce the complexity of manufacture semiconductor device.
Description
Technical field
This application involves technical field of semiconductors more particularly to a kind of semiconductor elements and semiconductor device.
Background technique
In semiconductor technology, semiconductor device can have multiple semiconductor elements, and the surface of semiconductor element is usual
It is provided with electrode pad (pad), electrode pad can be connect with the electrode of semiconductor element, also, can be welded on electrode pad
Lead is connect, so that the electrode of the semiconductor element is electrically connected with other electron component.
Patent document 1 (Japanese Unexamined Patent Publication 2008-252115) discloses a kind of semiconductor device.Fig. 1 is 1 disclosure of patent document
Semiconductor device a schematic diagram, as shown in Figure 1, semiconductor device 50 have control element 40 and be located at control element 40
The semiconductor element 2 and semiconductor element 4 of the left and right sides.The surface of semiconductor element 2 and semiconductor element 4 all has emitter
Pad E, gate pads G and diode pad 24, also, gate pads G is connected to control element 40 by lead.
As shown in Figure 1, gate pads G is formed in the close control element 40 of semiconductor element 2 in semiconductor element 2
Side, and be located at the upper position in middle part of semiconductor element 2；In semiconductor element 4, gate pads G is formed in
The side of the close control element 40 of semiconductor element 4, and the position upper positioned at the middle part of semiconductor element 4.
It should be noted that the above description of the technical background be intended merely to it is convenient to the technical solution of the application carry out it is clear,
Complete explanation, and facilitate the understanding of those skilled in the art and illustrate.Cannot merely because these schemes the application's
Background technology part is expounded and thinks that above-mentioned technical proposal is known to those skilled in the art.
Summary of the invention
The inventors of the present application found that in patent document 1, semiconductor element 2 and semiconductor element 4 are located at control
In the case where the left and right sides of element 40, for the ease of the gate pads of the gate pads G of semiconductor element 2, semiconductor element 4
G is connect with control element 40, and the gate pads G of semiconductor element 2 needs to be arranged in right side, the gate pads G of semiconductor element 4
It needs to be arranged in left side, therefore, when manufacturing semiconductor device 50, no matter whether the electrology characteristic of semiconductor element is identical, all
Need to prepare two kinds of different semiconductor elements of gate pads position, to increase the complexity of manufacture semiconductor device.
The application provides a kind of semiconductor element and semiconductor device, and the surface of the semiconductor element is in quadrangle, at least
Two gate pads are separately positioned on the both ends on one side of quadrangle, as a result, in the position of semiconductor element and control element
When the relationship of setting changes, gate pads can be made to be advantageously connected to control element, so, in manufacture semiconductor device
When, it does not need to prepare the different semiconductor element in gate pads position, to reduce the complexity of manufacture semiconductor device.
According to the embodiment of the present application in a first aspect, providing a kind of semiconductor element, have for receiving control signal
Gate pads, the surface of the semiconductor element is in quadrangle, and the quantity of the gate pads is at least two, wherein extremely
Few two gate pads are separately positioned on the both ends on one side of the quadrangle.
According to the second aspect of the embodiment of the present application, wherein the semiconductor element also has a diode pad, and described two
Pole pipe pad is arranged on the another side opposite with described one side of the quadrangle.
According to the third aspect of the embodiment of the present application, wherein the diode pad is than the electricity that the gate pads are born
Pressure is high.
According to the fourth aspect of the embodiment of the present application, wherein the semiconductor element also has emitter pad, the hair
Emitter-base bandgap grading pad is between the diode pad and the gate pads, also, on the direction for being parallel to described one side, institute
Emitter pad is stated between described two gate pads.
According to the 5th of the embodiment of the present application the aspect, a kind of semiconductor device is provided, the semiconductor device has as above
State first aspect semiconductor element described in either side into fourth aspect.
According to the 6th of the embodiment of the present application the aspect, wherein the semiconductor device has along perpendicular to described one side
The semiconductor element described above of 2 of direction arrangement, at least one semiconductor element are directed toward from the diode pad
The gate pads are directed toward from the diode pad different from other semiconductor elements in the direction of the gate pads
Direction.
According to the 7th of the embodiment of the present application the aspect, wherein the semiconductor device also has the control for generating control signal
Element processed, the control element are connected to the gate pads of the semiconductor element by lead.
According to the eighth aspect of the embodiment of the present application, wherein the control element is located at described 2 semiconductors described above
The side along an edge direction of element.
According to the 9th of the embodiment of the present application the aspect, wherein the control element is located at along the side perpendicular to described one side
To between 2 semiconductor elements of arrangement.
According to the tenth of the embodiment of the present application the aspect, wherein the semiconductor device also has lead frame, described partly to lead
Volume elements part and the control element are placed in the lead frame.
The beneficial effects of the present application are as follows: when manufacturing semiconductor device, it is different not need preparation gate pads position
Semiconductor element, to reduce the complexity of manufacture semiconductor device.
Referring to following description and accompanying drawings, specific implementations of the present application are disclosed in detail, specify the original of the application
Reason can be in a manner of adopted.It should be understood that presently filed embodiment is not so limited in range.In appended power
In the range of the spirit and terms that benefit requires, presently filed embodiment includes many changes, modifications and is equal.
Detailed description of the invention
Included attached drawing is used to provide that a further understanding of the embodiments of the present application, and which constitute one of specification
Point, for illustrating presently filed embodiment, and with verbal description come together to illustrate the principle of the application.Under it should be evident that
Attached drawing in the description of face is only some embodiments of the present application, for those of ordinary skill in the art, is not paying wound
Under the premise of the property made is laborious, it is also possible to obtain other drawings based on these drawings.In the accompanying drawings:
Fig. 1 is a schematic diagram of semiconductor device disclosed in patent document 1；
Fig. 2 is a schematic top plan view of the semiconductor element of the embodiment of the present application 1；
Fig. 3 is a schematic diagram of the A-A section of Fig. 2；
Fig. 4 is a schematic diagram of the B-B section of Fig. 2；
Fig. 5 is a schematic diagram of the C-C section of Fig. 2；
Fig. 6 is a schematic diagram of the semiconductor device of the embodiment of the present application 2.
Specific embodiment
Referring to attached drawing, by following specification, the aforementioned and other feature of the application be will be apparent.In specification
In attached drawing, specific implementations of the present application are specifically disclosed, which show wherein can be using the portion of the principle of the application
Divide embodiment, it will thus be appreciated that the application is not limited to described embodiment, on the contrary, the application includes falling into appended power
Whole modifications, modification and equivalent in the range of benefit requirement.
In addition, for convenience of description, semiconductor element is provided with gate pads in the following the description of the application
Surface be known as " upper surface ", the surface opposite with " upper surface " of the semiconductor element is known as " back side ", from " upper table
The direction of face " direction " back side " is known as "lower" direction, and the direction contrary with "lower" is known as "upper" direction.
Embodiment 1
The embodiment of the present application provides a kind of semiconductor element.
Fig. 2 is a schematic top plan view of the semiconductor element of the present embodiment.As shown in Fig. 2, the surface of semiconductor element 2
In quadrangle, also, the surface of semiconductor element 2 has the gate pads 21 for receiving control signal.
In the present embodiment, the quantity of gate pads 21 is at least two, wherein at least two gate pads 21 are distinguished
The both ends 2A1 and 2A2 of one side 2A of quadrangle are set.
It can make grid when the positional relationship of semiconductor element and control element changes according to the present embodiment
Pad is advantageously connected to control element, so, when manufacturing semiconductor device, it is different not need preparation gate pads position
Semiconductor element, to reduce the complexity of manufacture semiconductor device.
In the present embodiment, as shown in Figure 1, gate pads 21 are located at the corner on the surface of entire semiconductor element 2, by
This, gate pads 21 can independent of semiconductor element 2 interior layout and be arranged.
In the present embodiment, as shown in Figure 1, semiconductor element 2 can also have diode pad 22, diode pad 22
The another side 2B opposite with one side 2A of quadrangle can be arranged on.The quantity of diode pad 22 be also possible to two with
On, also, diode pad 22 can also be arranged on the both ends 2B1 and 2B2 of another side 2B.
In the present embodiment, it is arranged at opposite one side 2A respectively since diode pad 22 and gate pads 21 are located at
Therefore there is larger distance between diode pad 22 and gate pads 21, be applied to diode pad 22 with another side 2B
On voltage gate pads 21 will not be had an impact.
In the present embodiment, the voltage that diode pad 22 is born can be higher than the voltage that gate pads 21 are born, for example,
The voltage that diode pad 22 is born can be 600V or so, and the voltage that gate pads 21 are born can be 3V-15V, diode
There is larger distance, the high voltage being applied in diode pad 22 will not weld grid between pad 22 and gate pads 21
Disk 21 has an impact.
In the present embodiment, for diode pad 22 in the case where being applied voltage, which can be by conduct
Diode plays a role.
In the present embodiment, as shown in Fig. 2, diode pad 22 is located at the corner on the surface of semiconductor element 2, as a result,
Diode pad 22 can independent of semiconductor element 2 interior layout and be arranged.
In the present embodiment, as shown in Fig. 2, semiconductor element 2 can also have emitter pad 23, emitter pad 23
Can be between diode pad 22 and gate pads 21, also, on the direction for being parallel to one side 2A, emitter pad
23 can be located between two gate pads 21, and emitter pad 23 can be located at the center on the surface of semiconductor element 2 as a result,
Region is connected to the outside of semiconductor element 2 convenient for emitter pad 23 from multiple directions.
In the present embodiment, as shown with a dotted line in fig. 2, in the inside of semiconductor element 2, groove 24, ditch be can have
Groove portion 24 can be located at the lower section of emitter pad 23.In the present embodiment, gate electrode (not shown) can be via groove 24
It is connect with grid bus 25, grid bus 25 is electrically connected with gate pads 21, and gate electrode can be with 21 electricity of gate pads as a result,
Connection.
In the present embodiment, semiconductor element 2 can be power semiconductor, for example, the power semiconductor can
To be insulated gate bipolar transistor (IGBT) or Metal Oxide Semiconductor Field Effect Transistor (MOSFET) etc..Semiconductor
The material of element 2 can be silicon, in addition, the material of semiconductor element 2 is also possible to compound semiconductor, compound semiconductor member
Part is compared with silicon materials semiconductor element, the movement being able to carry out under the condition of high temperature, also, switching speed is very fast, is lost lower.
In the following, illustrating the internal structure of the semiconductor element 2 of Fig. 2 for IGBT.
Fig. 3 is a schematic diagram of the A-A section of Fig. 2, and Fig. 4 is a schematic diagram of the end face B-B of Fig. 2, and Fig. 5 is Fig. 2
C-C section a schematic diagram.
As shown in figure 3, being formed with active layer 27 in semiconductor substrate 26 in A-A section, wherein semiconductor substrate 26
It can be N-type, active layer 27 can be p-type, and the lightly doped district 27a in active layer 27 is P-type, lightly doped district 27a and substrate
Diode D is formed between 26.The surface of groove 24 and active layer 27 covers insulating film 28, and 28 surface of insulating film is covered with grid electricity
Pole 29, insulating film 30 between 29 surface coating of gate electrode, the opening and grid bus 25 that gate electrode 29 passes through interlayer dielectric 30
Connection.23 a part of emitter pad is located at 30 surface of interlayer dielectric, and another part is contacted with active layer 27.
As shown in figure 4, being formed with active layer 27 in semiconductor substrate 26 in B-B section, wherein semiconductor substrate 26
It can be N-type, active layer 27 can be p-type, and the lightly doped district 27a in active layer 27 is P-type, lightly doped district 27a and substrate
Diode D is formed between 26.The surface of groove 24 and active layer 27 covers insulating film 28, and 28 surface of insulating film is covered with grid electricity
Pole 29, insulating film 30 between 29 surface coating of gate electrode, 30 surface of interlayer dielectric is formed with gate pads 21.Emitter pad
23 a part are located at 30 surface of interlayer dielectric, and another part is contacted with active layer 27.
As shown in figure 5, being formed with active area 31,31 surface of active area covering two in semiconductor substrate 26 in C-C section
Pole pipe pad 22.In addition, collector pad 32 can also be formed in the lower surface of semiconductor element 2, diode pad as a result,
22, active area 31, semiconductor substrate 26 and collector pad 32 may be constructed diode structure.
In Fig. 3, Fig. 4 and Fig. 5, the internal structure of semiconductor element 2 is illustrated by taking IGBT as an example, the present embodiment
Can be without being limited thereto, semiconductor element can by other internal structures, also, semiconductor element 2 be also possible to have it is other
The element of function.
Embodiment 2
The present embodiment provides a kind of semiconductor devices, with semiconductor element described in embodiment 1.Due in embodiment
In 1, the structure of the semiconductor element is described in detail, content is incorporated in this, omits the description herein.
Fig. 6 is a schematic diagram of the semiconductor device of the present embodiment.As shown in fig. 6, semiconductor device 6 has embodiment
The grid bus 25 of semiconductor element 2 is not shown in Fig. 6 in semiconductor element 2 described in 1.
In the present embodiment, as shown in fig. 6, semiconductor device 6 has 2 along the direction V arrangement perpendicular to one side 2A
A above semiconductor element 2, wherein the slave diode pad 22 of at least one semiconductor element 2 is directed toward gate pads 21
The slave diode pad 22 that direction is different from other semiconductor elements 2 is directed toward the direction of gate pads 21, as a result, semiconductor element
2 can neatly adjust the direction of gate pads, consequently facilitating gate pads are connected with the outer member of semiconductor element 2.
In the present embodiment, semiconductor device 6 also has the control element 61 for generating control signal, the control element
61 are connected to the gate pads 21 of semiconductor element 2 by lead W1.
In the present embodiment, the adjacent semiconductor element 2 of semiconductor device 6 can be set to respective gate pads
21 is close to each other, and thereby, it is possible to be connected to control element by shorter lead convenient for the gate pads 21 of semiconductor element 2.
In the present embodiment, as shown in fig. 6, control element 61 can be located at this 2 with semiconductor elements 2 along this one
The side in the side direction 2A, that is to say, that control element 61 can be located at different column from this 2 with semiconductor elements 2, by
This, this 2 are located at phase the same side of control element 61 with semiconductor elements 2, convenient for semiconductor element 2 gate pads 21 with
Control element 61 connects.
In the present embodiment, the positional relationship of control element 61 and semiconductor element 2 can be not limited to shown in Fig. 6, for example,
Control element 61 can be located between 2 semiconductor elements 2 of the direction V arrangement perpendicular to one side 2A, that is, 2 half are led
Volume elements part 2 can be located at the two sides along direction V of control element 61.
In the present embodiment, as shown in fig. 6, the diode pad 22 of semiconductor element 2 can be connect with lead W2.
In the present embodiment, due to diode pad 22, gate pads 21 are arranged on the angle on the surface of semiconductor element 2
Portion, semiconductor element 2 can neatly adjust the direction of gate pads 21, thus both convenient for gate pads 21 by lead W1 with
Control element 61 can be such that lead W1 and lead W2 does not intersect spatially.In addition, lead W2 and being connected to emitter pad 23
Lead W3 can also not intersect spatially.
In the present embodiment, as shown in fig. 6, semiconductor device 6 can also have lead frame 62, wherein semiconductor element
Part 2 and control element 61 can be placed in lead frame.
In the present embodiment, control element 61 can be the semiconductor element for controlling communication pulse, and as power
The semiconductor element 2 of semiconductor element is compared, and the operating temperature of control element 61 can be lower.For example, control element 61 can be with
It is formed by silicon.
In the present embodiment, lead frame 62 can manufacture by existing manner, for example, to the tabular of 0.5mm thickness
Plate application punch process or chemical etching processing obtain.The material of lead frame 62 can be copper or copper alloy.This
Outside, the surface of lead frame 62 can carry out silver-plated process.
In the present embodiment, the material of lead W1, W2, W3 can be gold or aluminium etc..In addition, being connect with emitter pad 23
Lead W3 the angle lead (clip lead) formed by copper can be used, thus, it is possible to flow through high current.
In the present embodiment, semiconductor device 6 shown in fig. 6 can be used for carrying out three-phase drive, but the present embodiment can
With without being limited thereto, semiconductor device 6 also can have other functions.
In the semiconductor device of the present embodiment, when the positional relationship of semiconductor element and control element changes,
Gate pads can be made to be advantageously connected to control element, so, when manufacturing semiconductor device, do not need to prepare grid weldering
The different semiconductor element in disk position, to reduce the complexity of manufacture semiconductor device；Also, each weldering of semiconductor element
The lead of disk will not spatially intersect.
Combine specific embodiment that the application is described above, it will be appreciated by those skilled in the art that this
A little descriptions are all exemplary, and are not the limitation to the application protection scope.Those skilled in the art can be according to the application
Spirit and principle various variants and modifications are made to the application, these variants and modifications are also within the scope of application.
Claims (10)
1. a kind of semiconductor element has the gate pads for receiving control signal, it is characterised in that:
The surface of the semiconductor element is in quadrangle,
The quantity of the gate pads is at least two, wherein at least two gate pads are separately positioned on described four
The both ends on one side of side shape.
2. semiconductor element as described in claim 1, which is characterized in that
The semiconductor element also has a diode pad, the diode pad be arranged on the quadrangle with described one
The opposite another side in side.
3. semiconductor element as claimed in claim 2, which is characterized in that
The diode pad is higher than the voltage that the gate pads are born.
4. semiconductor element as claimed in claim 2, which is characterized in that
The semiconductor element also has emitter pad, and the emitter pad is located at the diode pad and the grid
Between pad, also, on the direction for being parallel to described one side, the emitter pad is located at described two gate pads
Between.
5. a kind of semiconductor device, which is characterized in that the semiconductor device has as of any of claims 1-4
Semiconductor element.
6. semiconductor device as claimed in claim 5, which is characterized in that
The semiconductor device has the two or more semiconductor element along the direction arrangement perpendicular to described one side,
In,
The direction that the slave diode pad of at least one semiconductor element is directed toward the gate pads is different from other described
The slave diode pad of semiconductor element is directed toward the direction of the gate pads.
7. semiconductor device as claimed in claim 6, which is characterized in that
The semiconductor device also has the control element for generating control signal,
The control element is connected to the gate pads of the semiconductor element by lead.
8. semiconductor device as claimed in claim 7, which is characterized in that
The control element is located at the side along an edge direction of described two semiconductor elements described above.
9. semiconductor device as claimed in claim 7, which is characterized in that
The control element is located between two semiconductor elements of the direction arrangement perpendicular to described one side.
10. semiconductor device as claimed in claim 7, which is characterized in that
The semiconductor device also has lead frame,
The semiconductor element and the control element are placed in the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711470436.7A CN109994445B (en) | 2017-12-29 | 2017-12-29 | Semiconductor element and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711470436.7A CN109994445B (en) | 2017-12-29 | 2017-12-29 | Semiconductor element and semiconductor device |
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| CN109994445A true CN109994445A (en) | 2019-07-09 |
| CN109994445B CN109994445B (en) | 2023-08-22 |
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| CN201711470436.7A Active CN109994445B (en) | 2017-12-29 | 2017-12-29 | Semiconductor element and semiconductor device |
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| Publication number | Publication date |
|---|---|
| CN109994445B (en) | 2023-08-22 |
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