JP2016012670A - Semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable detection of a part of a semiconductor substrate subjected to high temperature while achieving downsizing of a physical size in a semiconductor module capable of detecting temperature of the semiconductor substrate to higher temperature.SOLUTION: A semiconductor module comprises: a semiconductor device 14 which has a semiconductor substrate having an IGBT element 15 on which a gate electrode is formed on one surface side, and a plurality of gate pads 34a, 34b for external connection which are arranged on the one surface of the semiconductor substrate and connected to gate electrodes via gate wiring; and a gate drive circuit 18 for detecting temperature of the semiconductor substrate. The semiconductor device 14 includes a relay gate electrode for electrically relaying the two gate pads 34a, 34b as a gate electrode. The gate drive circuit 18 energizes the relay gate electrode via the two gate pads 34a, 34b and obtains temperature from resistance Rg between the gate pads in an energized state.

Description

  The present invention relates to a semiconductor module including a semiconductor substrate on which a switching element having a gate electrode is formed, and configured to detect the temperature of the semiconductor substrate.

  As a semiconductor module including a semiconductor substrate on which a switching element having a gate electrode is formed and configured to be able to detect the temperature of the semiconductor substrate (switching element), for example, one disclosed in Patent Document 1 is known.

  In Patent Document 1, a gate electrode made of polycrystalline silicon is arranged on one surface of a semiconductor substrate. A resistance temperature detector made of polycrystalline silicon is disposed in the same layer as the gate electrode. Sense pads are connected to both ends of the resistance temperature detector.

  According to this, the resistance value of the resistance temperature detector is measured as a potential difference generated between the sense pads by passing a constant current between the sense pads. Then, the temperature of the semiconductor substrate can be detected by converting the measured resistance value into a temperature from the temperature characteristic of the resistance value.

  Further, since the resistance temperature detector is used, it can be used up to a higher temperature than a diode made of polycrystalline silicon.

JP 2013-98316 A

  However, according to the configuration of Patent Document 1, the resistance thermometer must be arranged in a region different from the switching element formation region (active region) on one surface of the semiconductor substrate. It is difficult to downsize.

  In addition, since the resistance temperature detector is disposed around the active region, the temperature of the portion of the semiconductor substrate that is at a high temperature cannot be detected by driving the switching element.

  SUMMARY OF THE INVENTION In view of the above problems, the present invention has an object to enable detection of the temperature of a portion of a semiconductor substrate at a high temperature while reducing the size of the semiconductor module in a semiconductor module capable of detecting the temperature of the semiconductor substrate up to a higher temperature. And

  The invention disclosed herein employs the following technical means to achieve the above object. Note that the reference numerals in parentheses described in the claims and in this section indicate a corresponding relationship with specific means described in the embodiments described later as one aspect, and limit the technical scope of the invention. Not what you want.

  One of the disclosed inventions is a semiconductor substrate (20) having a switching element (15) in which a gate electrode (27) is formed on one side (20a), a gate wiring (33 ) And a plurality of external connection gate pads (34) connected to the gate electrode, and a temperature detection unit (18) for detecting the temperature of the semiconductor substrate.

  And as a gate electrode, the relay gate electrode (27a) which electrically relays two gate pads (34a, 34b) is included. The temperature detector is characterized in that the relay gate electrode is energized through two gate pads and the temperature is obtained from the resistance value between the gate pads in the energized state.

  According to this, the relay gate electrode is used as a temperature detection resistor. Therefore, the temperature of the semiconductor substrate (switching element) can be obtained from the resistance value between the gate pads when energized by the temperature detector, that is, the temperature of the semiconductor substrate can be detected.

  Further, since the relay gate electrode is used as a temperature detection resistor, it can be used at a higher temperature than when a diode made of polycrystalline silicon is employed.

  In addition, since the relay gate electrode is used not only as a gate electrode but also as a temperature detection resistor, the size of the semiconductor substrate is reduced compared to a configuration in which a temperature detection resistor is provided separately from the gate electrode. can do.

  Incidentally, the channel resistance occupies most of the on-resistance of the switching element. That is, the channel portion generates the most heat. In the present invention, since the temperature is detected by the relay gate electrode, the temperature of the channel portion, that is, the temperature of the high temperature portion of the semiconductor substrate can be detected.

It is a figure which shows schematic structure of the semiconductor module which concerns on 1st Embodiment. It is a top view which shows schematic structure of a semiconductor device among semiconductor modules. It is sectional drawing which follows the III-III line of FIG. It is a figure which shows schematic structure of a gate drive circuit. It is a figure which shows operation | movement to the gate drive circuit at the time of IGBT element drive. It is a figure for demonstrating the temperature measurement method. It is a figure for demonstrating the temperature measurement method. It is a figure which shows the 1st modification of a gate drive circuit. It is a figure which shows the 2nd modification of a gate drive circuit. It is a figure which shows the 3rd modification of a gate drive circuit. It is a top view which shows schematic structure of a semiconductor device among the semiconductor modules which concern on 2nd Embodiment. It is a top view which shows schematic structure of a semiconductor device among the semiconductor modules which concern on 3rd Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol is provided to the part which is mutually the same or equivalent in each figure below. Further, the thickness direction of the semiconductor substrate 20 is indicated as a Z direction. Further, the extending direction of the gate electrode 27 is perpendicular to the Z direction and is indicated as the X direction. A direction perpendicular to both the X direction and the Z direction is referred to as a Y direction. A shape along a plane defined by the X direction and the Y direction is referred to as a planar shape.

(First embodiment)
First, a schematic configuration of the semiconductor module will be described with reference to FIG.

  A semiconductor module 10 (power converter) shown in FIG. 1 is configured to convert a DC voltage supplied from a DC power supply 100 into a three-phase AC and output it to a motor generator 101 (hereinafter referred to as MG101). ing. Such a semiconductor module 10 is mounted on, for example, an electric vehicle or a hybrid vehicle. The semiconductor module 10 can also convert the electric power generated by the MG 101 into a direct current and charge the direct current power supply 100 (battery). In addition, the code | symbol 102 shown in FIG. 1 is a smoothing capacitor. In FIG. 1, only the DC power supply 100 is shown as the DC input unit, but a voltage conversion unit such as a boost converter may be provided in addition thereto.

  The semiconductor module 10 has a three-phase inverter 11. The three-phase inverter 11 is provided between a high-potential power line 12 connected to the positive electrode (high potential side) of the DC power supply 100 and a low-potential power line 13 connected to the negative electrode (low potential side). It has upper and lower arms for each phase. The upper and lower arms of each phase are constituted by two semiconductor devices 14.

  The semiconductor device 14 includes a switching element and a reflux element connected to the switching element in antiparallel. In the present embodiment, an IGBT element 15 as a switching element and an FWD element 16 as a reflux element are configured on the same semiconductor substrate. The IGBT element 15 corresponds to a switching element described in the claims, and the FWD element 16 corresponds to a free-wheeling diode. However, the IGBT element and the FWD element may be configured in separate chips. In the present embodiment, an n-channel IGBT element is employed. The cathode electrode of the FWD element 16 is shared with the collector electrode 15c of the IGBT element 15, and the anode electrode is shared with the emitter electrode 15e.

  In the semiconductor device 14 on the upper arm side, the collector electrode 15 c of the IGBT element 15 is electrically connected to the high potential power supply line 12, and the emitter electrode 15 e is connected to the output line 17 to the MG 101. In the semiconductor device 14 on the lower arm side, the collector electrode 15 c of the IGBT element 15 is connected to the output line 17 to the MG 101, and the emitter electrode 15 e is electrically connected to the low potential power supply line 13.

  In addition, the semiconductor module 10 has a gate drive circuit 18. The gate drive circuit 18 drives the three-phase inverter 11, that is, each IGBT element 15, according to a control command from an external control circuit (for example, MGECU) (not shown). The gate drive circuit 18 outputs a signal corresponding to the drive torque to be generated by the MG 101 to the gate electrode 15g of the IGBT element 15 as a drive control signal. In the present embodiment, the gate drive circuit 18 has a function of detecting the temperature of the semiconductor substrate on which the IGBT element 15 is configured. That is, the gate drive circuit 18 corresponds to the temperature detection unit described in the claims.

  Next, a schematic configuration of the semiconductor device 14 will be described with reference to FIGS. In FIG. 2, for convenience, the emitter electrode, the protective film, the interlayer insulating film, and the like are omitted, and the active region is indicated by a broken line. FIG. 3 corresponds to a cross section taken along line III-III in FIG.

  In this embodiment, a punch-through type IGBT element 15 is shown as an example. However, the present invention is not limited to this, and a non-punch through type or field stop type IGBT element 15 can also be employed.

  As shown in FIGS. 2 and 3, the semiconductor device 14 includes a semiconductor substrate 20, and the IGBT element 15 described above is formed in the active region 21 of the semiconductor substrate 20. Further, the FWD element 16 is also built in the semiconductor substrate 20. The active region 21 is a region in which the IGBT element 15 composed of a plurality of IGBT cells is arranged and conducts the main current. The active region 21 corresponds to a switching element forming region described in the claims.

  The semiconductor substrate 20 is formed using silicon as a material, and has one surface 20a and a back surface 20b opposite to the one surface 20a in the Z direction. The semiconductor substrate 20 includes a first conductivity type (p +) substrate layer 22 having a relatively high impurity concentration, and a second conductivity type (n−) drift having a relatively low impurity concentration that is epitaxially grown on the substrate layer 22. Layer 23. The substrate layer 22 functions as a collector region of the IGBT element 15. The surface of the substrate layer 22 opposite to the drift layer 23 forms the back surface 20b. Note that a second conductivity type (n +) buffer layer having a relatively high impurity concentration may be provided between the substrate layer 22 and the drift layer 23.

  A base region 24 of the first conductivity type (p) is selectively formed on the surface layer of the drift layer 23 opposite to the substrate layer 22. Then, a trench 25 is formed with a predetermined depth so as to penetrate the base region 24 from the one surface 20a side of the semiconductor substrate 20 and the tip reaches the drift layer 23. A gate insulating film 26 is disposed on the wall surface of the trench 25. A gate electrode 27 made of polycrystalline silicon is formed so as to fill the trench 25 via the gate insulating film 26. Thus, in this embodiment, the trench gate type IGBT element 15 is formed.

  As shown in FIG. 2, the gate electrode 27 (trench 25) extends along the X direction, and a plurality of gate electrodes 27 are arranged in parallel at a predetermined pitch in the Y direction. By providing the gate electrodes 27 in a stripe shape in this way, a plurality of IGBT cells are formed in the active region 21.

  A second conductivity type (n +) emitter region 28 having a relatively high impurity concentration is formed in the surface layer of the base region 24 so as to be adjacent to the gate electrode 27 having a trench structure. A contact region 29 of the first conductivity type (p +) having a relatively high impurity concentration is formed adjacent to the emitter region 28 on the surface layer of the base region 24. Therefore, in the portion where the emitter region 28 and the contact region 29 are provided on the surface layer, the surfaces of the emitter region 28 and the contact region 29 form one surface 20 a of the semiconductor substrate 20.

  The gate electrode 27 is covered with an interlayer insulating film 30. An emitter electrode 31 is formed on the interlayer insulating film 30 using a metal material. The emitter electrode 31 is electrically connected to the emitter region 28 and the contact region 29. The emitter electrode 31 is provided in almost the entire active region 21. On the other hand, a collector electrode 32 is formed on the back surface 20b of the semiconductor substrate 20 using a metal material. The collector electrode 32 is formed on almost the entire back surface 20b.

  A gate wiring 33 is formed around the active region 21 on the one surface 20a of the semiconductor substrate 20 via a field oxide film or an interlayer insulating film (not shown). The gate wiring 33 is formed using a metal material such as aluminum. The gate electrode 27 is electrically connected to the gate wiring 33 via an interlayer connection (via) (not shown) provided in the interlayer insulating film 30. In the present embodiment, the active area 21 has a substantially rectangular plane shape. The gate wiring 33 has a first gate wiring 33a and a second gate wiring 33b extending in the Y direction. The first gate wiring 33a is arranged along one rectangular side of the active region 21, and the second gate wiring 33b is arranged along the opposite side to the first gate wiring 33a. That is, in the X direction, the active region 21 is sandwiched between the two gate wirings 33a and 33b.

  A part of the gate wiring 33 serves as a gate pad 34 for receiving a drive control signal from the gate drive circuit 18. Therefore, the drive control signal input from the gate pad 34 is supplied to the gate electrode 27 via the gate wiring 33. In the present embodiment, a first gate pad 34a is provided as a part of the first gate wiring 33a, and a second gate pad 34b is provided as a part of the second gate wiring 33b. Thus, the two gate pads 34 (34a, 34b) are provided.

  All the gate electrodes 27 have one end electrically connected to the first gate pad 34a via the first gate wiring 33a and the other end electrically connected to the second gate pad 34b via the second gate wiring 33b. Connected. That is, all the gate electrodes 27 are relay gate electrodes 27a that electrically relay the two gate pads 34a and 34b.

  In the semiconductor device 14 configured as described above, as shown in FIG. 3, for example, in a state where 0 V (ground) is applied to the emitter electrode 31 and a positive voltage is applied to the collector electrode, the gate electrode 27 has a threshold voltage Vt or higher. When a voltage is applied, the portion of the base region 24 adjacent to the gate electrode 27 is inverted from the first conductivity type (p) to the second electric type (n), and from the collector electrode 32 to the emitter electrode 31 as indicated by an arrow. A current (collector current) flows in the direction. Of the on-resistances of the IGBT element 15, the channel resistance Rc is the highest. Therefore, when the IGBT element 15 is driven, heat is generated most from the channel portion.

  Next, the gate drive circuit 18 will be described with reference to FIG. In FIG. 4, only one semiconductor device 14 (one IGBT element 15) is shown as a temperature detection target by the gate drive circuit 18 for convenience. However, the temperature of the remaining five semiconductor devices 14 (IGBT elements 15) can also be detected by the gate drive circuit 18.

  As shown in FIG. 4, the gate drive circuit 18 has two voltage sources 40 and 41. These voltage sources 40 and 41 are configured so that the output voltage is variable based on a signal input from an MGECU (not shown). The first voltage source 40 generates a voltage equal to or higher than the threshold voltage Vt of the IGBT element 15 and a voltage lower than the threshold, and outputs the voltage as the voltage Vg3. Specifically, when the threshold voltage Vt is 15 V, 15.1 V that is a voltage equal to or higher than the threshold is generated at a predetermined timing, and 0.1 V that is less than the threshold is generated at a timing different from the voltage generation of 15.1 V. Is generated.

  The second voltage source 41 also generates and outputs a voltage equal to or higher than the threshold voltage Vt of the IGBT element 15 and a voltage lower than the threshold based on a signal input from the MGECU. Specifically, 15V that is a voltage equal to or higher than the threshold is generated at a predetermined timing, and 0V that is a voltage lower than the threshold is generated at a timing different from the voltage generation of 15V.

  The first voltage source 40 is electrically connected to the first gate pad 34a of the semiconductor device 14 via the current detection resistor R1. The current detection resistor R1 is set such that voltages Vg1 and Vg2, which will be described later, have different values with respect to the voltages generated by the voltage sources 40 and 41 during temperature detection. For example, when the switch SW1, which will be described later, is closed, when the first voltage source 40 generates 15.1V and the second voltage source 41 generates 15V, the voltages Vg1 and Vg2 have different values (Vg1> Vg2). Is set to

  The second voltage source 41 is connected to the second gate pad 34b of the semiconductor device 14 via the switch SW1. The switch SW1 is controlled to open and close based on a signal input from the MGECU. When the switch SW1 is closed, the second voltage source 41 and the second gate pad 34b are electrically connected. When the switch SW1 is in an open state, the second voltage source 41 and the second gate pad 34b are cut off, and the second gate pad 34b is electrically connected to the first voltage source 40 via the switch SW1 and the current detection resistor R1. Connected. The broken line in FIG. 4 indicates the open state of the switch SW1.

  The gate drive circuit 18 further includes a current detection unit 42, a voltage detection unit 43, a calculation unit 44, and a memory 45. The current detection unit 42 calculates the current flowing through the current detection resistor R1 from the potential difference between both ends of the current detection resistor R1 and the resistance value (fixed value) of the current detection resistor R1. In this way, the current detection unit 42 detects the current flowing through the current detection resistor R1, that is, the current flowing through the resistor Rg described later.

  The voltage detector 43 detects a difference (potential difference) between the voltage Vg1 applied to the first gate pad 34a and the voltage Vg2 applied to the second gate pad 34b. That is, the voltage detection unit 43 detects a voltage applied to both ends of the resistor Rg.

  The calculation unit 44 acquires the value of the current flowing through the current detection resistor R1 from the current detection unit 42, and acquires the potential difference between the two gate pads 34a and 34b from the voltage detection unit 43. From these values, the value of the resistance Rg of the relay gate electrode 27a (hereinafter referred to as the gate internal resistance Rg) is calculated. The resistance value of the relay gate electrode 27a made of polycrystalline silicon has temperature characteristics (temperature dependence). For example, the calculation unit 44 converts the resistance value into a temperature from a map indicating the relationship between the resistance value and the temperature stored in advance in the memory 45. When the calculated temperature is equal to or higher than a preset temperature, a fail safe signal is output to the MGECU.

  Thus, the temperature of the semiconductor substrate 20 (IGBT element 15) can be detected by the gate drive circuit 18 by using the relay gate electrode 27a as a temperature measurement resistor.

  Since the gate internal resistance Rg is a resistance between the two gate pads 34a and 34b, strictly speaking, the resistance includes not only the above-described relay gate electrode 27a but also the gate wiring 33 and the like. However, since the gate wiring 33 is formed using a metal material having excellent conductivity such as aluminum, the relay gate electrode 27a made of polycrystalline silicon occupies most of the resistance.

  Next, a temperature measurement method will be described with reference to FIGS.

  First, a driving method (without temperature measurement) of the IGBT element 15 will be described. A voltage Ve shown in FIG. 5 is an emitter voltage applied to the emitter electrode 31. The voltage Ve is 0 V (ground), and the first voltage source 40 outputs a voltage Vg3 of 15.1 V with respect to the voltage Ve. Further, the SW1 is opened, so that the voltages Vg1 and Vg2 are equal to each other. In this case, the current detection resistor R1 can also be used as an external gate resistor. Since the second voltage source 41 is disconnected from the second gate pad 34b by the switch SW1, the generated voltage is not particularly limited.

  Next, a method for measuring temperature when the IGBT element 15 is driven (on period) will be described. The gate drive circuit 18 temporarily measures the temperature during the ON period of the IGBT element 15. As shown in FIG. 6, the switch SW1 is closed, the first voltage source 40 generates 15.1V, and the second voltage source 41 generates 15V. Thereby, the current Ia flows through the current detection resistor R1, and the current Ia is calculated from the known resistance value and the difference between the voltage Vg3 and the voltage Vg1. Further, the voltage Vg1 and the voltage Vg2 have different values. That is, different voltages are applied to the two gate pads 34a and 34b. Therefore, the gate internal resistance Rg can be calculated from the difference between the voltage Vg1 and the voltage Vg2 and the current Ia, and the temperature can be obtained from the temperature characteristics of the gate internal resistance Rg.

  Since the voltages generated by the first voltage source 40 and the second voltage source 41 are both equal to or higher than the threshold voltage Vt and close to each other, it is possible to turn on the IGBT element 15 while measuring the temperature. it can.

  Next, a method for measuring temperature when the IGBT element 15 is not driven (off period) will be described. The gate drive circuit 18 temporarily measures the temperature during the off period of the IGBT element 15. Except for the fact that the voltages generated by the first voltage source 40 and the second voltage source 41 are different, this is the same as FIG. As shown in FIG. 7, the switch SW1 is closed, the first voltage source 40 generates 0.1V, and the second voltage source 41 generates 0V. As a result, since the current Ia flows through the current detection resistor R1, the current Ia is calculated from the known resistance value and the difference between the voltage Vg3 and the voltage VG1. Further, the voltage Vg1 and the voltage Vg2 have different values. That is, different voltages are applied to the two gate pads 34a and 34b. Therefore, the gate internal resistance Rg can be calculated from the difference between the voltage Vg1 and the voltage Vg2 and the current Ia, and the temperature can be obtained from the temperature characteristics of the gate internal resistance Rg.

  Since the voltages generated by the first voltage source 40 and the second voltage source 41 are both less than the threshold voltage Vt, the IGBT element 15 can be turned off while measuring the temperature.

  Next, effects of the semiconductor device 14 and the semiconductor module 10 described above will be described.

  In this embodiment, the relay gate electrode 27a is used as a temperature detection resistor. Therefore, the temperature of the semiconductor substrate 20 (IGBT element 15) can be obtained from the value of the gate internal resistance Rg when the gate drive circuit 18 is energized, that is, the temperature of the semiconductor substrate 20 can be detected.

  Further, since the relay gate electrode 27a is used as a temperature detecting resistor, the relay gate electrode 27a can be used at a higher temperature than when a diode made of polycrystalline silicon is employed. In addition, the manufacturing process of the semiconductor device 14 can be simplified.

  Further, since the relay gate electrode 27a is used not only as the gate electrode 27 but also as a temperature detecting resistor, the semiconductor device 14 (semiconductor device 14) is compared with a configuration in which a temperature detecting resistor is provided separately from the gate electrode. The size of the substrate 20) can be reduced.

  By the way, the channel resistance Rc occupies most of the on-resistance of the IGBT element 15. That is, most heat is generated from the channel portion during the ON period of the IGBT element 15. On the other hand, in this embodiment, since the temperature is detected using the relay gate electrode 27a adjacent to the channel as a temperature detection resistor, the temperature of the channel portion, that is, the temperature of the semiconductor substrate 20 at a high temperature is accurately measured. Can be detected well. Thereby, the accuracy of fail-safe processing can be improved. Further, the temperature can be detected with good responsiveness in response to the temperature change of the semiconductor substrate 20.

  According to the configuration of the present embodiment, the gate driving circuit 18 applies voltages having a value equal to or higher than the threshold voltage Vt to the two gate pads 34a and 34b during the ON period of the IGBT element 15. be able to. Therefore, the IGBT element 15 can be driven while measuring the temperature. That is, the temperature of the driving state of the IGBT element 15 can be detected.

  Further, according to the configuration of the present embodiment, the gate driving circuit 18 applies voltages having different values to the two gate pads 34a and 34b that are less than the threshold voltage Vt during the off period of the IGBT element 15. Can be applied. Therefore, the IGBT element 15 can be turned off while measuring the temperature. That is, the temperature of the semiconductor substrate 20 during regeneration by the FWD element 16 can be detected.

  In the present embodiment, when the IGBT element 15 is driven (without temperature measurement), the switch SW1 is opened and the voltage Vg3 of the first voltage source 40 is applied to the two gate pads 34a and 34b. It was. However, the switch SW1 may be provided between the current detection resistor R1 on the first voltage source 40 side and the first gate pad 34a, and the switch SW1 may be opened when the IGBT element 15 is driven (without temperature measurement). . In this case, the voltage 15V of the second voltage source 41 is applied to the two gate pads 34a and 34b. When the IGBT element 15 is not driven (without temperature measurement), the voltage 0 V of the second voltage source 41 is applied to the two gate pads 34a and 34b in the same manner.

  In the present embodiment, an example in which the gate drive circuit 18 includes two voltage sources 40 and 41 has been described. However, a configuration having only the first voltage source 40 as in the first modification shown in FIG. 8 may be employed. In FIG. 8, the gate drive circuit 18 has a step-down circuit 46 instead of the second voltage source 41. Other configurations are the same as those in FIG. In this case, when the first voltage source 40 generates 15.1V, the step-down circuit 46 reduces the voltage to generate 15V. When the first voltage source 40 generates 0.1V, the step-down circuit 46 steps down the voltage to generate 0V. Note that only the second voltage source 41 may be provided, and this output may be boosted by a booster circuit.

  Further, a configuration without the switch SW1 as in the second modified example shown in FIG. 9 may be employed. In FIG. 9, the gate drive circuit 18 includes a first voltage source 47 and a second voltage source 41. The second voltage source 41 generates 15 V and 0 V as in the above embodiment. On the other hand, unlike the above embodiment, the first voltage source 47 generates 15.1V, 15V, 0.1V, and 0V. Specifically, the first voltage source 47 generates 15 V when the IGBT element 15 is driven (without temperature measurement). When the temperature is measured when the IGBT element 15 is driven, the first voltage source 47 generates 15.1V. When the temperature is measured when the IGBT element 15 is not driven, the first voltage source 47 generates 0.1V. When the IGBT element 15 is not driven (without temperature measurement), the first voltage source 47 generates 0V. In FIG. 9, reference symbol R2 is an external gate resistance on the second voltage source 14 side.

  Furthermore, a configuration in which the gate drive circuit 18 includes a constant current source 48 as in the third modification shown in FIG. The gate drive circuit 18 shown in FIG. 10 includes a constant current source 48 instead of the voltage source, and is configured as a constant current drive gate drive circuit. The constant current source 48 is connected to the first gate pad 34a. Further, the gate drive circuit 18 has a switch SW2 connected in parallel to the gate internal resistance Rg. Temperature measurement is performed when the switch SW2 is open, and normal control is performed when the switch SW2 is closed. The switch SW2 is controlled to open and close based on a signal input from the MGECU.

  Specifically, a constant current is output from the constant current source 48, and after the potential of the gate electrode 27 becomes constant due to the constant current, the switch SW2 is opened as shown in FIG. In this open state, when the current is instantaneously extracted, that is, when the supply by the constant current source 48 is stopped for a moment, a difference occurs between the voltages Vg1 and Vg2. This potential difference is detected by the voltage detection unit 43, and the calculation unit 44 calculates the value of the gate internal resistance Rg from the detected potential difference and constant current value, and in turn converts the resistance value into temperature. Thus, temperature measurement can be performed when the IGBT element 15 is driven.

  On the other hand, after the current is drawn and the potential of the gate electrode 27 becomes 0 V, the switch SW2 is opened. When a current is instantaneously supplied in this open state, that is, when a constant current is supplied from the constant current source 48, a difference occurs between the voltages Vg1 and Vg2. This potential difference is detected by the voltage detection unit 43, and the calculation unit 44 calculates the value of the gate internal resistance Rg from the detected potential difference and the constant current value. Also, the resistance value is converted into temperature. In this way, the temperature can be measured when the IGBT element 15 is not driven.

(Second Embodiment)
In the present embodiment, descriptions of parts common to the semiconductor device 14 and the semiconductor module 10 shown in the first embodiment are omitted.

  In the first embodiment, an example in which all the gate electrodes 27 are relay gate electrodes 27a has been described. On the other hand, in this embodiment, as shown in FIG. 11, only a part of the gate electrode 27 is used as the relay gate electrode 27a, and the remaining gate electrode 27 is connected to only one of the gate pads 34a and 34b. Has been.

  The emitter electrode 31 of the semiconductor device 14 is soldered to a member (not shown) such as a lead. Solder is disposed on almost the entire surface of the emitter electrode 31. The emitter electrode 31 corresponds to a surface electrode to be soldered according to the claims. As in the first embodiment, the plurality of gate electrodes 27 are each extended in the X direction and juxtaposed in the Y direction. This Y direction corresponds to the first direction described in the claims.

  In such a configuration, the temperature near the center 21a of the active region 21 is the highest. Reference numeral 21 b illustrated in FIG. 11 indicates a portion of the active region 21 where the temperature is increased by driving the IGBT element 15, that is, a temperature increasing portion. The center of the temperature rise portion 21b substantially coincides with the center 21a.

  Therefore, in the present embodiment, the relay gate electrode 27a is disposed in the first region 21c including the center 21a in the active region 21. The 1st field 21c is set up corresponding to temperature rise part 21b. On the other hand, a gate-dedicated electrode 27b that is electrically connected to only one of the gate pads 34a and 34b is disposed in the second region 21d that is the region excluding the first region 21c in the active region 21. . Since the gate-dedicated electrode 27b is electrically connected to only one of the gate pads 34a and 34b, it does not function as a temperature detection resistor but only as a gate electrode.

  Specifically, in the Y direction, the second area 21d, the first area 21c, and the second area 21d are set in this order. Of the two second regions 21d, the gate-dedicated electrode 27b of one second region 21d is connected to the first gate pad 34a via the first gate wiring 33a, and is dedicated to the gate of the other second region 21d. The electrode 27b is connected to the second gate pad 34b through the second gate wiring 33b.

  Thus, according to the present embodiment, it is possible to detect the temperature of the portion of the semiconductor substrate 20 (IGBT element 15) where the temperature is particularly high. Further, the relay gate electrode 27a that functions as a temperature detection resistor is disposed only in the first region 21c including the temperature rise portion 21b where the temperature rises, and the second region 21d functions as a temperature detection resistor. A gate-dedicated electrode 27b is provided. According to this, the term of the resistance of the gate electrode 27 that changes in temperature can be increased in (resistance of the gate electrode 27 that changes in temperature) / (resistance of all the gate electrodes 27). That is, sensor sensitivity can be increased.

(Third embodiment)
In the present embodiment, descriptions of parts common to the semiconductor device 14 and the semiconductor module 10 shown in the second embodiment are omitted.

  In the second embodiment, the example in which the relay gate electrode 27a is arranged only in part in the configuration in which the emitter electrode 31 is joined by soldering has been described. On the other hand, in this embodiment, a bonding wire (not shown) is joined to the emitter electrode 31 as the surface electrode. As in the second embodiment, the plurality of gate electrodes 27 are each extended in the X direction and juxtaposed in the Y direction.

  In such a configuration, the temperature of the active region 21 in the vicinity of the bonding region of the bonding wire, specifically, the portion immediately below the bonding region of the bonding wire becomes high when the IGBT element 15 is driven. Reference numeral 21 e shown in FIG. 12 indicates a portion of the active region 21 where the temperature becomes high when the IGBT element 15 is driven, that is, a temperature increasing portion. The temperature rise portion 21e corresponds to the bonding region of the bonding wire described above. In the example shown in FIG. 12, bonding wires are joined at three locations.

  Therefore, in the present embodiment, the relay gate electrode 27a is disposed in the bonding region of the bonding wire, that is, the third region 21f including the temperature rising portion 21e in the active region 21. On the other hand, the gate-dedicated electrode 27b is arranged in the fourth region 21g, which is the region excluding the third region 21f, in the active region 21.

  Specifically, in the Y direction, the fourth region 21g, the third region 21f, the fourth region 21g, the third region 21f, the fourth region 21g, and the third region 21f are set in this order. Further, the gate dedicated electrode 27b is alternately connected to the first gate pad 34a and connected to the second gate pad 34b in the order of arrangement in the Y direction.

  Thus, according to the present embodiment, it is possible to detect the temperature of the portion of the semiconductor substrate 20 (IGBT element 15) where the temperature is particularly high. In addition, the relay gate electrode 27a that functions as a temperature detection resistor is disposed only in the third region 21f including the temperature rise portion 21e where the temperature rises, and the fourth region 21g functions as a temperature detection resistor. A gate-dedicated electrode 27b is disposed. According to this, the term of the resistance of the gate electrode 27 that changes in temperature can be increased in (resistance of the gate electrode 27 that changes in temperature) / (resistance of all the gate electrodes 27). That is, sensor sensitivity can be increased.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  Although an example of the trench gate type IGBT element 15 has been shown, the present invention is not limited to this. Other structures such as a planar gate type may be employed.

  Although the example of the IGBT element 15 was shown as a switching element formed in the semiconductor substrate 20, it is not limited to this. For example, a power MOSFET can be employed.

  In the example, the gate pad 34 has two gate pads 34a and 34b. However, the number of gate pads 34 is not limited to two. It is good also as a structure provided with three or more. Also in this case, the temperature can be detected by energizing the relay gate electrode 27a through two gate pads connected to the relay gate electrode 27a among the three or more gate pads 34.

  The control target of the gate drive circuit 18 is not limited to the three-phase inverter 11. What is necessary is just to control the drive of at least one IGBT element 15 (semiconductor device 14).

DESCRIPTION OF SYMBOLS 10 ... Semiconductor module, 11 ... Three-phase inverter, 12 ... High potential power line, 13 ... Low potential power line, 14 ... Semiconductor device, 15 ... IGBT element, 16 ... FWD element, 17 ... Output line, 18 ... Gate drive circuit 20 ... Semiconductor substrate, 20a ... One side, 20b ... Back side, 21 ... Active region, 21a ... Center, 21b, 21e ... Temperature rising part, 21c ... First region, 21d ... Second region, 21f ... Third region, 21g ... 4th region, 22 ... Substrate layer, 23 ... Drift layer, 24 ... Base region, 25 ... Trench, 26 ... Gate insulating film, 27 ... Gate electrode, 27a ... Relay gate electrode, 27b ... Gate-dedicated electrode, 28 ... Emitter Region, 29 ... contact region, 30 ... interlayer insulating film, 31 ... emitter electrode, 32 ... collector electrode, 33 ... gate wiring, 33a ... first gate wiring, 3b ... second gate wiring, 34 ... gate pad, 34a ... first gate pad, 34b ... second gate pad, 40, 47 ... first voltage source, 41 ... second voltage source, 42 ... current detection unit, 43 ... Voltage detection unit, 44: arithmetic unit, 45: memory, 46: step-down circuit, 48: constant current source, 100: DC power supply, 101: motor generator, 102: smoothing capacitor, R1: resistance for current detection, R2: gate resistance , Rc: channel resistance, Rg: gate electrode resistance

Claims (7)

A semiconductor substrate (20) having a switching element (15) having a gate electrode (27) formed on one surface (20a) side;
A plurality of gate pads (34) for external connection disposed on the one surface of the semiconductor substrate and connected to the gate electrode via a gate wiring (33);
A temperature detector (18) for detecting the temperature of the semiconductor substrate;
With
The gate electrode includes a relay gate electrode (27a) that electrically relays the two gate pads (34a, 34b),
The temperature detection unit energizes the relay gate electrode through the two gate pads, and obtains a temperature from a resistance value between the gate pads in an energized state.   The semiconductor module according to claim 1, wherein the temperature detection unit applies different voltages to the two gate pads.   The temperature detection unit applies a voltage having a value that is equal to or higher than a threshold voltage of the gate electrode to the two gate pads during a period in which the switching element is turned on. 2. The semiconductor module according to 2. On the semiconductor substrate, a free-wheeling diode (16) connected in reverse parallel to the switching element is formed,
The temperature detecting unit applies a voltage having a value lower than a threshold voltage of the gate electrode and different from each other to the two gate pads in a period in which the switching element is turned off. The semiconductor module of Claim 2 or Claim 3.   The semiconductor module according to claim 1, wherein the temperature detection unit causes a constant current to flow between the two gate pads. The semiconductor substrate further includes a surface electrode (31) disposed on the one surface corresponding to the switching element formation region (21) in the semiconductor substrate and solder-joined.
The semiconductor substrate has a plurality of the gate electrodes,
The plurality of gate electrodes are juxtaposed in a first direction along the one surface of the semiconductor substrate, and in the first direction, in a first region (21c) including the center (21a) of the switching element formation region. The relay gate electrode is disposed, and the gate electrode (27b) electrically connected to only one of the gate pads is disposed in the second region (21d) excluding the first region. The semiconductor module according to claim 1, wherein the semiconductor module is characterized in that: A surface electrode (31) disposed on the one surface corresponding to the switching element formation region (21) in the semiconductor substrate and to which a bonding wire is bonded is further provided.
The semiconductor substrate has a plurality of the gate electrodes,
The plurality of gate electrodes are arranged in parallel in a first direction along the one surface of the semiconductor substrate, and the relay gate electrodes are arranged in a third region (21f) including a bonding region of the bonding wires in the first direction. The gate electrode (27b) electrically connected to only one of the gate pads is disposed in the fourth region (21g) excluding the third region. Item 6. The semiconductor module according to any one of Items 1 to 5.

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