JPH02170437A - Manufacture of mis-type semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an electric field from being concentrated in a drain diffusion region part and to eliminate a drop in breakdown strength and reliability by a method wherein a peripheral edge part of a selective oxide film pattern and a peripheral part of a gate electrode are crossed at obtuse angles. CONSTITUTION:An opening-part pattern 2 of a selective oxide film 1 formed by a LOCOS method forms a funnel shape where a large rectangle and a small rectangle are connected at oblique sides formed at 45 deg. with sides of the rectangles. Accordingly, a crossing angle of the pattern 2 and a peripheral edge of a gate electrode 3 on the drain side becomes 135 deg.. As a result, corner parts 6 on the channel side in a drain region formed by diffusion of impurities by making use of the film 1 and the electrode 3 as a mask has an angle of 135 deg.; an electric field is not concentrated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to the manufacture of a MIS type semiconductor device in which a gate electrode is provided on an intermediate portion between a source impurity diffusion region and a drain impurity diffusion region with a gate insulating film interposed therebetween. Regarding the method.

(Prior Art) In order to form the source region and drain region of a MIS type semiconductor device, for example, an MO5 type field effect transistor (MOSFET), conventionally, as shown in Fig. 2, openings are formed on a semiconductor substrate by the LOCO3 method. Impurities were introduced in a self-aligned manner as a gate electrode i4 mask provided over the thick selective oxidation region 1 forming the pattern 2 and the center portion of the thin gate oxide film formed within the opening pattern 2.

Drain diffusion layer region 4. Source diffusion layer region 5 is formed in this manner.

[Invention tries to solve it! li! 3MO3 type FE
With the miniaturization of T, problems arise such as a decrease in drain breakdown voltage and a decrease in reliability due to the generation of hot carriers. One of the causes is the electric field concentration at the channel side corner part 6 of the drain diffusion layer region 4. The mechanism of this electric field concentration is as follows. That is, if each terminal of the gate 3, source 5, and substrate is fixed at ground potential and the potential of the drain terminal is increased, the arrow 7
The electric field strength vector shown by is most likely to be concentrated in the corner part 6 on the channel side of the drain region 4, and avalanche breakdown is likely to occur first.This tendency is due to M
This problem becomes more noticeable as the O3 type FET becomes smaller and the junction depth of the drain region 4 becomes shallower. In other words, when the junction depth is relatively deep as shown in FIG. If the junction depth is relatively shallow as shown in (3), the radius of curvature of some corners will be small, making it easier for electric field concentration to occur.As a countermeasure for this,
As shown in FIG. 4, source diffusion layer region 5. Drain diffusion layer region 4. A commonly used method is to arrange the gate electrodes 3 concentrically to prevent electric field concentration from occurring at a corner of the drain diffusion layer region.

However, although this method is suitable for use in single MO3 type FETs and MIs type semiconductor integrated circuit devices with relatively simple circuit configurations and low integration, it reduces the area occupied by the elements and the layout efficiency. Therefore, there is a problem that it is not suitable for a MIS type semiconductor device with a complicated circuit configuration and a high degree of integration.

An object of the present invention is to prevent breakdown from occurring due to electric field concentration at a part of the channel-side corner of the drain region when the gate, source, and substrate terminals are fixed at ground potential and the potential of the drain terminal is raised. Few Mis
An object of the present invention is to provide a method for manufacturing a type semiconductor device.

[! ! Means for Solving Problem 1] In order to solve the above problem, the present invention forms a drain region in a self-aligned manner by diffusion of impurities using a thick selective oxidation region and a gate electrode on a thin insulating film as a mask. In this case, the angle at which the periphery of the selective oxide film region and the periphery of the gate electrode intersect is an obtuse angle on the drain side.

[Effect]

By making the angle at which the periphery of the selective oxide film region and the periphery of the gate electrode intersect at an obtuse angle on the drain side, the angle at the channel-side corner of the drain diffusion layer region becomes an obtuse angle, making it possible to prevent electric field concentration. As a result, even in a miniaturized MIS type semiconductor device, it is possible to prevent a decrease in breakdown voltage and a decrease in reliability due to electric field concentration in a part of the channel side corner of the drain diffusion layer region.

〔Example〕

FIG. 1(a), (bl is M according to two embodiments of the present invention)
This is a plan view of an O8 type FET, and the same parts as in FIGS. 2 and 3 are given the same reference numerals. In the embodiment shown in FIG. 1 (al), the selective oxidation II!l opening pattern 2 formed by the LOCO3 method has a funnel shape in which a large rectangle and a small rectangle are connected by a diagonal side of 45''. The gate electrode 3 is provided on the oblique side of this funnel-shaped connection. That is, the intersection angle θ between the LOCO8 film opening pattern 2 and the periphery of the gate electrode 3 on the drain side is 135°. , a drain region 4 formed by impurity diffusion using the LOCO3 film l and the gate electrode 3 as a mask.
The channel side corner part 6 has an angle of 135°, and electric field concentration is less likely to occur compared to the conventional example of 90" shown in Part 3). As a result, the drain breakdown voltage is improved, It is also possible to prevent a decrease in @conductivity due to the generation of hot carriers.Also, according to this embodiment, unlike the concentric arrangement method shown in FIG. It does not cause any deterioration.

In the embodiment shown in Part 1), the opening pattern 2 of LOGO3III is rectangular, and the gate electrode 3 is bent by 45 degrees in the shape of a square, so that the intersection of the opening pattern 2 and the peripheral edge of the gate electrode 3 on the drain side is By setting the angle θ to 1356, the same effect as in FIG. 1 ia) can be obtained regarding prevention of power concentration in the corner part 6.

〔Effect of the invention〕

In the present invention, the periphery of the selective oxide film pattern used as a mask for forming the drain region by diffusion intersects the periphery of the gate electrode at an obtuse angle. A portion of the corner was also made obtuse to prevent power concentration at that portion, and a Mis-type semiconductor device was obtained with little reduction in breakdown voltage or reliability.

[Brief explanation of the drawing]

FIG. 1 (♂l, (bl is M according to two embodiments of the present invention)
The plan view of each O8 type FET, Figure 2 is the conventional 0MO
Figure 3 (5) shows the mechanism of electric field concentration in a part of the channel-side corner of the drain region of a type 3 FET. FIG. 4 is a plan view of another conventional MO3 type FET. 1: LOGO5 selective oxide film, 2: LOCO3 film opening pattern, 3: Gate bridge, 4 Nidrain region,
5: Source area. Figure 1 Figure 2

Claims (1)

[Claims] (1) When forming a drain region in a self-aligned manner by diffusion of impurities using a thick selective oxidation region and a gate electrode on a thin insulating film as a mask, the angle at which the periphery of the selective oxide film region intersects the periphery of the gate electrode is determined. A method for manufacturing an MIS type semiconductor device, characterized in that the angle is made obtuse on the drain side.