JPS6042867A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6042867A JPS6042867A JP15098183A JP15098183A JPS6042867A JP S6042867 A JPS6042867 A JP S6042867A JP 15098183 A JP15098183 A JP 15098183A JP 15098183 A JP15098183 A JP 15098183A JP S6042867 A JPS6042867 A JP S6042867A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- electrode
- type
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 4
- 241001092070 Eriobotrya Species 0.000 claims 1
- 235000009008 Eriobotrya japonica Nutrition 0.000 claims 1
- 239000002245 particle Substances 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 abstract description 5
- 239000000956 alloy Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 230000002265 prevention Effects 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- 244000201986 Cassia tora Species 0.000 description 1
- 206010028980 Neoplasm Diseases 0.000 description 1
- 101150089174 PTST gene Proteins 0.000 description 1
- 208000002564 X-linked cardiac valvular dysplasia Diseases 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 201000011510 cancer Diseases 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 210000002468 fat body Anatomy 0.000 description 1
- 150000002484 inorganic compounds Chemical class 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- NCAIGTHBQTXTLR-UHFFFAOYSA-N phentermine hydrochloride Chemical compound [Cl-].CC(C)([NH3+])CC1=CC=CC=C1 NCAIGTHBQTXTLR-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000007127 saponification reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に関し、特にショットキー接合でソ
ース、ドレイン領域を形成したＭＯ３半導体装置に係る
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to an MO3 semiconductor device in which source and drain regions are formed by Schottky junctions.
ＭＯ８）ランジスメはチャネル長が短かくなるに従い、
ソース、ドレイン領域の不ＡＪヒ物が横方向（基板の平
面方向）へ延びることによる影暫が生じ、設＝ｔ した
マスクのダート長よシも実効チャネル長が短かくなシ、
いわゆるショートチャネル効果が決われる。MO8) As the channel length becomes shorter,
A shadow is caused by the AJ defects in the source and drain regions extending in the lateral direction (in the planar direction of the substrate), and the effective channel length is shorter than the dart length of the set mask.
The so-called short channel effect is determined.
上記不純物の横方向への拡散はｎチャネルＭＯ８）ラン
ジスタよシもｐナヤネルＭＯ８Ｉ−ランノスタの力が大
きい。これは一般にｎチャネルＭＯ８）ランノスタの不
純物として用いられている砒累（Ａｓ）よシもｐチャネ
ルＡ（Ｏ８）ンンノスタの不純物として用いられている
ポロン（Ｂ）の方が拡散係数か大きいｆｃめである。The lateral diffusion of the impurity has a larger force than the n-channel MO8 transistor and the p-channel MO8I transistor. This is because poron (B), which is generally used as an impurity for p-channel A (O8) lannostar, has a higher diffusion coefficient than arsenic (As), which is generally used as an impurity for n-channel MO8) lannostar. be.
そこで、特にｐチャネルＭＯ８）ランソスタのショート
チャネル効果を抑制するノこめに、ショットキー接合で
ソース、ドレイン領域をＪし成したものが提案され・て
いる（例えは、１９８１゜ＩＥＤＭ’、 Ｐ、３６７〜
３７０ 、 ” ５ｃｈｏｔｔｋｙ ＭＯ８ＦＥＴｆｏ
ｒ ＶＬＳＩ ” ； １９８２ ｅ Ｓｙｍｐｏｓｉ
ｕｍ ｏｎ ＶＬＳＩｔｅｃｈｎｏｌ゛ｏｇｙ ａ Ｐ
＠６〜？ 、 −Ｌａｔｃｈ −、ｕｐ ｆｒｅｅＣＭ
Ｏ８ｂｙ ５ｃｈｏｔｔｋｙ ｂａｒｒｉｅｒ ｔｅｃ
ｈｎｏｌｏｇｙ、つ・こうしたＭＯＳトランジスタにお
いては、ン了ス。Therefore, in order to suppress the short channel effect of the p-channel MO8) run source, it has been proposed to form the source and drain regions with Schottky junctions (for example, 1981゜IEDM', P, 367～
370,” 5chottky MO8FETfo
r VLSI”; 1982 e Symposia
um on VLSI technology aP
@6~? , -Latch-, up freeCM
O8by 5chottky barrier tec
In terms of hnology, these MOS transistors have different characteristics.
ドレイン領域のシリコン基板表面からの探さ方向及び横
方向への延びは、ショットキー接合を構成するショット
キーバリアメタルとシリコン基板との合金層（例えばＰ
ｔＳｉ層）の厚み分の半分だけであるので、設計したマ
スクのダート長がＩよぼ保たれる。The drain region extends from the surface of the silicon substrate in the search direction and in the lateral direction through an alloy layer of the Schottky barrier metal and the silicon substrate (for example, P
Since it is only half the thickness of the tSi layer, the designed dart length of the mask can be maintained at approximately I.
上述したよりなショットキー接合でソース。Source with the Schottky junction described above.
ドレイン領域を形成した従来のＭＯＳ）ランジスタをＭ
１図及び第２図を参照して説明する。なお、第２図は第
１図のｎ−ｎ線に沿う断面図である。The conventional MOS) transistor that formed the drain region is
This will be explained with reference to FIGS. 1 and 2. Note that FIG. 2 is a sectional view taken along line nn in FIG. 1.
図中１１ｉｎ型シリコン基板でわシ、このｎ型シリコン
基板１表向には選択鹸化法によりフィールド鹸化膜２が
形成され、このフィールド酸化膜２下の基板１内にはｎ
Ｗフィールド反転防止層３が形成されている。フィール
ドば化膜２によって囲まれた素子領」或にはゲートば化
膜４を介して多結晶シリコンからなるダートａ極５が形
成されている。また、ゲート′電極５両側方の基板１表
面にはショットキーバリアメタル（例えば、ｐｔ、ｗ等
）を蒸着し、低温熱処理（３００〜３５０℃）を施す′
ことによｐ１基板１との間でショットキー接合を形成す
る冶金層（例えばｐｔｓｔ層）からなるソース、ドレイ
ン領域６，７が形成されている。また、全面にＣＶＤ酸
化Ｍ８が堆積されておシ、所定−υｆにコンタクトホー
ル９ｍ、９ｂ、９ｃが開孔さ７している。In the figure, an 11-inch silicon substrate is shown, and a field saponified film 2 is formed on the surface of this n-type silicon substrate 1 by a selective saponification method.
A W field inversion prevention layer 3 is formed. A dirt a-pole 5 made of polycrystalline silicon is formed in the element region surrounded by the field oxide film 2 or via the gate oxide film 4. Further, a Schottky barrier metal (for example, PT, W, etc.) is deposited on the surface of the substrate 1 on both sides of the gate electrode 5, and subjected to low-temperature heat treatment (300 to 350°C).
Source and drain regions 6, 7 are formed of a metallurgical layer (for example a PTST layer) forming a Schottky junction with the p1 substrate 1, for example. Further, CVD oxide M8 is deposited on the entire surface, and contact holes 9m, 9b, and 9c are opened 7 at predetermined positions -υf.
更に、ＣＶＤ酸化膜８上にはコンタクトホール９ ｍ
＊ Ｌｂ ＠ ９ Ｃを介してそれぞれソース、ドレイ
ン領域６，７及びゲート′Ｉ４Ｌ他５と接続する′−極
配ｆＪＪ １０ ＆ ＊ １０ ｂ 、 １０ ｃがｔ
ｅｗさｉしている。Furthermore, a contact hole 9m is formed on the CVD oxide film 8.
* Lb @ 9 C connects to the source, drain regions 6, 7 and gate 'I4L and other 5, respectively'-polar wiring fJJ 10 & * 10 b, 10 c are connected to t
I'm doing it.
上記ＭＯ３）ランジスタのゲート電懐５にしきい値電圧
を超える電圧が加わると、ダート′電極５下部の基板１
表面にｐｉｉ反転層が形成される。When a voltage exceeding the threshold voltage is applied to the gate electrode 5 of the above MO3) transistor, the substrate 1 under the dart' electrode 5
A pii inversion layer is formed on the surface.
この反転Ｊａはソース、ドレイン領域６，１の端部にま
で拡がシ、これらを構成する合金ｌ−に接触する。反転
鳩は比較的濃度の商いｐ型であるので、ソース、ドレイ
ン領域６，７を構成するａ金１−とはショットキーバリ
アを形成せず、抵抗接触（オーミック接触）となる。This inversion Ja extends to the ends of the source and drain regions 6 and 1, and comes into contact with the alloy l- constituting these regions. Since the inversion dovetail has a relatively p-type concentration, it does not form a Schottky barrier with the a gold 1- constituting the source and drain regions 6 and 7, but forms a resistive contact (ohmic contact).
上日己ＭＯ８）ランジスタでは前述したようにソース、
ドレイン領域６，２の横方向への延びが少ないため、実
効チャネル長ははげマスクのダート長に等しく、ショー
トチャネル効果を抑制でひる。Kaminichi MO8) In the transistor, as mentioned above, the source,
Since the lateral extension of the drain regions 6 and 2 is small, the effective channel length is equal to the dart length of the bald mask, thereby suppressing the short channel effect.
ところで、一般的にＭＯＳ ）ランジスタでは、フィー
ルド敵化膜２下にｐ型反転層が生じて隣接−したトラン
ジスタと短絡した多、ソース、ドレイン領域の空乏層が
延びて、ｂＩ４接したトランジスタと知略するのを防止
する目的で、フィールド酸化膜２の底面及び側面にｎ型
フィールド反転防止層３を形成している。このフィール
ド反転防止層３の不和ＩＩ物拡散はノロセス工程を容易
にするため、フィールド酸化膜２とセルファライン（自
己整合）で行なうのが一般的である。By the way, in general, in a MOS (MOS) transistor, a p-type inversion layer is formed under the field barrier film 2, and the depletion layer in the source and drain regions short-circuited with the adjacent transistor extends, resulting in a transistor in contact with bI4. In order to prevent this, an n-type field inversion prevention layer 3 is formed on the bottom and side surfaces of the field oxide film 2. In order to facilitate the norocess process, diffusion of the inorganic compound into the field inversion prevention layer 3 is generally carried out in a self-aligned manner with the field oxide film 2.
この場合、ｎ型フィールド反転防止層３の′不細９勿濃
度は１〜３×１０ ｔｍ である。In this case, the n-type field inversion prevention layer 3 has a concentration of 1 to 3×10 tm.
しかしながら、ショットキー縁合ができるｎ型シリコン
基板の最大−塵は１〜２ Ｘ １０’ ７ｃｍ−’程度
であシ、上述したような濃度の１１型フィールド反転防
止層３がソース、ドレイン領域６゜７を構成する合金層
に接触しｆｃ場合には、シ。However, the maximum amount of dust on an n-type silicon substrate that can form a Schottky edge is about 1 to 2 x 10' 7 cm, and the 11-type field inversion prevention layer 3 with the above-mentioned concentration is in the source and drain regions 6. If it comes into contact with the alloy layer constituting ゜7, then fc.
、トキー接合ができなかったシ、接合耐圧が低いものに
なっ′ＩＣシするという欠点がある。However, there are disadvantages in that it is not possible to perform a single-key junction, and the junction breakdown voltage is low, leading to IC failure.
本発明は上記欠点を解消するためにな込れたものであシ
、耐圧の低下等を招く゛こと々くフィールド反転防止層
をセルファラインで形成することができ、ショートチャ
ネル効Ｍ′ｔ−有効に抑ｆｉｉｌｊできる牛尋体装置を
提供−〜ようとするものである。The present invention has been developed to solve the above-mentioned drawbacks, and it is possible to form a field reversal prevention layer with a self-line, which often causes a decrease in breakdown voltage, etc., and the short channel effect M't- It is an object of the present invention to provide a cow fat body device that can effectively suppress cancer.
本発明の＃−導体装飯は、第１寺電型（例えばｎ ｕ
）の半４体基板に、ショットキー接合で形成されＰｃン
ース、ドレイン領域をｆ；’＝、ｙｙだ半導体装１５（
例えばｐナヤ不ルＭＯ８）ランソスタ）にお・いて、ダ
ート電極下ｈＩＳ以外の素子分喘絶縁膜（ンイールド臥
化族）の周囲の基板中に第２導′Ｉ■帖（ｐ型）の不純
物領域を形成したことを特ｆ改とするものである。The #-conductor arrangement of the present invention is of the first type (for example, n u
), the semiconductor device 15 (
For example, in the case of a p-type (p-type) impurity in the substrate around the insulating film (n-yield) for elements other than the hIS under the dirt electrode. The special feature is that the area is formed.
こうした半導体装置によれば、ショットキー接合で形成
されたソース、ドレイン領域と、素子分離絶に＝ｙ、Ｍ
下の反転防止層か接触することがないので、ショットキ
ー接合の耐圧劣化等の問題が生じることがなく、ショー
トチャネル効果を有効に抑制することができる。According to such a semiconductor device, the source and drain regions formed by the Schottky junction and the element isolation are completely isolated from each other.
Since there is no contact with the underlying inversion prevention layer, problems such as deterioration of the breakdown voltage of the Schottky junction do not occur, and short channel effects can be effectively suppressed.
以下、不発ゆ」の実施例金泥３図及び第４図をβＨして
説明する。なお、紀４図は第３図の■−ＩＶ緑に沿う断
面図である。また、既述した第１図及び第２図と同一の
領域には同−社号を付して説明を省略する。Hereinafter, the example gold paint of "Unexploded Yuu" will be explained using βH as shown in FIGS. 3 and 4. It should be noted that Figure 4 is a cross-sectional view taken along the green line ■-IV in Figure 3. Further, the same areas as those in FIG. 1 and FIG. 2 already described are given the same company name and the explanation thereof will be omitted.
第３図及び第４図゛図示のｐチャネルＭＱＳ）ランジス
タは、ダート電極５下部以外のフィールド酸化Ｍ２の周
囲の基板Ｉ中にｐ型不縄物領域１１．１１を・形成した
ほかは、第１図及び第２図図示の従来のｐチャネルＭＯ
８）ランノスタと同様な構造を有している。The p-channel MQS transistor shown in FIGS. 3 and 4 has a p-type impurity region 11.11 formed in the substrate I around the field oxide M2 other than the lower part of the dirt electrode 5. Conventional p-channel MO shown in FIGS. 1 and 2
8) It has a similar structure to Rannostar.
前記ｐムｙ不純物領域１１．１１は、多結晶シリコン膜
、をパターニングすることにょシダート電極５を形成し
た後、写真蝕刻法にょルホトレジストパターンを形成し
、これをマスクとしてｓｔａンをイオン注入し、更に、
前記ホトレジストノリ−ンを除去した後、熱処理するこ
とにょシ形成することができる。The p-y impurity region 11.11 is formed by patterning a polycrystalline silicon film to form a radiation electrode 5, then forming a photoresist pattern by photolithography, and using this as a mask, ion-implanting STAN. , furthermore,
After the photoresist layer is removed, it can be formed by heat treatment.
しかして、上記ｐチャネルＭＯ８）ランノスタによれば
、ソース、ドレイン領域６．７を禍成する合金層（例え
ばＰｔＳｉ層）とｎ型フィール１゛反転防止層３，３と
の間にｐ型不純物領域１１゜１１が介在しているので、
両者が＋ｂｍすることはなく、ｎｍフィールド反反転防
止層、３の不純物ａ腹が向くで・もショットキル接合の
耐圧が劣化することはない。すなわち、ショットキー接
も自体の耐圧はＦＩ型シリコン基板１の不純物磯度によ
って決定される耐圧となるため、高い降伏′旺圧をイｊ
する。したがって、ｎｔ１１フィールド反転防止Ｊ奮３
，３を従来通シフイールド鹸化膜２とセルフアンインで
形成しても耐圧の劣化ヲ招くことかなく、ショートチャ
ネル効果を１効に防止することができる。According to the above-mentioned p-channel MO8) Lannostar, p-type impurity is added between the alloy layer (for example, PtSi layer) forming the source and drain regions 6.7 and the n-type field 1' inversion prevention layers 3, 3. Since the region 11°11 is interposed,
Both do not increase +bm, and the breakdown voltage of the shotkill junction does not deteriorate even if the nano-field anti-inversion layer and the impurity a-antino of 3 are oriented. In other words, the breakdown voltage of the Schottky contact itself is determined by the degree of impurity in the FI type silicon substrate 1, so a high breakdown voltage is not required.
do. Therefore, nt11 field reversal prevention
.
なお、本発明の半導体装置は第３図及び第４図に示し７
１ｃＪ＠造に限らず、例えは第５図に示す構造でもよい
。第５図図示のｐチャネルＭＯＳトランジスタはダート
電極５′を、フィールド酸化膜２と交わる近傍の部分の
寸法を中央部の寸法よシ大きくしたものである。The semiconductor device of the present invention is shown in FIGS. 3 and 4.
The structure is not limited to the 1cJ@ structure, and for example, the structure shown in FIG. 5 may be used. The p-channel MOS transistor shown in FIG. 5 has a dirt electrode 5' in which the size of the portion near where it intersects with the field oxide film 2 is larger than the size of the center portion.
゛こりしたｐチャネルＭＯ８）ランジスタによれは、ケ
゛−ト電極５′とフィールド酸化膜２との交わる部分近
傍でｐ型不純物領域１１．ＩＩの横方間の拡散により実
効チャネル長が短かくなるのを防止することができる。Due to the damaged p-channel MO transistor (8), the p-type impurity region 11. It is possible to prevent the effective channel length from becoming short due to the lateral diffusion of II.
特に、ｐ型不純物領域１１．１１−の不純物娘度が高く
、横方向の拡散が大きい一合に有効である。This is particularly effective in cases where the p-type impurity regions 11, 11- have a high impurity degree and a large amount of lateral diffusion.
また、本発明の半導体装置は上ｍｌ実施例の如くｐチャ
ネルＭＯ８）ランジスタに１狐らず、ｎチャネルＭＯＳ
トラ／ノスタ、０ＭＯ８等にも１万Ｊ様に適用できる。In addition, the semiconductor device of the present invention does not have a p-channel MOS transistor as in the above embodiment, but an n-channel MOS transistor.
It can also be applied to Tora/Nosta, 0MO8, etc. for 10,000J.
以上詳述した如く、本ｉｈ明の半導体装Ｕによれは、Ｍ
ＯＳトランジスタ等の接合耐圧の劣化を・招くことなく
、ショートチャネル効果を１力止することができ、ひい
ては素子の微力１ｕ化を達Ｊ戊できる等顕著な効果を奏
するものである。As detailed above, the semiconductor device U of the present invention has M
This has remarkable effects such as being able to temporarily stop the short channel effect without causing deterioration of the junction breakdown voltage of the OS transistor, etc., and further achieving the miniaturization of the device to 1 μ.
第１図はショットキー接合でソース、ドレイン領域が形
成された従来のｐチャネルＭＯ８＋・ランジスタの平面
図、第２図ｉＩｊ：第１図のＩＩ −ＩＩ ｉｂ＋’ｉ
に沿う断面図、第３図は本発明の実施例におけるｐチャ
ネル１〜ｆＯ８ｌ−ランノスクの平面図、第４図は第３
図の■−■縁に沿う−「面図、第５図は本）ら明の他の
実施例におけるｐチャネルＭＯＳトランジスタの平面図
である。
１・・・ｎ型シリコン基板、２・・・フィールド敗化膜
、３・・・ｎ型フィールド反転防止層、４・・・ゲート
敲化収、５．５′・・・ダート電極、６，７・・・ソー
ス、ドレイン領域、８・・・ＣＶＤ１化膜、−９ａ ＋
９ｂ １９ ｃ ”’コンタクトホール、１０ ａ ＋
１０ｂ＊１０ｃ・・・寛憾配餓、１１・・・ｐ型不純
物領域０出願人代理人 弁理士 鈴 江 武 が第１図
第２図
第３図Figure 1 is a plan view of a conventional p-channel MO8+ transistor with source and drain regions formed by Schottky junctions, Figure 2 iIj: II-II ib+'i in Figure 1
3 is a plan view of p-channels 1 to fO8l-lannosk in the embodiment of the present invention, and FIG.
5 is a plan view of a p-channel MOS transistor in another embodiment of the present invention along the edge of the figure. 1... n-type silicon substrate, 2... Field destruction film, 3... N-type field inversion prevention layer, 4... Gate ablation layer, 5.5'... Dirt electrode, 6, 7... Source, drain region, 8... CVD1 film, -9a +
9b 19 c ”' Contact hole, 10 a +
10b*10c...Relaxation, 11...P-type impurity region 0 Applicant's agent, patent attorney Takeshi Suzue, is shown in Figure 1, Figure 2, and Figure 3.
Claims (2)
び該；！≦子分離絶縁股下に形成された第１寺Ｉａ型の
反転防止層によって囲まれた素子領域に、互いに′電気
的に分離され、ショットキー接合でノー成されたンース
、ドレイン領域を設け、これらソース、ドレイン領域向
の基板上にダート杷琢膜を介してダート電極を設けた″
Ｐ専鉢体装置１１おいて、前記ダート′嵯極下部以外の
累子分−ト杷程１１にの周囲の基板中に第２専′亀型の
不純物鎖板を形成し／くことを特徴とする半導体に置。(1) An element isolation insulating film on the surface of a first conductivity type semiconductor substrate and the;! ≦In the device region surrounded by the first temple Ia type anti-inversion layer formed under the child isolation insulating crotch, source and drain regions electrically isolated from each other and formed by a Schottky junction are provided. A dart electrode is provided on the substrate facing the source and drain regions via a dart loquat film.
The P-type pot body device 11 is characterized in that a second specialized tortoise-shaped impurity chain plate is formed in the substrate around the particle diameter 11 other than the extreme lower part of the dirt plate. Placed in semiconductors.
の部分の寸法をり゛−ト篭極中央ｉｂの寸法よシ大きく
したとを特徴とする特許請求の範囲第１項記載の半導体
装置。(2) Claim 1, characterized in that the dimension of the portion of the ri-1/' electrode in the vicinity of where it intersects with the element branch insulating film is made larger than the dimension of the center ib of the ri-1/' electrode. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15098183A JPS6042867A (en) | 1983-08-19 | 1983-08-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15098183A JPS6042867A (en) | 1983-08-19 | 1983-08-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6042867A true JPS6042867A (en) | 1985-03-07 |
Family
ID=15508674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15098183A Pending JPS6042867A (en) | 1983-08-19 | 1983-08-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6042867A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02170437A (en) * | 1988-12-22 | 1990-07-02 | Fuji Electric Co Ltd | Manufacture of mis-type semiconductor device |
| JPH0330476A (en) * | 1989-06-28 | 1991-02-08 | Matsushita Electron Corp | Mis transistor and protective circuit provided therewith |
| US5306082A (en) * | 1992-06-12 | 1994-04-26 | James Karlin | Appliance doors and panels |
| US5928599A (en) * | 1995-06-01 | 1999-07-27 | Batesville Services, Inc. | Method of forming articles of manufacture of various shapes including undercuts therein with generic tool |
-
1983
- 1983-08-19 JP JP15098183A patent/JPS6042867A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02170437A (en) * | 1988-12-22 | 1990-07-02 | Fuji Electric Co Ltd | Manufacture of mis-type semiconductor device |
| JPH0330476A (en) * | 1989-06-28 | 1991-02-08 | Matsushita Electron Corp | Mis transistor and protective circuit provided therewith |
| US5306082A (en) * | 1992-06-12 | 1994-04-26 | James Karlin | Appliance doors and panels |
| US5928599A (en) * | 1995-06-01 | 1999-07-27 | Batesville Services, Inc. | Method of forming articles of manufacture of various shapes including undercuts therein with generic tool |
| US6530134B1 (en) | 1995-06-01 | 2003-03-11 | Batesville Services, Inc. | Molded casket shell and trim therefore |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3229012B2 (en) | Method for manufacturing semiconductor device | |
| JPS63102264A (en) | Thin film semiconductor device | |
| US4426766A (en) | Method of fabricating high density high breakdown voltage CMOS devices | |
| JPS6042867A (en) | Semiconductor device | |
| US4142197A (en) | Drain extensions for closed COS/MOS logic devices | |
| JP3000739B2 (en) | Vertical MOS field effect transistor and method of manufacturing the same | |
| US3518750A (en) | Method of manufacturing a misfet | |
| GB2152283A (en) | Gate protection arrangement for a semiconductor device | |
| US5181094A (en) | Complementary semiconductor device having improved device isolating region | |
| JPS59130465A (en) | Manufacture of metal insulator semiconductor device | |
| US3936862A (en) | MISFET and method of manufacture | |
| JPS6119174A (en) | Semiconductor device | |
| JPS62248256A (en) | Semiconductor device | |
| US4528581A (en) | High density CMOS devices with conductively interconnected wells | |
| JP3350170B2 (en) | Power MOS type semiconductor device and method of manufacturing the same | |
| JPS6247151A (en) | Formation of mutual connection on substrate | |
| JPS6058674A (en) | Mos type transistor | |
| JP3095912B2 (en) | Semiconductor integrated circuit device | |
| JPS594083A (en) | Manufacture of semiconductor device | |
| TW200425472A (en) | Semiconductor device | |
| JPS5918676A (en) | Semiconductor integrated circuit | |
| JPS63200559A (en) | Semiconductor integrated circuit device | |
| JP2968640B2 (en) | Semiconductor device | |
| JP3052019B2 (en) | Integrated circuit device | |
| JPS5931224B2 (en) | semiconductor equipment |