JP2005217146A - 平行導電回路シート及び平行導電回路シートを用いた電子回路 - Google Patents
平行導電回路シート及び平行導電回路シートを用いた電子回路 Download PDFInfo
- Publication number
- JP2005217146A JP2005217146A JP2004021382A JP2004021382A JP2005217146A JP 2005217146 A JP2005217146 A JP 2005217146A JP 2004021382 A JP2004021382 A JP 2004021382A JP 2004021382 A JP2004021382 A JP 2004021382A JP 2005217146 A JP2005217146 A JP 2005217146A
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- conductive circuit
- parallel
- sheet
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Combinations Of Printed Boards (AREA)
- Wire Bonding (AREA)
- Non-Insulated Conductors (AREA)
- Insulated Conductors (AREA)
- Structure Of Printed Boards (AREA)
Abstract
【解決手段】 一様な厚さを有するシート状の絶縁層5と、この絶縁層5の面上に形成される導電性材料からなる導電回路3とで構成される平行導電回路シート1であって、この導電回路3を平行に複数本配置すると共に、導電回路3の間隔を少なくとも接続対象であるプリント基板7aの配線間隔da以下、若しくはIC部品端子の端子間隔db以下とすることで、プリント基板7a又はIC部品の端子1本に対して複数本の導電回路3を接続することができる。これにより狭幅な配線接続を可能とし、更に高精度な実装能力が求められていた微細な配線接続及びIC実装を容易に行うことができる。
【選択図】 図1
Description
「月間Semiconductor World」、1998年9月号、p157−158、「2.ACF接続」
3…導電回路
5…絶縁層
7a,7b…プリント基板
9…導電配線
13a,13b…導電配線
103…ACF
105…導電性フィラー
107…基板
109…配線
111…半導体チップ
113…端子
Claims (4)
- 対向配置された接続対象基板上に設けられる配線間を連結接続する平行導電回路シートであって、
一様な厚さを有するシート状の絶縁層と、該絶縁層の面上に形成される導電回路とで構成され、前記導電回路は前記絶縁層面上に平行且つ複数本設けられ、該導電回路の幅は少なくとも接続対象基板上に設けられる配線の配線間隔以下、若しくは電子部品端子の端子間隔以下であること特徴とする平行導電回路シート。 - 前記導電回路の幅は、前記接続対象基板上に設けられる配線間隔の1/2以下、若しくは電子部品端子の端子間隔の1/2以下であることを特徴とする請求項1記載の平行導電回路シート。
- 請求項1又は2記載の平行導電回路シートと、所定の配線間隔で形成された複数本の導電配線を備える第1基板と、所定の配線間隔で形成された複数本の導電配線を備える第2基板とで構成され、前記第1及び第2基板の導電配線間を前記平行導電回路シートに設けられる導電回路を用いて接続することを特徴とする平行導電回路シートを用いた電子回路。
- 請求項1又は2記載の平行導電回路シートと、所定の配線間隔で形成された複数本の導電配線を備える基板と、所定の配線間隔で形成された複数本の端子を備える電子部品とで構成され、前記基板の導電配線と前記電子部品の端子間を前記平行導電回路シートに設けられる導電回路を用いて接続することを特徴とする平行導電回路シートを用いた電子回路。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004021382A JP4430419B2 (ja) | 2004-01-29 | 2004-01-29 | 平行導電回路シートを用いた電子回路及びその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004021382A JP4430419B2 (ja) | 2004-01-29 | 2004-01-29 | 平行導電回路シートを用いた電子回路及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005217146A true JP2005217146A (ja) | 2005-08-11 |
JP4430419B2 JP4430419B2 (ja) | 2010-03-10 |
Family
ID=34905045
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004021382A Expired - Fee Related JP4430419B2 (ja) | 2004-01-29 | 2004-01-29 | 平行導電回路シートを用いた電子回路及びその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4430419B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7460690B2 (ja) | 2021-03-09 | 2024-04-02 | グーグル エルエルシー | 低温用途のためのフレキシブル配線 |
-
2004
- 2004-01-29 JP JP2004021382A patent/JP4430419B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7460690B2 (ja) | 2021-03-09 | 2024-04-02 | グーグル エルエルシー | 低温用途のためのフレキシブル配線 |
Also Published As
Publication number | Publication date |
---|---|
JP4430419B2 (ja) | 2010-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10515918B2 (en) | Methods of fluxless micro-piercing of solder balls, and resulting devices | |
EP0653789A2 (en) | Electronic package structure and method of making same | |
JP2007088055A (ja) | フレキシブルプリント配線板およびその製造方法 | |
US8102664B2 (en) | Printed circuit board and method of manufacturing the same | |
JP2004296562A (ja) | 電子部品内蔵基板及びその製造方法 | |
JP2007019507A (ja) | 基板組立体製造方法 | |
JP4430419B2 (ja) | 平行導電回路シートを用いた電子回路及びその製造方法 | |
JP4318895B2 (ja) | 3次元モジュール、3次元モジュールの製造方法 | |
JP3946200B2 (ja) | 電子部品の実装方法 | |
CN112825600A (zh) | 双面铜的软性电路板及其布线结构 | |
US9673063B2 (en) | Terminations | |
KR20020069675A (ko) | 연성인쇄회로기판의 접합방법 | |
JP2001156416A (ja) | フレキシブル配線基板の接続構造 | |
JP2010010611A (ja) | プリント回路板及び電子機器 | |
JP2009071159A (ja) | フレキシブル配線基板及びベアチップ実装方法 | |
JP2009194058A (ja) | 電気接続装置 | |
JP3026205B1 (ja) | 電子回路装置及び表示装置 | |
KR100986294B1 (ko) | 인쇄회로기판의 제조방법 | |
JP2006332465A (ja) | チップオンフィルム半導体装置 | |
JP2005294615A (ja) | 配線基板 | |
JPH10144728A (ja) | 表面実装部品及びこれを用いたプリント配線板 | |
JP2001053410A (ja) | チップ実装構造 | |
JP3404275B2 (ja) | 複数基板からなるモジュール及びその製造方法 | |
JPH11150150A (ja) | 半導体搭載用基板とその製造方法及び半導体チップの実装方法 | |
JPH0751794Y2 (ja) | 半導体の実装構造 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20061128 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090820 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090901 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091020 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20091201 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091217 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121225 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121225 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131225 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |