JP2005191576A - 半導体デバイス及びその製造方法 - Google Patents
半導体デバイス及びその製造方法 Download PDFInfo
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- JP2005191576A JP2005191576A JP2004374418A JP2004374418A JP2005191576A JP 2005191576 A JP2005191576 A JP 2005191576A JP 2004374418 A JP2004374418 A JP 2004374418A JP 2004374418 A JP2004374418 A JP 2004374418A JP 2005191576 A JP2005191576 A JP 2005191576A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000000034 method Methods 0.000 title claims description 14
- 239000002019 doping agent Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000009792 diffusion process Methods 0.000 claims abstract description 31
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 230000002040 relaxant effect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 9
- 229910017052 cobalt Inorganic materials 0.000 description 6
- 239000010941 cobalt Substances 0.000 description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000005684 electric field Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】 本発明による半導体デバイスは、半導体基体上にあって、下側に位置するゲート絶縁層を有するゲート電極と、半導体基体内において互いに離間し、ゲート電極と位置合わせされている1対の軽度にドープされた領域と、半導体基体内において互いに離間し、1対の軽度にドープされた領域とそれぞれ部分的に重なっている1対の重度にドープされた領域と、1対の軽度にドープされた領域を囲っている1対の拡散ソース/ドレイン領域とを含む。
【選択図】 図2
Description
12、22、32 ゲート酸化物
13、23、33 ゲート電極
14 DDD領域
24、34 LDD領域
15、25、35 ソース/ドレイン領域
16、26、36 フィールド酸化物層
17、27、37 シリサイド層
18、28、38 スペーサ
19、29、39 拡散ソース/ドレイン領域
Claims (9)
- 半導体デバイスであって、
上記半導体基体上にあって下側に位置するゲート絶縁層を有するゲート電極と、
上記半導体基体内において互いに離間し、上記ゲート電極と位置合わせされている1対の軽度にドープされた領域と、
上記半導体基体内において互いに離間し、上記1対の軽度にドープされた領域とそれぞれ部分的に重なっている1対の重度にドープされた領域と、
上記1対の軽度にドープされた領域を囲っている1対の拡散ソース/ドレイン領域と、を含むことを特徴とする半導体デバイス。 - 上記1対の拡散ソース/ドレイン領域は、付加的なドーパントを用いて重度にドープすることを特徴とする請求項1に記載の半導体デバイス。
- 上記付加的なドーパントは、リン(P)であることを特徴とする請求項2に記載の半導体デバイス。
- 上記軽度にドープされた領域の接合プロファイルは、付加的なドーパントの横方向拡散によって勾配緩和されていることを特徴とする請求項2に記載の半導体デバイス。
- 半導体デバイスの製造方法であって、
下側にゲート絶縁層を有するゲート電極を半導体基体上に形成させるステップと、
半導体基体内において互いに離間し、上記ゲート電極と位置合わせされている1対の軽度にドープされた領域を形成させるステップと、
上記ゲート電極の側壁にスペーサを形成させるステップと、
上記半導体基体内において互いに離間し、上記1対の軽度にドープされた領域とそれぞれ部分的に重なっている1対の重度にドープされた領域を形成させるステップと、
上記重度にドープされた領域を付加的なドーパントを用いて重度にドープするステップと、
上記付加的なドーパントを上記軽度にドープされた領域に向かって横方向に拡散させ、上記1対の軽度にドープされた領域を囲っている1対の拡散ソース/ドレイン領域を形成させるステップと、
を含むことを特徴とする方法。 - 上記付加的なドーパントは、リン(P)であることを特徴とする請求項5に記載の方法。
- 上記付加的なドーパントを拡散させ、上記1対の軽度にドープされた領域を囲むことによって二重拡散ドレイン構造(DDD)を回避することを特徴とする請求項5に記載の方法。
- 上記軽度にドープされた領域の接合プロファイルは、上記付加的なドーパントの横方向拡散によって勾配緩和されることを特徴とする請求項5に記載の方法。
- 上記ゲート電極及び上記1対の重度にドープされた領域上にシリサイド層を形成させるステップを更に含むことを特徴とする請求項5に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020030096991A KR100552808B1 (ko) | 2003-12-24 | 2003-12-24 | 확산 소스/드레인 구조를 갖는 반도체 소자 및 그 제조 방법 |
Publications (1)
Publication Number | Publication Date |
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JP2005191576A true JP2005191576A (ja) | 2005-07-14 |
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Application Number | Title | Priority Date | Filing Date |
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JP2004374418A Pending JP2005191576A (ja) | 2003-12-24 | 2004-12-24 | 半導体デバイス及びその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7368357B2 (ja) |
JP (1) | JP2005191576A (ja) |
KR (1) | KR100552808B1 (ja) |
DE (1) | DE102004063144A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7602017B2 (en) * | 2007-03-13 | 2009-10-13 | Fairchild Semiconductor Corporation | Short channel LV, MV, and HV CMOS devices |
KR20090007053A (ko) * | 2007-07-13 | 2009-01-16 | 매그나칩 반도체 유한회사 | 고전압 소자 및 그 제조방법 |
CN101740392B (zh) * | 2008-11-27 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Ldmos晶体管、半导体器件及其制造方法 |
US7977743B2 (en) * | 2009-02-25 | 2011-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alternating-doping profile for source/drain of a FET |
US9117843B2 (en) | 2011-09-14 | 2015-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device with engineered epitaxial region and methods of making same |
KR102230198B1 (ko) | 2014-09-23 | 2021-03-19 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
KR102259080B1 (ko) | 2014-09-23 | 2021-06-03 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
US10636873B2 (en) * | 2017-11-22 | 2020-04-28 | Vanguard International Semiconductor Corporation | Method of fabricating semiconductor device |
CN114420760B (zh) * | 2022-03-28 | 2022-05-31 | 北京芯可鉴科技有限公司 | 横向双扩散场效应晶体管、制作方法、芯片及电路 |
CN115020343B (zh) * | 2022-07-19 | 2023-01-31 | 合肥晶合集成电路股份有限公司 | 一种半导体器件的制作方法 |
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US5171700A (en) * | 1991-04-01 | 1992-12-15 | Sgs-Thomson Microelectronics, Inc. | Field effect transistor structure and method |
WO1994027325A1 (en) * | 1993-05-07 | 1994-11-24 | Vlsi Technology, Inc. | Integrated circuit structure and method |
US5675166A (en) * | 1995-07-07 | 1997-10-07 | Motorola, Inc. | FET with stable threshold voltage and method of manufacturing the same |
US6300662B1 (en) | 1996-10-01 | 2001-10-09 | Analog Devices, Inc. | Electronic programmable read-only-memory including a charge storage capacitor coupled to the gate electrode |
US6693001B2 (en) * | 1997-03-14 | 2004-02-17 | Renesas Technology Corporation | Process for producing semiconductor integrated circuit device |
US5952693A (en) * | 1997-09-05 | 1999-09-14 | Advanced Micro Devices, Inc. | CMOS semiconductor device comprising graded junctions with reduced junction capacitance |
US6353245B1 (en) * | 1998-04-09 | 2002-03-05 | Texas Instruments Incorporated | Body-tied-to-source partially depleted SOI MOSFET |
US6180464B1 (en) * | 1998-11-24 | 2001-01-30 | Advanced Micro Devices, Inc. | Metal oxide semiconductor device with localized laterally doped channel |
JP3911585B2 (ja) * | 1999-05-18 | 2007-05-09 | 富士通株式会社 | 半導体装置およびその製造方法 |
KR100361533B1 (en) | 2001-03-29 | 2002-11-23 | Hynix Semiconductor Inc | Method for fabricating semiconductor device |
US7274076B2 (en) * | 2003-10-20 | 2007-09-25 | Micron Technology, Inc. | Threshold voltage adjustment for long channel transistors |
-
2003
- 2003-12-24 KR KR1020030096991A patent/KR100552808B1/ko not_active IP Right Cessation
-
2004
- 2004-12-22 DE DE102004063144A patent/DE102004063144A1/de not_active Withdrawn
- 2004-12-23 US US11/021,056 patent/US7368357B2/en active Active
- 2004-12-24 JP JP2004374418A patent/JP2005191576A/ja active Pending
-
2005
- 2005-09-20 US US11/230,697 patent/US20060138567A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
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US7368357B2 (en) | 2008-05-06 |
US20050184335A1 (en) | 2005-08-25 |
US20060138567A1 (en) | 2006-06-29 |
KR100552808B1 (ko) | 2006-02-20 |
DE102004063144A1 (de) | 2005-08-04 |
KR20050065221A (ko) | 2005-06-29 |
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