JP2005150685A5 - - Google Patents

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Publication number
JP2005150685A5
JP2005150685A5 JP2004211354A JP2004211354A JP2005150685A5 JP 2005150685 A5 JP2005150685 A5 JP 2005150685A5 JP 2004211354 A JP2004211354 A JP 2004211354A JP 2004211354 A JP2004211354 A JP 2004211354A JP 2005150685 A5 JP2005150685 A5 JP 2005150685A5
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JP
Japan
Prior art keywords
semi
amorphous semiconductor
semiconductor layer
manufacturing
impurity
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Application number
JP2004211354A
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English (en)
Japanese (ja)
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JP4554292B2 (ja
JP2005150685A (ja
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Application filed filed Critical
Priority to JP2004211354A priority Critical patent/JP4554292B2/ja
Priority claimed from JP2004211354A external-priority patent/JP4554292B2/ja
Publication of JP2005150685A publication Critical patent/JP2005150685A/ja
Publication of JP2005150685A5 publication Critical patent/JP2005150685A5/ja
Application granted granted Critical
Publication of JP4554292B2 publication Critical patent/JP4554292B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2004211354A 2003-07-18 2004-07-20 薄膜トランジスタの作製方法 Expired - Fee Related JP4554292B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004211354A JP4554292B2 (ja) 2003-07-18 2004-07-20 薄膜トランジスタの作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2003277144 2003-07-18
JP2003361289 2003-10-21
JP2004211354A JP4554292B2 (ja) 2003-07-18 2004-07-20 薄膜トランジスタの作製方法

Publications (3)

Publication Number Publication Date
JP2005150685A JP2005150685A (ja) 2005-06-09
JP2005150685A5 true JP2005150685A5 (enExample) 2007-06-14
JP4554292B2 JP4554292B2 (ja) 2010-09-29

Family

ID=34704840

Family Applications (1)

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JP2004211354A Expired - Fee Related JP4554292B2 (ja) 2003-07-18 2004-07-20 薄膜トランジスタの作製方法

Country Status (1)

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JP (1) JP4554292B2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8900970B2 (en) * 2006-04-28 2014-12-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device using a flexible substrate
JP5117001B2 (ja) * 2006-07-07 2013-01-09 株式会社ジャパンディスプレイイースト 有機ｅｌ表示装置
US8330887B2 (en) * 2007-07-27 2012-12-11 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic device
JP2009071289A (ja) * 2007-08-17 2009-04-02 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US8101444B2 (en) * 2007-08-17 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
KR101484297B1 (ko) * 2007-08-31 2015-01-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시장치 및 표시장치의 제작방법
US20090141004A1 (en) * 2007-12-03 2009-06-04 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
JP5498711B2 (ja) * 2008-03-01 2014-05-21 株式会社半導体エネルギー研究所 薄膜トランジスタ
JP5518366B2 (ja) * 2008-05-16 2014-06-11 株式会社半導体エネルギー研究所 薄膜トランジスタ
JP5602389B2 (ja) * 2008-05-16 2014-10-08 株式会社半導体エネルギー研究所 薄膜トランジスタ
CN102509736B (zh) 2008-10-24 2015-08-19 株式会社半导体能源研究所 半导体器件和用于制造该半导体器件的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0682839B2 (ja) * 1984-08-21 1994-10-19 セイコー電子工業株式会社 表示用パネルの製造方法
JP3238020B2 (ja) * 1994-09-16 2001-12-10 株式会社東芝 アクティブマトリクス表示装置の製造方法
KR0171984B1 (ko) * 1995-12-11 1999-03-30 김주용 박막 트랜지스터의 자기 정렬 노광 방법
JP2915397B1 (ja) * 1998-05-01 1999-07-05 インターナショナル・ビジネス・マシーンズ・コーポレイション バックチャネル効果を防止する薄膜トランジスタおよびその製造方法
JP2000357797A (ja) * 1999-06-15 2000-12-26 Toshiba Corp 薄膜トランジスタの製造方法
JP3965562B2 (ja) * 2002-04-22 2007-08-29 セイコーエプソン株式会社 デバイスの製造方法、デバイス、電気光学装置及び電子機器

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