JP2005136392A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form multiple sensor elements in a limited amount of area and to reduce an area that the sensor elements occupy and accumulate so that higher output and smaller physical size of a sensor element can be realized in the future. <P>SOLUTION: Higher output and smaller physical size are achieved by integrating an output amplifier circuit composed of TFT having a crystal structure semiconductor film (typically polysilicon film) with a sensor element using an amorphous semiconductor film (typically amorphous silicon film) on a heat-resistant plastic film substrate which can resist temperature at a time of packaging for solder reflow treatment and the like. Sensor elements strong against bending stress can be realized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a sensor element and a circuit including a thin film transistor (hereinafter referred to as TFT) and a method for manufacturing the semiconductor device.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  Conventionally, solid-state imaging devices include a sensor device using a single crystal silicon substrate and a sensor device using an amorphous silicon film.

A feature of the sensor element using the single crystal silicon substrate is that an output amplifier circuit is produced on the single crystal silicon substrate and integrated with the sensor element, thereby enabling high output. However, since the wavelength sensitivity correction filter is necessary, the shape of the packaged finished part is not smart. Further, there is a problem that the sensor element using the single crystal silicon substrate has a large variation.

  On the other hand, the sensor element using an amorphous silicon film is characterized in that the wavelength sensitivity is close to the human eye, so no correction filter such as an infrared light cut filter is required, but the output value of the sensor element is amplified. There is no limit because it is not. Further, since the output value of the sensor element is small, it is easily affected by noise of other signals. The output value of the sensor element depends on the absolute amount (area, thickness, etc.) of the sensor element. Therefore, in order to improve the output value of the sensor element using the amorphous silicon film, it is necessary to increase the area accordingly.

  It is also possible to attach an operational amplifier externally to the sensor element using the amorphous film and amplify the output of the sensor element using the amorphous silicon film, but the number of external parts increases and the sensor circuit becomes large. A new problem occurred.

  Compared with a sensor element using a single crystal silicon substrate, the optical sensitivity of the sensor element using an amorphous film is 1/10 or less. For this reason, when a sensor element using an amorphous film is used in a display device that requires a large area such as a liquid crystal projector, the wiring area of the large area display device becomes longer, which makes it more susceptible to noise. In order to use a sensor element using an amorphous film in a large display device, a wiring shield or the like is required, which increases the cost of the display device.

Further, the present applicant has proposed Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4 regarding a semiconductor device having a sensor element and a circuit formed of TFTs on a glass substrate.
Japanese Patent Laid-Open No. 6-275808 JP 2001-320547 A JP 2002-62856 A JP2002-176162

It is an object of the present invention to form a plurality of elements in a limited area so as to reduce the area occupied by the elements and integrate them in order to further increase the output and size of the sensor element in the future.

For sensor elements using single crystal silicon substrates and sensor elements using amorphous silicon films, the area used for component mounting becomes smaller as the size is reduced. It will be difficult to ensure. When there are few fixed areas and the hardness of the sensor element is high (mechanical strength such as a single crystal silicon substrate or glass substrate), flexural stress is not relaxed when bending stress is applied to the parts. There is a risk of causing the component to be fixed and broken due to this balance.

Therefore, an object of the present invention is to realize a sensor element that is resistant to bending stress.

  The present invention relates to an output amplifying circuit comprising a TFT having a semiconductor film having a crystal structure (typically a polysilicon film) as an active layer on a heat-resistant plastic film substrate that can withstand a temperature during mounting such as solder reflow processing. And a sensor element using an amorphous semiconductor film (typically an amorphous silicon film) are integrated to increase the output and reduce the size. Further, since the optical sensor element and the amplifier circuit are directly connected on the sensor substrate, noise is hardly superimposed. In addition, a sensor element resistant to bending stress can be realized.

  In the light receiving region of the sensor element having a pair of electrodes, the present invention does not provide the first electrode that overlaps the entire light receiving region, but provides the first electrode that overlaps only a part of the light receiving region. A larger amount of light is absorbed by the photoelectric conversion layer. Therefore, most of the light incident on the photoelectric conversion layer does not pass through the first electrode, passes only through the interlayer insulating film, the base insulating film, and the film substrate and reaches the photoelectric conversion layer. Note that the second electrode is provided in the entire light receiving region of the sensor element. In the case where the photoelectric conversion layer has a multilayer structure, when a p-type semiconductor layer or an n-type semiconductor layer is used as a single layer, the p-type semiconductor layer or the n-type semiconductor layer also functions as an electrode. The semiconductor layer and the n-type semiconductor layer are not called a first electrode or a second electrode.

The configuration of the invention disclosed in this specification is as follows.
A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a photoelectric conversion layer made of a semiconductor film having an amorphous structure on the first electrode, and a second electrode on the photoelectric conversion layer,
The amplifier circuit includes a TFT having a semiconductor film having a crystal structure.

  In this specification, a chip having an optical sensor element and an amplifier circuit does not indicate a chip using a semiconductor substrate, but a small piece of a plastic substrate having an optical sensor element and an amplifier circuit. .

  The semiconductor device of the present invention can function as an optical sensor, and light incident on a diode (photodiode) is absorbed by a photoelectric conversion layer to form a photoelectric charge. The amount of photocharge formed by this light depends on the amount of light absorbed by the photoelectric conversion layer. Photoelectric charges formed by light are amplified and detected by a circuit including TFTs.

  As a configuration of the diode in the present invention, a Schottky type in which a photoelectric conversion layer is sandwiched between a first electrode and a second electrode is used. Here, the photoelectric conversion element that converts light into an electrical signal is not limited to the diode having the above-described configuration, and a PIN-type, PN-type diode, an avalanche diode, or the like can also be used.

  For example, as another configuration, the photoelectric conversion layer sandwiched between the first electrode and the second electrode may be a single layer, only an i-type (intrinsic) semiconductor layer, only a p-type semiconductor, or an n-type semiconductor. It may be composed only of. As another configuration, the photoelectric conversion layer sandwiched between the first electrode and the second electrode may be two layers, i-type (intrinsic) semiconductor layer and n-type semiconductor layer, or i-type. (Intrinsic) It may be composed of two layers of a semiconductor layer and a p-type semiconductor layer, or two layers of a p-type semiconductor layer and an n-type semiconductor layer.

  Note that a PIN photodiode includes a pair of electrodes, a p-type semiconductor layer, an n-type semiconductor layer, and an i-type (intrinsic) semiconductor layer sandwiched between the p-type semiconductor layer and the n-type semiconductor layer. Has been.

In addition, the configuration of other inventions is as follows:
A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a p-type amorphous semiconductor layer partially in contact with the first electrode, and an amorphous structure in contact with the p-type amorphous semiconductor layer. A photoelectric conversion layer made of a semiconductor film, an n-type amorphous semiconductor layer in contact with the photoelectric conversion layer made of the semiconductor film having an amorphous structure, and a second contact in contact with the n-type amorphous semiconductor layer An electrode,
The amplifier circuit is a semiconductor device including an n-channel TFT having a semiconductor film having a crystal structure.

  In addition, the p-type semiconductor layer, the n-type semiconductor layer, and the i-type (intrinsic) semiconductor layer are not limited to amorphous semiconductor films, and crystalline semiconductors such as microcrystalline semiconductor films (also referred to as microcrystalline semiconductor films). A membrane can be used.

In addition, the configuration of other inventions is as follows:
A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a photoelectric conversion layer made of a crystalline semiconductor film on the first electrode, and a second electrode on the photoelectric conversion layer,
The amplifier circuit includes a TFT having a semiconductor film having a crystal structure.

  By using a microcrystalline semiconductor film, an impurity concentration imparting n-type or p-type can be included at a high concentration, and the electric resistance value of the film can be reduced.

Further, as the p-type semiconductor layer, the n-type semiconductor layer, and the i-type (intrinsic) semiconductor layer, a semiconductor material obtained by a low pressure thermal CVD method, a plasma CVD method, a sputtering method, or the like, for example, silicon or silicon germanium (Si ₁₎ It is possible to use a _-X Ge _X (X = 0.0001 to 0.02) alloy.

Note that in this specification, a crystalline semiconductor film is a kind of semiconductor film having a crystal structure, but refers to a film including crystal grains of several nm to 50 nm, and for convenience, crystal grains larger than 50 nm. A film containing the crystal is called a semiconductor film having a crystal structure. A case where a crystal grain of about several to 50 nm is mixed in an amorphous semiconductor film is also called a crystalline semiconductor film.

In addition, the configuration of other inventions is as follows:
In a semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element is in contact with a cathode-side electrode (first electrode), a photoelectric conversion layer made of a semiconductor film having an amorphous structure partially in contact with the cathode-side electrode, and the photoelectric conversion layer. An electrode on the anode side (second electrode),
The amplifier circuit is composed of an n-channel TFT having a semiconductor film having a crystal structure,
The optical sensor element and the amplifier circuit are provided on a plastic substrate via an adhesive layer.

  In the above structure, the first electrode is formed using the same material as the source electrode or the drain electrode of the n-channel TFT. In the above structure, the photoelectric conversion layer is provided in contact with an interlayer insulating film of the n-channel TFT.

In addition, a p-channel TFT can be used instead of the n-channel TFT, and the configuration of the other invention is as follows.
A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a p-type amorphous semiconductor layer partially in contact with the first electrode, and an amorphous structure in contact with the p-type amorphous semiconductor layer. A photoelectric conversion layer made of a semiconductor film, an n-type amorphous semiconductor layer in contact with the photoelectric conversion layer made of the semiconductor film having an amorphous structure, and a second contact in contact with the n-type amorphous semiconductor layer An electrode,
The amplifier circuit is a semiconductor device including a p-channel TFT having a semiconductor film having a crystal structure.

Further, in the case of a PIN photodiode, the p-type semiconductor layer, the n-type semiconductor layer, or the i-type (intrinsic) semiconductor layer may be a crystalline semiconductor film. Other aspects of the invention are:
A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element includes a first electrode, a p-type crystalline semiconductor layer partially in contact with the first electrode, and a semiconductor film having an amorphous structure in contact with the p-type crystalline semiconductor layer A photoelectric conversion layer comprising: an n-type crystalline semiconductor layer in contact with the photoelectric conversion layer comprising a semiconductor film having an amorphous structure; and a second electrode in contact with the n-type crystalline semiconductor layer. And
The amplifier circuit is a semiconductor device including an n-channel TFT having a semiconductor film having a crystal structure.

In the above structure, a p-channel TFT can be used instead of the n-channel TFT.
A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element includes a first electrode, a p-type crystalline semiconductor layer partially in contact with the first electrode, and a semiconductor film having an amorphous structure in contact with the p-type crystalline semiconductor layer A photoelectric conversion layer comprising: an n-type crystalline semiconductor layer in contact with the photoelectric conversion layer comprising a semiconductor film having an amorphous structure; and a second electrode in contact with the n-type crystalline semiconductor layer. And
The amplifier circuit is a semiconductor device including a p-channel TFT having a semiconductor film having a crystal structure.

In the case of a PIN photodiode, only the n-type semiconductor layer of the p-type semiconductor layer, the n-type semiconductor layer, or the i-type (intrinsic) semiconductor layer may be a crystalline semiconductor film. The configuration is
A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a p-type amorphous semiconductor layer partially in contact with the first electrode, and an amorphous structure in contact with the p-type amorphous semiconductor layer. A photoelectric conversion layer made of a semiconductor film, an n-type crystalline semiconductor layer in contact with the photoelectric conversion layer made of a semiconductor film having an amorphous structure, and a second electrode in contact with the n-type crystalline semiconductor layer Have
The amplifier circuit is a semiconductor device including an n-channel TFT having a semiconductor film having a crystal structure.

In the above structure, a p-channel TFT can be used instead of the n-channel TFT.
A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a p-type amorphous semiconductor layer partially in contact with the first electrode, and an amorphous structure in contact with the p-type amorphous semiconductor layer. A photoelectric conversion layer made of a semiconductor film, an n-type crystalline semiconductor layer in contact with the photoelectric conversion layer made of a semiconductor film having an amorphous structure, and a second electrode in contact with the n-type crystalline semiconductor layer Have
The amplifier circuit is a semiconductor device including a p-channel TFT having a semiconductor film having a crystal structure.

In the case of a PIN photodiode, only the p-type semiconductor layer of the p-type semiconductor layer, the n-type semiconductor layer, or the i-type (intrinsic) semiconductor layer may be a crystalline semiconductor film. The configuration is
A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element includes a first electrode, a p-type crystalline semiconductor layer partially in contact with the first electrode, and a semiconductor film having an amorphous structure in contact with the p-type crystalline semiconductor layer A n-type amorphous semiconductor layer in contact with the n-type amorphous semiconductor layer; a n-type amorphous semiconductor layer in contact with the n-type amorphous semiconductor layer; Have
The amplifier circuit is a semiconductor device including an n-channel TFT having a semiconductor film having a crystal structure.

In the above structure, a p-channel TFT can be used instead of the n-channel TFT.
A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element includes a first electrode, a p-type crystalline semiconductor layer partially in contact with the first electrode, and a semiconductor film having an amorphous structure in contact with the p-type crystalline semiconductor layer A n-type amorphous semiconductor layer in contact with the n-type amorphous semiconductor layer; a n-type amorphous semiconductor layer in contact with the n-type amorphous semiconductor layer; Have
The amplifier circuit is a semiconductor device including a p-channel TFT having a semiconductor film having a crystal structure.

  In each of the above structures, the optical sensor element and the amplifier circuit are provided on a plastic substrate via an adhesive layer.

  In each of the above structures, the external terminal provided on the chip having the plastic substrate has a two-terminal structure. Therefore, the number of pins is reduced as in the case of the conventional single amorphous visible light sensor, and visible light sensing can be performed at a small number of mounting locations.

In addition, the configuration of the invention related to a method for manufacturing a semiconductor device is as follows.
In a method for manufacturing a semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
Forming a source electrode or a drain electrode connected to a source region or a drain region of a thin film transistor constituting an amplifier circuit, and simultaneously forming a first electrode in contact with the interlayer insulating film of the thin film transistor;
Stacking a first conductive crystalline semiconductor film, an amorphous semiconductor film, and a second conductive crystalline semiconductor film covering the first electrode and the interlayer insulating film;
Forming a second electrode on the second conductive crystalline semiconductor film;
Etching the first conductive crystalline semiconductor film, the amorphous semiconductor film, and the second conductive crystalline semiconductor film in a self-aligning manner using the second electrode as a mask. This is a method for manufacturing a semiconductor device.

  In the structure related to the manufacturing method, the stack of the first conductive crystalline semiconductor film, the amorphous semiconductor film, and the second conductive crystalline semiconductor film is a photoelectric conversion layer, and the first electrode is a cathode. The second electrode is an anode electrode, and the second electrode is an anode electrode.

In addition, the semiconductor device obtained by the above manufacturing method is etched using the second electrode as a mask so that the end surface of the second electrode and the end surface of the photoelectric conversion layer are aligned.

  In addition, the present invention is characterized in that the sensor element and the amplification circuit are transferred to a plastic film substrate using the peeling and transfer technique described in JP-A-2003-174153. Further, the peeling and transfer technique is not limited to the technique described in the above publication, and various methods (for example, those described in JP-A-8-288522, JP-A-8-250745, or JP-A-8-26496). A technique such as a peeling technique in which the peeling layer is removed by dry etching or wet etching may be used.

In addition, the configuration of the invention related to a manufacturing method for realizing the above structure is as follows.
In a method for manufacturing a semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
Forming a layer to be peeled including an amplifier circuit and an optical sensor element on a first substrate;
Peeling the layer to be peeled including the amplification circuit and the optical sensor element from the first substrate;
Transferring a layer to be peeled including the amplification circuit and the optical sensor element to a second substrate;
Dividing the second substrate to produce a chip including the amplifier circuit and the optical sensor element;
Mounting a chip including the amplifier circuit and the optical sensor element on a printed wiring board by a solder reflow process.

Further, in the above manufacturing method, the step of peeling the peeled layer including the amplifier circuit and the optical sensor element from the first substrate and transferring the peeled layer to the second substrate,
A first step of applying an organic resin film soluble in a solvent on the layer to be peeled;
A second step of bonding a fifth substrate to the organic resin film with a first double-sided tape, and sandwiching the peeled layer and the organic resin film between the first substrate and the fifth substrate;
A third step of bonding a sixth substrate to the first substrate with a second double-sided tape;
A fourth step of separating the first substrate to which the sixth substrate is bonded and the layer to be peeled off by physical means or etching;
A fifth step of adhering a second substrate to the peelable layer with a first adhesive, and sandwiching the peelable layer between the sixth substrate and the second substrate;
A sixth step of separating the peelable layer and the first double-sided tape from the sixth substrate;
A seventh step of separating the peelable layer and the first double-sided tape;
And an eighth step of removing the organic resin film.

In the manufacturing method, the solvent is water or alcohols. In the manufacturing method, the first substrate is a glass substrate, and the fifth substrate and the sixth substrate are quartz substrates or metal substrates. In the manufacturing method, the second substrate and the fourth substrate are plastic film substrates.

  The present invention can be applied regardless of the TFT structure. For example, a top gate TFT, a bottom gate (inverse staggered) TFT, or a forward staggered TFT can be used. Further, the TFT is not limited to a single-gate TFT, and may be a multi-gate TFT having a plurality of channel formation regions, for example, a double-gate TFT.

  By integrally forming a visible light sensor and an amplifier circuit using TFTs on the same substrate, it is possible to reduce costs, reduce the volume of components by reducing the thickness, and reduce the mounting area. Can be reduced.

  By using a sensor element using an amorphous silicon film as the visible light sensor, an infrared cut filter is not required, and a visible light sensor with small output variation of the sensor element can be obtained. In addition, an increase in output current and suppression of variation can be achieved by an amplifier circuit formed of TFTs formed on the same substrate. In addition, the light receiving area can be reduced by the output amplification by the amplifier circuit, so that the mounting set can be reduced in size and weight, and the number of parts can be reduced.

  Further, by using a plastic film substrate, impact resistance is improved, and a visible light sensor that can withstand bending, twisting, and the like can be realized. Moreover, it can be made thin and can be mounted on a curved surface. If a plastic film substrate having high heat resistance is used, it can be mounted by a solder reflow process as in the case of a conventional SMD component.

  In addition, if a sensor element is formed over a plastic film substrate, laser processing becomes possible, so that it is possible to realize a micro size that is difficult to cut with a single crystal silicon substrate or a glass substrate.

  Embodiments of the present invention will be described below.

  FIG. 1A is a view showing a mounting cross section of the optical sensor chip of the present invention. FIG. 1A shows an example of a two-terminal visible light sensor chip (2.0 mm × 1.5 mm). In FIG. 1A, 10 is a film substrate, 11 is an adhesive layer, 12 is a base insulating film, and 13 is a gate insulating film. Since the received light passes through the film substrate 10, the adhesive layer 11, the base insulating film 12, and the gate insulating film 13, it is desirable that all of these materials are materials having high translucency. Further, as the film substrate 10, a heat-resistant plastic substrate (thickness: 200 μm to 500 μm) that can withstand a mounting temperature (about 250 ° C.) such as solder reflow processing, for example, an HT substrate (Nippon Steel) having a Tg of 400 ° C. or more. Chemical Co., Ltd.) is used. Furthermore, the HT substrate has high transparency (400 nm light transmittance of 90% or more) and low thermal expansion (CTE <48 ppm).

  The PIN photodiode 25 is sandwiched between a first electrode 19, a second electrode 23, a p-type semiconductor layer 21p, an n-type semiconductor layer 21n, and a p-type semiconductor layer and an n-type semiconductor layer. The i-type (intrinsic) semiconductor layer 21i is used.

  An amplifier circuit provided on the same substrate for amplifying the output value of the PIN photodiode 25 is formed of a current mirror circuit including n-channel TFTs 30 and 31. Although only two TFTs are shown in FIG. 1A, two n-channel TFTs 30 (channel size L / W = 8 μm / 50 μm) and n-channel are actually used to increase the output value by five times. Ten type TFTs 31 (channel size L / W = 8 μm / 50 μm) are provided. Here, one n-channel TFT 30 and 100 n-channel TFTs 31 are provided in order to make the magnification 100 times.

  FIG. 1B shows an equivalent circuit diagram of a two-terminal visible light sensor chip. FIG. 1B is an equivalent circuit diagram using an n-channel TFT, but only a p-channel TFT may be used instead of the n-channel TFT.

  In the case of forming with a p-channel TFT, an equivalent circuit diagram shown in FIG. 12 is obtained. In FIG. 12, terminal electrodes 26 and 53 are the same as those in FIG. 1B, but a photodiode 1225 and p-channel TFTs 1230 and 1231 may be connected as shown in FIG. In the case of using a p-channel TFT, the p-channel TFT 1230 is electrically connected to the anode-side electrode of the photodiode 1225. The photodiode 1225 is formed by sequentially stacking an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer on a second electrode (anode side electrode) connected to the p-channel TFT 1230, and then the first electrode (cathode). Side electrode) may be formed. Alternatively, a photodiode in which the stacking order is reversed may be used. After sequentially stacking a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer on the first electrode (cathode side electrode), a p-channel type is formed. A second electrode (an anode side electrode) connected to the TFT 1230 may be formed, and a cathode side terminal electrode connected to the first electrode may be formed.

  Further, in order to amplify the output value, the amplifier circuit may be composed of an operational amplifier (op-amp) in which n-channel TFTs or p-channel TFTs are appropriately combined, but has five terminals. In addition, an operational amplifier can be configured by an operational amplifier and a level shifter can be used to reduce the number of power supplies to four terminals.

  Further, although the n-channel TFTs 30 and 31 are examples of a top gate type TFT having a single gate structure, a variation in on-current value may be reduced by a double gate structure. In order to reduce the off-current value, the n-channel TFTs 30 and 31 may have a lightly doped drain (LDD) structure. In this LDD structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration. It is called. The LDD structure has the effect of relaxing the electric field in the vicinity of the drain and preventing deterioration due to hot carrier injection. In order to prevent deterioration of the on-current value due to hot carriers, the n-channel TFTs 30 and 31 may have a GOLD (Gate-drain Overlapped LDD) structure. The GOLD structure in which the LDD region is disposed so as to overlap the gate electrode with the gate insulating film interposed therebetween has an effect of relaxing the electric field in the vicinity of the drain and preventing deterioration due to hot carrier injection as compared with the LDD structure. By adopting such a GOLD structure, the electric field strength in the vicinity of the drain is relaxed to prevent hot carrier injection and to effectively prevent the deterioration phenomenon.

  The wiring 14 is a wiring connected to the first electrode 19 and also extends above the channel formation region of the TFT 30 of the amplifier circuit and serves as a gate electrode.

  The wiring 15 is connected to the second electrode 23 and is connected to the drain electrode or the source electrode of the TFT 31. 16 and 18 are inorganic insulating films, 17 is an insulating film formed by a coating method, and 20 is a connection electrode. Since the received light passes through the inorganic insulating films 16 and 18 and the insulating film 17 formed by a coating method, it is desirable that all of these materials are materials having high translucency. The insulating film 17 is not limited to a coating method, and an inorganic insulating film obtained by a CVD method may be used. When the insulating film 17 is an inorganic insulating film obtained by a CVD method, the fixing strength is improved.

  The terminal electrode 50 is formed in the same process as the wirings 14 and 15, and the terminal electrode 51 is formed in the same process as the electrodes 19 and 20.

  The terminal electrode 26 on the anode side is connected to the second electrode 23, and is mounted on the electrode 61 of the printed wiring board 60 with solder 64. The cathode-side terminal electrode 53 is formed in the same process as the terminal electrode 26, and is mounted on the electrode 62 of the printed wiring board 60 with solder 63.

  In addition, a manufacturing process for obtaining the above structure is described below with reference to FIGS. The semiconductor element formed on the glass substrate is peeled off and transferred, and attached to the film substrate 10 with the adhesive layer 11.

  Here, an example in which a semiconductor element is peeled and transferred using a peeling method using a metal film (W, WN, Mo, etc.) and a silicon oxide film by a sputtering method is shown.

  First, an element is formed over a glass substrate (first substrate 70). Here, AN100 is used as the glass substrate. A metal film 71, here a tungsten film (deposition conditions for reducing film stress: Ar flow rate 100 sccm, film formation pressure 2 Pa, film formation power 4 kW, substrate temperature 200 ° C., film thickness 10 nm on this glass substrate by sputtering. ˜200 nm, preferably 50 nm to 75 nm), and an oxide film which is the first layer of the base insulating film 12 without being exposed to the atmosphere, here a silicon oxide film (film thickness 150 nm to 200 nm) is stacked by sputtering. Form. The thickness of the oxide film is preferably at least twice that of the metal film. Note that an amorphous metal oxide film (tungsten oxide film) is formed to a thickness of about 2 nm to 5 nm between the metal film 71 and the silicon oxide film at the time of stacking. When separation is performed in a later step, separation occurs in the tungsten oxide film, at the interface between the tungsten oxide film and the silicon oxide film, or at the interface between the tungsten oxide film and the tungsten film. In place of the tungsten film, an element selected from Ti, Ta, Mo, Nd, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, or an alloy material containing the element as a main component or A single layer made of a compound material or a stacked layer thereof, or a single layer made of these nitrides such as titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride, or a stacked layer thereof can be used.

Note that since sputtering is performed on the substrate end surface, the tungsten film, tungsten oxide film, and silicon oxide film formed on the substrate end surface are dry-etched using SF ₆ gas and He gas, and O ₂ ashing, etc. Is preferably removed selectively.

Next, a silicon oxynitride film (film thickness: 100 nm) which is the second layer of the base insulating film 12 is formed by PCVD, and an amorphous silicon film (film thickness: 54 nm) containing hydrogen is stacked without being exposed to the atmosphere. . Note that the silicon oxynitride film is a blocking layer that prevents diffusion of impurities such as alkali metal from the glass substrate.

  Next, the amorphous silicon film is crystallized by a known technique (solid phase growth method, laser crystallization method, crystallization method using a catalytic metal, etc.), and an element using a TFT having a polysilicon film as an active layer is obtained. Form. Here, a polysilicon film is obtained using a crystallization method using a catalytic metal. A nickel acetate salt solution containing 10 ppm of nickel by weight is applied with a spinner. Note that a nickel element may be dispersed over the entire surface by sputtering instead of coating. Next, heat treatment is performed for crystallization, so that a semiconductor film having a crystal structure (here, a polysilicon layer) is formed. Here, after heat treatment (500 ° C., 1 hour), heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a silicon film having a crystal structure.

The amorphous silicon film contains hydrogen, and when a polysilicon film is formed by heating, if a heat treatment at 410 ° C. or higher is performed for crystallization, hydrogen can be diffused at the same time as the polysilicon film is formed. Further, by performing heat treatment at 400 ° C. or higher, the amorphous metal oxide film is crystallized, and a metal oxide film having a crystal structure is obtained. Therefore, by performing a heat treatment at 410 ° C. or higher, a metal oxide film having a crystal structure is formed, and hydrogen is diffused. When the heat treatment at 410 ° C. or higher is completed, a relatively small force (for example, human hand, wind pressure of gas blown from a nozzle, ultrasonic wave, etc.) is applied to the tungsten oxide film or the tungsten oxide film. Separation can occur at the interface between the silicon oxide film and the interface between the tungsten oxide film and the tungsten film. Note that when heat treatment is performed at a temperature at which a metal oxide film having a crystal structure is obtained, the composition of the metal oxide film is changed and the thickness of the metal oxide film is slightly reduced. Further, the tungsten oxide film having a crystal structure has a plurality of crystal structures (WO ₂ , WO ₃ , WOx (2 <X <3)), and the composition of WO ₃ changes to WO ₂ or WOx by heat treatment. .

Next, after removing the oxide film on the surface of the silicon film having a crystal structure with dilute hydrofluoric acid or the like, irradiation with laser light (XeCl: wavelength 308 nm) for increasing the crystallization rate and repairing defects left in the crystal grains In the air or in an oxygen atmosphere. As the laser light, excimer laser light having a wavelength of 400 nm or less, and second harmonic and third harmonic of a YAG laser are used. Here, a pulsed laser beam having a repetition frequency of about 10 to 1000 Hz is used, the laser beam is condensed to 100 to 500 mJ / cm ² by an optical system, and irradiated with an overlap rate of 90 to 95%. May be scanned. Here, laser light irradiation was performed in the air at a repetition frequency of 30 Hz and an energy density of 470 mJ / cm ² . Note that since the reaction is performed in the air or in an oxygen atmosphere, an oxide film is formed on the surface by laser light irradiation. Although an example using a pulse laser is shown here, a continuous wave laser may be used, and in order to obtain a crystal with a large grain size when crystallizing an amorphous semiconductor film, continuous wave is possible. It is preferable to use a simple solid-state laser and apply the second to fourth harmonics of the fundamental wave. Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied. In the case of using a continuous wave laser, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method of emitting harmonics by putting a YVO ₄ crystal and a nonlinear optical element in a resonator. Preferably, the laser beam is shaped into a rectangular or elliptical shape on the irradiation surface by an optical system, and the object to be processed is irradiated. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.

Next, in addition to the oxide film formed by the laser light irradiation, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total thickness of 1 to 5 nm. This barrier layer is formed in order to remove nickel added for crystallization from the film. Here, the barrier layer is formed using ozone water, but the surface of the semiconductor film having a crystal structure is oxidized by a method of oxidizing the surface of the semiconductor film having a crystal structure by irradiation with ultraviolet light in an oxygen atmosphere or the oxygen plasma treatment. The barrier layer may be formed by depositing an oxide film of about 1 to 10 nm by a method, plasma CVD method, sputtering method or vapor deposition method. Further, the oxide film formed by laser light irradiation may be removed before forming the barrier layer.

Next, an amorphous silicon film containing an argon element serving as a gettering site is formed with a thickness of 10 nm to 400 nm, here 100 nm, over the barrier layer by a sputtering method. Here, the amorphous silicon film containing an argon element is formed in an atmosphere containing argon using a silicon target. In the case where an amorphous silicon film containing an argon element is formed using a plasma CVD method, the film formation conditions are a monosilane / argon flow rate ratio (SiH ₄ : Ar) of 1:99 and a film formation pressure of 6.665 Pa. (0.05 Torr), RF power density is 0.087 W / cm ^2, and film forming temperature is 350 ° C.

After that, heat treatment is performed for 3 minutes in a furnace heated to 650 ° C., and gettering is performed to reduce the nickel concentration in the semiconductor film having a crystal structure. A lamp annealing apparatus may be used instead of the furnace.

Next, the amorphous silicon film containing an argon element as a gettering site is selectively removed using the barrier layer as an etching stopper, and then the barrier layer is selectively removed with dilute hydrofluoric acid. Note that during gettering, nickel tends to move to a region with a high oxygen concentration, and thus it is desirable to remove the barrier layer made of an oxide film after gettering.

  Note that in the case where the semiconductor film is not crystallized using a catalytic element, the above-described barrier layer formation, gettering site formation, heat treatment for gettering, gettering site removal, barrier layer removal, etc. This step is unnecessary.

  Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also called a polysilicon film), a mask made of resist is formed using a first photomask, and a desired film is formed. A semiconductor layer separated into islands is formed by etching into a shape. After the semiconductor layer is formed, the resist mask is removed.

Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped in order to control the threshold value of the TFT. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used.

  Next, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the silicon film is washed, and then an insulating film containing silicon as a main component and serving as the gate insulating film 13 is formed. Here, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 115 nm is formed by plasma CVD.

  Next, after forming a metal film over the gate insulating film, patterning is performed using a second photomask to form the gate electrode, the wirings 14 and 15, and the terminal electrode 50. Next, the source layer or the drain region of the TFT is formed by doping the active layer.

  Next, after forming a first interlayer insulating film (not shown) made of a silicon oxide film by CVD with a thickness of 50 nm, a step of activating the impurity element added to each semiconductor layer is performed. This activation step may be a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination thereof. By different methods.

  Next, a second interlayer insulating film 16 made of a silicon nitride oxide film containing hydrogen is formed and subjected to heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) to hydrogenate the semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the first interlayer insulating film 16. The semiconductor layer can be hydrogenated regardless of the presence of the insulating film 13 made of a silicon oxide film.

  Next, a third interlayer insulating film 17 made of an insulating material is formed on the second interlayer insulating film 16. As the third interlayer insulating film 17, an organic insulating film obtained by a coating method or an inorganic insulating film obtained by a CVD method can be used. Here, an acrylic resin film having a thickness of 0.8 μm is formed.

  Next, a fourth interlayer insulating film 18 made of an inorganic insulating film having a thickness of 250 nm to 350 nm is formed on the third interlayer insulating film 17 by sputtering. Note that in the case where an inorganic insulating film is formed as the third interlayer insulating film, the fourth interlayer insulating film 18 is not necessarily formed.

  Next, a resist mask is formed using a third photomask, and the interlayer insulating films 16, 17, 18 or the gate insulating film 13 are selectively etched to form contact holes. Then, the resist mask is removed.

  Next, after laminating the metal film, a resist mask is formed using a fourth photomask, and the metal laminate film is selectively etched, so that the first electrode 19, the connection electrode 20, the terminal electrode 51, A source electrode or a drain electrode of the TFT is formed. Then, the resist mask is removed. Note that the metal stacked film is a three-layer stack including a Ti film with a thickness of 100 nm, an Al film containing a small amount of Si with a thickness of 350 nm, and a Ti film with a thickness of 100 nm.

  Through the above steps, the top gate TFTs 30 and 31 having the polysilicon film as an active layer can be manufactured, and the structure shown in FIG. 2A is obtained.

  Next, a p-type semiconductor layer, an i-type (intrinsic) semiconductor layer, and an n-type semiconductor layer are sequentially stacked on the first electrode as a photoelectric conversion layer.

As the p-type semiconductor layer, a PCVD method is used, the electrode interval is 32 mm, the film forming pressure is 266 Pa, the RF power is 550 W, SiH ₄ (flow rate 4 sccm), B ₂ H ₆ (flow rate 20 sccm), H ₂ (flow rate 773 sccm) A p-type amorphous silicon film with a film thickness of 50 nm is formed using as a source gas.

In addition, the PCVD method is used for the i-type (intrinsic) semiconductor layer, the electrode interval is 36 mm, the deposition pressure is 133 Pa, the RF power is 50 W to 88 W, and SiH ₄ (flow rate 100 sccm) and H ₂ (flow rate 1000 sccm) are used as source gases. An I-type amorphous silicon film having a thickness of 600 nm is formed.

Further, as the n-type semiconductor layer, a PCVD method is used, the electrode interval is 36 mm, the film forming pressure is 133 Pa, the RF power is 300 W, SiH ₄ (flow rate 5 sccm), PH ₃ (flow rate 30 sccm), H ₂ (flow rate 950 sccm) An n-type amorphous silicon film with a film thickness of 70 nm is formed using as a source gas.

In addition, before the photoelectric conversion layer is formed, a treatment for improving the adhesion with the interlayer insulating film 18, for example, an Ar plasma treatment or a CF ₄ plasma treatment may be performed.

Next, after forming a metal film, here, a 100 nm-thick Ti film, a resist mask is formed using a fifth photomask, and the Ti film is etched to form the second electrode 23. Either dry etching or wet etching can be used. Here, etching is performed using an etchant (NH ₄ OH: H ₂ O ₂ : H ₂ O = 2: 5: 2). When dry etching is performed, Cl ₂ gas may be used. Here, the area of the second electrode 23 of one photosensor is 1.57 mm ² , and this area is substantially equal to the light receiving area. Then, the resist mask is removed.

Next, a resist mask is formed using a sixth photomask, and the stacked layer of the amorphous silicon film is selectively etched to form photoelectric conversion layers 21p, 21i, and 21n. Either dry etching or wet etching can be used. Here, dry etching using SF ₆ (flow rate 20 sccm) and He (flow rate 20 sccm) as etching gases is performed. Further, dry etching may be performed using NF ₃ instead of SF ₆ . Then, the resist mask is removed.

  Through the above steps, a photodiode including the first electrode 19, photoelectric conversion layers 21p, 21i, and 21n made of an amorphous silicon film, and the second electrode 23 can be manufactured. The structure illustrated in FIG. obtain.

  Next, a sealing resin 24 made of an insulating material film is formed on the entire surface with a thickness (1 μm to 30 μm). Here, an acrylic resin film having a thickness of 1.6 μm is formed as the insulator material film. Further, as the insulating material film, an insulating film made of a SiOx film containing an alkyl group obtained by a coating method, for example, silica glass, an alkylsiloxane polymer, an alkylsilsesquioxane polymer, or a hydrogenated silsesquioxane polymer may be used. Good. Examples of siloxane-based polymers include PSB-K1 and PSB-K31, which are Toray-made coating insulating film materials, and ZRS-5PH, which is a catalytic chemical-made coating insulating film material. When an insulating film made of a SiOx film containing an alkyl group is used, the mounting strength can be improved. Next, a resist mask is formed using a seventh photomask, and the organic insulating material film is selectively etched to form contact holes. Then, the resist mask is removed.

  Here, an example in which the sealing resin is formed by patterning the resin film using the photolithography technique is shown, but the present invention is not particularly limited. For example, the sealing resin may be formed by a screen printing method. Further, instead of the sealing resin, an inorganic insulating film sealing layer obtained by a CVD method may be used.

  Next, the terminal electrodes 26 and 53 are formed by sputtering using a metal mask. The terminal electrodes 26 and 53 are laminated films of a Ti film, a Ni film, and an Au film. FIG. 5 shows the result of evaluating the fixing strength by forming a laminated film of a Ti film, a Ni film, and an Au film on a glass substrate by a sputtering method using a metal mask. A pair of electrode patterns was formed with the metal masks having a dimension of 0.3 mm, 0.5 mm, and 0.7 mm. Considering the amount of wraparound of the mask, the distance between the terminal electrode 26 and the terminal electrode 53 is preferably 0.3 mm or more. In FIG. 5, the vertical axis indicates the adhesion strength, and the horizontal axis indicates the sum of the two electrode areas. As can be seen from FIG. 5, it can be seen that each sample has a sufficient fixing strength as a terminal electrode since the fixing strength exceeds 5N.

  Here, an example in which the terminal electrode is formed by sputtering using a metal mask has been shown, but there is no particular limitation. For example, the terminal electrode is formed by screen printing using Ni paste or Carbon-based resin. Also good. In addition, the electrode (terminal electrode) formed by screen printing is comprised with the electrically-conductive material containing resin.

  Through the above steps, terminal electrodes 26 and 53 capable of solder connection are formed, and the structure shown in FIG. 2C is obtained. An optical sensor and an amplifier circuit can be manufactured using seven photomasks and one metal mask, that is, a total of eight masks.

  Next, an adhesive material soluble in water or alcohols is applied to the entire surface and baked. The composition of the adhesive may be any one such as epoxy, acrylate, or silicone. Here, a film (thickness 30 μm) 74 made of a water-soluble resin (manufactured by Toagosei Co., Ltd .: VL-WSHL10) 74 is applied by spin coating, exposure is performed for 2 minutes for temporary curing, and then UV light is applied from the back surface 2 Exposure is performed for 5 minutes, 10 minutes from the surface, and a total of 12.5 minutes for the main curing. This water-soluble resin film functions as a flattening film, and can be bonded so that the surface of the flattening film and the substrate surface are substantially parallel when the substrates are bonded together. When this water-soluble resin film is not used, there is a risk that unevenness due to electrodes or TFTs may occur when pressure bonding.

  Next, in order to facilitate subsequent peeling, a treatment for partially reducing the adhesion between the metal film 71 and the metal oxide film or the adhesion between the metal oxide film and the oxide film is performed. The process of partially lowering the adhesion is a process of partially irradiating the metal oxide film with a laser beam along the periphery of the region to be peeled, or a local treatment from the outside along the periphery of the region to be peeled off. In this process, a pressure is applied to damage the metal oxide layer or a part of the interface. Specifically, a hard needle may be pressed vertically with a diamond pen or the like to move under a load. Preferably, a scriber device is used, the pushing amount is 0.1 mm to 2 mm, and the pressure is applied. In this way, it is important to create a part where peeling phenomenon is likely to occur before peeling, that is, a trigger, and by performing a pretreatment that selectively (partially) decreases adhesion, peeling is performed. Defects are eliminated and the yield is improved.

  Next, the second substrate 72 is attached to the film 74 made of a water-soluble resin by using a double-sided tape 73. Further, a third substrate 76 is attached to the first substrate 70 using a double-sided tape 75. The third substrate 76 prevents the first substrate 70 from being damaged in a subsequent peeling step. As the second substrate 72 and the third substrate 76, it is preferable to use a substrate having higher rigidity than the first substrate 70, such as a quartz substrate or a semiconductor substrate. Note that an adhesive may be used instead of the double-sided tape, and for example, an adhesive that is peeled off by ultraviolet irradiation may be used.

  Next, the first substrate 70 on which the metal film 71 is provided is peeled off by physical means from the region side where the adhesion is partially reduced. It can be peeled off with a relatively small force (for example, a human hand, wind pressure of a gas blown from a nozzle, ultrasonic waves, etc.). Thus, the layer to be peeled formed on the silicon oxide layer 12 can be separated from the first substrate 70. The state after peeling is shown in FIG.

When peeled, all of WO ₂ remains on the first substrate, 1/3 of WO ₃ remains on the first substrate, and the remaining 2/3 remains on the layer to be peeled. Separation is likely to occur in the tungsten oxide film, particularly from the boundary between WO ₂ and WOx or the boundary between WO ₂ and WO ₃ . Although the tungsten oxide film is partially left on the layer to be peeled, it is transparent, and therefore it may not be removed or may be removed. Remove here.

  In this manner, a circuit including a TFT having high electrical characteristics (typically field effect mobility) that can only be obtained on a glass substrate can be transferred onto the film substrate as it is.

  Next, the fourth substrate 10 and the oxide layer 12 (and the layer to be peeled) are bonded with the adhesive 11. (FIG. 3 (B)) The adhesive 11 is more adhesive between the oxide layer 12 (and the layer to be peeled) and the fourth substrate than the adhesiveness between the second substrate 72 and the layer to be peeled by the double-sided tape 73. It is important that it is higher.

Examples of the adhesive 11 include a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and various curable adhesives such as an anaerobic adhesive.

  Next, the second substrate 72 is separated from the double-sided tape 73. Next, the double-sided tape 73 is peeled off. Further, the water-soluble resin 74 is dissolved and removed using water. (Figure 3 (C))

  Through the above steps, an amplifier circuit and an optical sensor element made of TFT transferred to the plastic substrate 10 can be prepared.

Next, a plurality of optical sensor chips are cut out by cutting with CO ₂ laser or dicing. Since the substrate provided with the optical sensor element is a film substrate, cutting can be performed relatively easily. A large amount of optical sensor chips (2 mm × 1.5 mm) can be manufactured from one large-area substrate (for example, 600 cm × 720 cm).

  FIG. 4A shows a cross-sectional view of one cut-out optical sensor chip (2 mm × 1.5 mm), FIG. 4B is a bottom view thereof, FIG. 4C is a top view thereof, and an external photograph from the top surface. The figure is shown in FIG. In FIG. 4, the same reference numerals are used for portions that are the same as in FIGS. 1, 2, and 3.

In FIG. 4A, the total film thickness including the substrate 10, the adhesive layer 11, the element formation region 400, and the electrodes 26 and 53 is 0.25 ± 0.05 mm. 4B, one electrode size of the terminal electrodes 26 and 53 is 0.6 mm × 1.1 mm, and the electrode interval is 0.4 mm. In FIG. 4C, the area of the light receiving portion 401 is approximately equal to the area of the second electrode and is 1.57 mm ² . In addition, the amplifier circuit unit 402 is provided with about 100 TFTs.

  Finally, the obtained optical sensor chip is mounted on the mounting surface of the printed wiring board 60. The terminal electrodes 26 and 53 and the electrodes 61 and 62 are connected by using solder, which is previously formed on the electrodes 61 and 62 of the printed wiring board 60 by a screen printing method or the like, and the solder and the terminal electrodes are applied. Solder reflow treatment is performed after mounting. The solder reflow process is performed, for example, in an inert gas atmosphere at a temperature of about 255 ° C. to 265 ° C. for about 10 seconds. Therefore, as the substrate 10, it is preferable to use a film substrate having a heat resistance of 260 ° C. or higher that can withstand at least this solder reflow process. The HT substrate used as the substrate 10 is a plastic substrate obtained by processing a material in which inorganic particles having a diameter of several nanometers are dispersed in an organic polymer matrix into a sheet shape, and has a glass transition temperature Tg of 400 ° C. or more and sufficiently withstands a solder reflow process. sell. In addition to solder, bumps formed of metal (gold, silver, etc.) or bumps formed of conductive resin can be used. Moreover, you may mount using lead-free solder in consideration of an environmental problem.

FIG. 1A shows an optical sensor chip mounted through the above steps.

  FIG. 6 shows the illuminance characteristics of the optical sensor. In FIG. 6, the vertical axis represents the photocurrent IL (μA), and the horizontal axis represents the illuminance Ev (lx). The photosensor of the present invention shown in FIG. 6 (a circuit-integrated photosensor equipped with an amplifier circuit that increases the output value by 100) can obtain a photocurrent of about 10 μA at an illuminance of 100 lux.

FIG. 11 shows electrical characteristics (IV characteristics) of a circuit-integrated photosensor provided with an amplifier circuit that increases the output value by 10 times. In order to increase the output value by 10 times, two n-channel TFTs 30 (channel size L / W = 8 μm / 50 μm) and 20 n-channel TFTs 31 (channel size L / W = 8 μm / 50 μm) are provided. Since the output value of the sensor having an amplification circuit of 10 magnification is changed according to the magnification with or without light, it is shown that the amplification circuit (10 times) is functioning. In FIG. 11, the voltage shown on the horizontal axis corresponds to the power supply potential connected to the TFT side in the circuit diagram (FIG. 1B), and the potential on the first electrode side of the photosensor is 0 (V). It corresponds to. In FIG. 11, the current value shown on the vertical axis is the output of the optical sensor.

  The present invention having the above-described configuration will be described in more detail with the following examples.

  In this embodiment, a manufacturing example which is partly different from the process shown in the best mode is shown in FIG. 7 differs from FIGS. 1, 2, and 3 only in the second electrode, the same reference numerals are used for other parts that are the same.

First, according to the best mode, a photoelectric conversion layer is formed, and then a process of forming a metal film to be a second electrode later is performed.

  In this embodiment, in order to reduce the number of masks and the number of processes, after forming the second electrode 723 made of Ti, the etching gas is changed, and the mask made of the resist used in forming the second electrode 723 is used. Using 722, the photoelectric conversion layer made of an amorphous silicon film is etched in a self-aligning manner. A process cross-sectional view at this time is shown in FIG.

  When patterning the photoelectric conversion layer, the outermost surface of the first electrode 19 is Ti, so that it functions as an etching stopper, and the insulating film 18 also functions as an etching stopper.

Next, the resist mask 722 is removed, the sealing resin 24 is formed as in the best mode, contact holes are formed, and then the terminal electrodes 26 and 53 are formed. (Fig. 7 (B))

  Since the subsequent steps are the same as the best mode, description thereof is omitted here.

  In this manner, an optical sensor and an amplifier circuit can be manufactured using six photomasks and one metal mask, that is, a total of seven masks.

  Further, since it is formed in a self-aligned manner, the electrode area of the second electrode can be slightly increased compared to the best mode.

  This embodiment can be freely combined with the best mode.

  In this embodiment, a manufacturing example in which the second electrode pattern is different from the process shown in the best mode is shown in FIG. 8 differs from FIGS. 1, 2, and 3 only in the second electrode pattern, and the same reference numerals are used for other parts that are the same. Further, although an amplifier circuit is not shown in FIG. 8, it is formed in the same manner as in the best mode.

First, according to the best mode, a photoelectric conversion layer is formed, and then a process of forming a metal film to be a second electrode later is performed.

  In this embodiment, in order to reduce the number of masks and the number of steps, after forming the second electrode 823 made of Ti, the etching gas is changed, and the mask made of the resist used in forming the second electrode 723 is used. 822 is used to etch the photoelectric conversion layer made of an amorphous silicon film in a self-aligning manner. A process cross-sectional view at this time is shown in FIG.

The second electrode 823 has a pattern shape that completely covers the first electrode 19. The photoelectric conversion layer formed in a self-aligned manner with the second electrode 823 also has a pattern shape that completely covers the first electrode 19.

Next, the resist mask 822 is removed, the sealing resin 24 is formed in the same manner as in the best mode, contact holes are formed, and then the terminal electrodes 26 and 53 are formed. (Fig. 8 (B))

  Since the subsequent steps are the same as the best mode, description thereof is omitted here.

  Thus, the electrode area of the second electrode can be increased as compared with the best mode.

  In addition, an optical sensor and an amplifier circuit can be manufactured using six photomasks and one metal mask, that is, a total of seven masks.

  This embodiment can be freely combined with the best mode.

  In the above embodiment, an example of an amplifier circuit using only an n-channel TFT has been shown. However, in this embodiment, an example of an operational amplifier (op-amp) using a plurality of n-channel TFTs and p-channel TFTs is shown. .

First, similarly to the best mode, a resist mask is formed using a first photomask, and an etching process is performed to a desired shape to form semiconductor layers separated into island shapes. At this stage, the semiconductor layer is formed over the tungsten film and the base insulating film 912 over the glass substrate.

Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped in order to control the threshold value of the TFT. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used.

  Next, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the silicon film is washed, and then an insulating film containing silicon as a main component to be the gate insulating film 913 is formed.

  Next, a first conductive film with a thickness of 20 to 100 nm and a second conductive film with a thickness of 100 to 400 nm are stacked over the gate insulating film. In this embodiment, a tantalum nitride film having a thickness of 50 nm and a tungsten film having a thickness of 370 nm are sequentially stacked on the gate insulating film 913, and patterning is performed in the following procedure to form each gate electrode and each wiring.

  The conductive material for forming the first conductive film and the second conductive film is an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Form. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film and the second conductive film. Further, the present invention is not limited to the two-layer structure. For example, a three-layer structure in which a 50 nm-thickness tungsten film, a 500 nm-thick aluminum and silicon alloy (Al-Si) film, and a 30 nm-thickness titanium nitride film are sequentially stacked Also good. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient.

An ICP (Inductively Coupled Plasma) etching method may be used for the etching of the first conductive film and the second conductive film (first etching process and second etching process). Using the ICP etching method, the film is formed into a desired taper shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) Can be etched. Here, after a mask made of resist is formed, 700 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa as a first etching condition, and CF ₄ , Cl _2, and O are used as etching gases. ₂ and each gas flow ratio is 25/25/10 (sccm), 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is set. Apply. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil-type electrode area size (here, the quartz disk provided with the coil) is a disk having a diameter of 25 cm. The W film is etched under this first etching condition so that the end portion is tapered. Thereafter, the resist mask is not removed and the second etching condition is changed, CF ₄ and Cl ₂ are used as etching gases, the gas flow ratio is 30/30 (sccm), and the pressure is 1 Pa. Then, 500 W RF (13.56 MHz) power was applied to the coil-type electrode to generate plasma, and etching was performed for about 30 seconds. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Here, the first etching condition and the second etching condition are referred to as a first etching process.

Next, a second etching process is performed without removing the resist mask. Here, CF ₄ and Cl ₂ are used as etching gases as the third etching condition, the respective gas flow ratios are set to 30/30 (sccm), and 500 W of RF (13.56) is applied to the coil-type electrode at a pressure of 1 Pa. MHz) power was applied to generate plasma and etching was performed for 60 seconds. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Thereafter, the resist mask is not removed and the etching condition is changed to the fourth etching condition. CF ₄ , Cl ₂ and O ₂ are used as etching gases, and the respective gas flow ratios are 20/20/20 (sccm). The plasma was generated by applying 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa, and etching was performed for about 20 seconds. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Here, the third etching condition and the fourth etching condition are referred to as a second etching process. At this stage, gate electrodes, wirings 914 and 915, and terminal electrodes (not shown) are formed with the first conductive layers 945a and 946a as a lower layer and the second conductive layers 945b and 946b as an upper layer.

Next, after removing the resist mask, a first doping process is performed to dope the entire surface using the gate electrode as a mask. The first doping process may be performed by an ion doping method or an ion implantation method. The conditions of the ion doping method are a dose amount of 1.5 × 10 ¹³ atoms / cm ² and an acceleration voltage of 50 to 100 keV. Typically, phosphorus (P) or arsenic (As) is used as the impurity element imparting n-type conductivity. A first impurity region (n ⁻ region) is formed in a self-aligning manner.

  Next, a resist mask is newly formed. The mask is provided to protect the channel formation region of the semiconductor layer for forming the p-channel TFT of the driver circuit and its peripheral region.

Next, a second doping process is selectively performed using the mask made of the resist to form impurity regions (n ⁻ regions) 941 and 942 and high-concentration impurity regions 943 and 944 that overlap with part of the gate electrode. To do. The second doping process may be performed by an ion doping method or an ion implantation method. Here, an ion doping method is used, a gas in which phosphine (PH ₃ ) is diluted to 5% with hydrogen is set to a flow rate of 40 sccm, a dose amount is set to 3 × 10 ¹⁵ atoms / cm ² , and an acceleration voltage is set to 65 keV. In this case, the resist mask and the second conductive layer serve as a mask for the impurity element imparting n-type conductivity, and second impurity regions 941 and 942 are formed. An impurity element imparting n-type conductivity is added to the second impurity region in a concentration range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . Here, a region having the same concentration range as the second impurity region is also referred to as an n ⁻ region. An impurity element imparting n-type conductivity is added to the third impurity regions 943 and 944 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Here, a region having the same concentration range as the third impurity region is also referred to as an n ⁺ region.

  Next, after removing the resist mask, a new resist mask is formed and a third doping process is performed. Through the third doping treatment, fourth impurity regions 948 and 949 in which an impurity element imparting p-type conductivity is added to the semiconductor layer forming the semiconductor layer forming the p-channel TFT are formed.

In addition, an impurity element imparting p-type conductivity is added to the fourth impurity regions 948 and 949 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Incidentally, in the fourth impurity regions 948,949 area in the preceding step phosphorus (P) has been added ^- is a (n region), the 1.5 the concentration of the impurity element imparting p-type Three times as much is added and the conductivity type is p-type. Here, a region having the same concentration range as the fourth impurity region is also referred to as a p ⁺ region.

  Through the above steps, impurity regions having n-type or p-type conductivity are formed in each semiconductor layer.

  Next, an insulating film (not shown) that covers substantially the entire surface is formed. In this example, a 50 nm-thickness silicon oxide film was formed by plasma CVD. Of course, this insulating film is not limited to the silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

  Next, a step of activating the impurity element added to each semiconductor layer is performed.

  Next, a first interlayer insulating film 916 made of a silicon nitride film is formed and subjected to a heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) to hydrogenate the semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the first interlayer insulating film 916.

  Next, a second interlayer insulating film 917 made of an organic insulating material is formed on the first interlayer insulating film 916. In this embodiment, an acrylic resin film 917 having a film thickness of 1.6 μm is formed by a coating method, and a third interlayer insulating film 918 made of a 300 nm silicon nitride film is laminated by a sputtering method.

  Next, the interlayer insulating films 916, 917, and 918 are selectively etched to form contact holes. Specifically, electrodes 950 to 953 that serve as source wirings or drain electrodes, a connection electrode 923, a first electrode 919, and the like Form. Here, patterning was performed using a laminated film of a Ti film (film thickness: 100 nm), an Al film containing silicon (film thickness: 350 nm), and a Ti film (film thickness: 50 nm) as materials for these electrodes and wirings.

  As described above, the n-channel TFT, the p-channel TFT, and the first electrode 919 can be manufactured.

  The n-channel TFT includes a channel formation region 940, low-concentration impurity regions 941 and 942, and high-concentration impurity regions 943 and 944 as active layers. The gate electrodes 945a and 945b having a two-layer structure overlap with the channel formation region 940 with the gate insulating film 913 interposed therebetween. In addition, the gate electrode 945a, which is wider than the gate electrode 945b, overlaps with the low-concentration impurity region and has a GOLD structure. The high concentration impurity regions 943 and 944 are source regions or drain regions, and 950 and 951 are source electrodes or drain electrodes.

  The p-channel TFT includes a channel formation region 947 and source or drain regions 948 and 949 as active layers. The gate electrodes 946 a and 946 b having a two-layer structure overlap with the channel formation region 947 with the gate insulating film 913 interposed therebetween. Reference numerals 952 and 953 denote source electrodes or drain electrodes.

  An operational amplifier can be formed by appropriately combining the n-channel TFT and the p-channel TFT thus obtained. When the operational amplifier is formed, the power supply VBB is required in addition to the high-potential-side power supply VDD and the low-potential-side power supply VSS, so the number of terminals is five. Therefore, it is desirable to form a level shift circuit. By using the level shift circuit, the number of power supplies can be reduced and four terminals can be provided. In the sensor chip, it is desirable in terms of strength to form connection electrode terminals at four points on the chip and mount them on a printed circuit board or the like. In order to reduce variations, a feedback resistor may be provided, and the output current of the photodiode may be converted into a voltage by the feedback resistor and taken out as a voltage output from the output terminal.

  In this embodiment, the amplifier circuit is described as an operational amplifier (op-amp), but it goes without saying that the amplifier circuit is not limited to an operational amplifier.

  In the subsequent steps, the photoelectric conversion layers 924p, 924i, and 924n, the second electrode 925, the sealing resin 926, and the terminal electrode 927 are formed according to the best mode, and then the transfer process is performed on the film substrate 910. Just do it. The film substrate 910 is bonded with an adhesive layer 911. After the transfer, the optical sensor chip is formed by dividing and then mounted as appropriate.

  In addition, this embodiment can be freely combined with the best mode, embodiment 1, or embodiment 2.

Various electronic devices can be manufactured by incorporating an optical sensor chip obtained by implementing the present invention. Electronic devices include video cameras, digital cameras, goggles-type displays (head-mounted displays), projectors, monitors such as liquid crystal televisions, navigation systems, sound playback devices (car audio, audio components, etc.), notebook-type personal computers, game machines , A portable information terminal (mobile computer, cellular phone, portable game machine, electronic book, etc.), an image playback device equipped with a recording medium (specifically, a playback medium such as a digital versatile disc (DVD), etc.) And the like).

  In this embodiment, an example in which the optical sensor of the present invention is incorporated in an information terminal device represented by a mobile phone or a PDA is shown.

In recent years, the power consumption of lighting such as a backlight has been increasing due to color display of information devices such as mobile phones and PDAs, and improvement of moving image quality. On the other hand, it is required to save power without degrading display quality. Therefore, power consumption is reduced by sensing the illuminance of the environment in which the information device is used, thereby controlling the brightness of the display device and controlling the illumination of the key switch.

FIG. 10A illustrates a mobile phone, which includes a main body 2001, a casing 2002, a display portion 2003, operation keys 2004, an audio output portion 2005, an audio input portion 2006, optical sensor portions 2007, 2008, and the like. The present invention can be applied to the optical sensor units 2007 and 2008. Control the luminance of the display unit 2003 according to the illuminance obtained by the optical sensor unit 2007, or control the illumination of the key switch 2004 according to the illuminance obtained by the optical sensor unit 2008, thereby suppressing current consumption of the mobile phone. Can do.

In the case of a photographing device such as a digital camera or a digital video camera, a visible light detection sensor is provided in the vicinity of the eyepiece (viewing window) of the optical viewfinder to detect whether the photographer has looked into the optical viewfinder. For example, when the photographer's face approaches the viewfinder eyepiece, the area around the eyepiece becomes a shadow of the photographer and the amount of light received by the sensor changes.

FIG. 10B illustrates a digital camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, a viewfinder 2107, an optical sensor portion 2108, and the like. The present invention can be applied to the optical sensor unit 2108. It is detected whether or not the photographer has looked into the optical viewfinder when the amount of sensor light received by the optical sensor unit 2108 provided near the viewfinder 2107 changes. When the photographer is looking into the optical viewfinder, power consumption can be suppressed by turning off the display portion 2102.

  Further, the optical sensor element of the present invention can be used for the purpose of adjusting the convergence of the projector.

  In addition, by mounting the optical sensor of the present invention on a camera (film camera) that does not have a display screen, the shutter is driven at an appropriate shutter speed and aperture value based on the brightness obtained by the optical sensor. Can do. It is possible to prevent a failure photo from being taken by the camera equipped with the optical sensor of the present invention.

  This embodiment can be freely combined with the best mode, embodiment 1, embodiment 2, or embodiment 3.

A single crystal silicon substrate has a size limit and a mass production limit. However, if it is manufactured on an inexpensive glass substrate or a plastic substrate according to the present invention, a large-area substrate, for example, 320 mm × 400 mm, 370 mm × 470 mm, etc. A large number of substrates can be manufactured on a substrate having a size of 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, or 1150 mm × 1300 mm, and the unit cost per unit can be reduced.

Sectional drawing and circuit diagram of the optical sensor apparatus of this invention. Sectional drawing which shows the manufacturing process of an optical sensor apparatus. Sectional drawing which shows the manufacturing process of an optical sensor apparatus. The figure which shows the external shape of the optical sensor apparatus of this invention. The graph which shows the sticking strength of a terminal electrode. The graph which shows an illuminance characteristic. FIG. 3 is a cross-sectional process diagram of the photosensor device showing Example 1. Sectional process drawing of the optical sensor device showing the second embodiment. FIG. 6 is a cross-sectional process diagram of an optical sensor device showing Example 3. FIG. 14 illustrates an example of an electronic device. It is an electrical characteristic (IV characteristic) of the circuit integrated photosensor provided with the amplifier circuit which makes an output value 10 times. The circuit diagram which shows another example of the optical sensor apparatus of this invention.

Explanation of symbols

10: Film substrate 11: Adhesive layer 19: First electrode (cathode side electrode)
23: Second electrode (anode side electrode)

Claims (14)

A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a photoelectric conversion layer made of a semiconductor film having an amorphous structure on the first electrode, and a second electrode on the photoelectric conversion layer,
The amplifying circuit is constituted by a TFT having a semiconductor film having a crystal structure. A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a photoelectric conversion layer made of a crystalline semiconductor film on the first electrode, and a second electrode on the photoelectric conversion layer,
The amplifying circuit is constituted by a TFT having a semiconductor film having a crystal structure. A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a p-type amorphous semiconductor layer partially in contact with the first electrode, and an amorphous structure in contact with the p-type amorphous semiconductor layer. A photoelectric conversion layer made of a semiconductor film, an n-type amorphous semiconductor layer in contact with the photoelectric conversion layer made of the semiconductor film having an amorphous structure, and a second contact in contact with the n-type amorphous semiconductor layer An electrode,
2. The semiconductor device according to claim 1, wherein the amplifier circuit includes an n-channel TFT having a semiconductor film having a crystal structure. A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a p-type amorphous semiconductor layer partially in contact with the first electrode, and an amorphous structure in contact with the p-type amorphous semiconductor layer. A photoelectric conversion layer made of a semiconductor film, an n-type amorphous semiconductor layer in contact with the photoelectric conversion layer made of the semiconductor film having an amorphous structure, and a second contact in contact with the n-type amorphous semiconductor layer An electrode,
The amplifier circuit is constituted by a p-channel TFT having a semiconductor film having a crystal structure. A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element includes a first electrode, a p-type crystalline semiconductor layer partially in contact with the first electrode, and a semiconductor film having an amorphous structure in contact with the p-type crystalline semiconductor layer A photoelectric conversion layer comprising: an n-type crystalline semiconductor layer in contact with the photoelectric conversion layer comprising a semiconductor film having an amorphous structure; and a second electrode in contact with the n-type crystalline semiconductor layer. And
2. The semiconductor device according to claim 1, wherein the amplifier circuit includes an n-channel TFT having a semiconductor film having a crystal structure. A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element includes a first electrode, a p-type crystalline semiconductor layer partially in contact with the first electrode, and a semiconductor film having an amorphous structure in contact with the p-type crystalline semiconductor layer A photoelectric conversion layer comprising: an n-type crystalline semiconductor layer in contact with the photoelectric conversion layer comprising a semiconductor film having an amorphous structure; and a second electrode in contact with the n-type crystalline semiconductor layer. And
The amplifier circuit is constituted by a p-channel TFT having a semiconductor film having a crystal structure. A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a p-type amorphous semiconductor layer partially in contact with the first electrode, and an amorphous structure in contact with the p-type amorphous semiconductor layer. A photoelectric conversion layer made of a semiconductor film, an n-type crystalline semiconductor layer in contact with the photoelectric conversion layer made of a semiconductor film having an amorphous structure, and a second electrode in contact with the n-type crystalline semiconductor layer Have
2. The semiconductor device according to claim 1, wherein the amplifier circuit includes an n-channel TFT having a semiconductor film having a crystal structure. A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element has a first electrode, a p-type amorphous semiconductor layer partially in contact with the first electrode, and an amorphous structure in contact with the p-type amorphous semiconductor layer. A photoelectric conversion layer made of a semiconductor film, an n-type crystalline semiconductor layer in contact with the photoelectric conversion layer made of a semiconductor film having an amorphous structure, and a second electrode in contact with the n-type crystalline semiconductor layer Have
The amplifier circuit is constituted by a p-channel TFT having a semiconductor film having a crystal structure. A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element includes a first electrode, a p-type crystalline semiconductor layer partially in contact with the first electrode, and a semiconductor film having an amorphous structure in contact with the p-type crystalline semiconductor layer A n-type amorphous semiconductor layer in contact with the n-type amorphous semiconductor layer; a n-type amorphous semiconductor layer in contact with the n-type amorphous semiconductor layer; Have
2. The semiconductor device according to claim 1, wherein the amplifier circuit includes an n-channel TFT having a semiconductor film having a crystal structure. A semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
The photosensor element includes a first electrode, a p-type crystalline semiconductor layer partially in contact with the first electrode, and a semiconductor film having an amorphous structure in contact with the p-type crystalline semiconductor layer A n-type amorphous semiconductor layer in contact with the n-type amorphous semiconductor layer; a n-type amorphous semiconductor layer in contact with the n-type amorphous semiconductor layer; Have
The amplifier circuit is constituted by a p-channel TFT having a semiconductor film having a crystal structure.   11. The semiconductor device according to claim 1, wherein the optical sensor element and the amplifier circuit are provided on a plastic substrate via an adhesive layer.   12. The semiconductor device according to claim 1, wherein the external terminal provided on the chip has a two-terminal structure. 13. The semiconductor device according to claim 1, wherein the semiconductor device is a video camera, a digital camera, a goggle type display, a personal computer, or a portable information terminal. In a method for manufacturing a semiconductor device mounted with a chip having an optical sensor element and an amplifier circuit,
Forming a source electrode or a drain electrode connected to a source region or a drain region of a thin film transistor constituting an amplifier circuit, and simultaneously forming a first electrode in contact with the interlayer insulating film of the thin film transistor;
Stacking a first conductive crystalline semiconductor film, an amorphous semiconductor film, and a second conductive crystalline semiconductor film covering the first electrode and the interlayer insulating film;
Forming a second electrode on the second conductive crystalline semiconductor film;
Etching the first conductive crystalline semiconductor film, the amorphous semiconductor film, and the second conductive crystalline semiconductor film in a self-aligning manner using the second electrode as a mask. A method for manufacturing a semiconductor device.