JP2007318094A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably operate an amplifier circuit by adjusting the parasitic resistance in the amplifier circuit through installation of a compensation resistor. <P>SOLUTION: A semiconductor device is provided with a compensation resistor for compensating for the parasitic resistance in a current mirror circuit. The current mirror circuit has at least two thin film transistors. Each of the thin film transistors comprises: a channel formation region; an island-shaped semiconductor film having source or drain regions; a gate insulating film; a gate electrode; and source or drain electrodes. The compensation resistor compensates for the parasitic resistance of any one of the gate electrodes, the source electrode, and the drain electrode. In addition, the compensation resistor has a conductive layer containing the same material as that of the gate electrode, the source or drain electrodes, or the source or drain regions. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a thin film semiconductor element and a method for manufacturing the semiconductor device.

  In general, a current mirror circuit is often used as a part of a power supply circuit such as a display. The power supply circuit is composed of an analog circuit, and the performance of the bias circuit is important for its stable operation. When designing a high-performance analog circuit or a low-voltage operation circuit, it is important to design a bias circuit.

Some conventional amplifier circuits have improved performance by multistage connection of thin film transistors (TFTs) (see, for example, Patent Document 1).
JP-A-6-37558

  Many conventional amplifier circuits have a multi-stage configuration including a correction circuit, and a large power supply voltage is required. In order to construct an electric circuit, it is necessary to stably supply a power supply voltage from various aspects such as energy saving and high performance.

  However, an amplifier circuit constituted by the TFT as described above has a problem that its operation becomes unstable due to a parasitic resistance due to a wiring layer constituting the TFT and a wiring resistance or a contact resistance of a wiring connected thereto. It was.

  The cause of the unstable operation of the amplifier circuit is that the conductive layer constituting the TFT and the wiring connected to the TFT are made of different materials, or the width and length thereof are different. It can be mentioned that the values are different from each other, and the balance of parasitic resistance in each TFT constituting the amplifier circuit is deteriorated.

  When the operation of the amplifier circuit becomes unstable, the output current value becomes unstable. This is because TFTs constituting the circuit operate in a region that is easily affected by characteristic variations.

  The semiconductor device of the present invention includes a resistor and an amplifier circuit, and adjusts the parasitic resistance value in the amplifier circuit by adding a resistor, thereby stably operating the amplifier circuit. That is, by forming a correction resistor corresponding to the parasitic resistance value in the amplifier circuit and balancing the resistance, a stable operation is enabled. Thereby, the output in the substrate plane can be made constant in the semiconductor device.

  Note that in this specification, a semiconductor device refers to a device including a semiconductor layer, and an entire device including an element including a semiconductor layer is also referred to as a semiconductor device.

  The present invention relates to a semiconductor device having a function of reducing a power supply voltage and operating an amplifier circuit stably.

  The present invention relates to a semiconductor device characterized in that a correction resistor for correcting the parasitic resistance is provided for the parasitic resistance in the current mirror circuit in a current mirror circuit.

  In the present invention, the current mirror circuit has at least two thin film transistors.

  In the present invention, the thin film transistor includes an island-shaped semiconductor film having a channel formation region, a source region or a drain region, a gate insulating film, a gate electrode, a source electrode or a drain electrode, and the correction resistor includes the gate electrode This is to correct the parasitic resistance.

  In the present invention, the thin film transistor includes an island-shaped semiconductor film having a channel formation region, a source region or a drain region, a gate insulating film, a gate electrode, a source electrode or a drain electrode, and the correction resistor includes the source electrode This is to correct the parasitic resistance.

  In the present invention, the thin film transistor includes an island-shaped semiconductor film having a channel formation region, a source region or a drain region, a gate insulating film, a gate electrode, a source electrode or a drain electrode, and the correction resistor includes the drain electrode This is to correct the parasitic resistance.

  The present invention includes a first transistor including a gate electrode, a source electrode, and a drain electrode, a second transistor including a gate electrode, a source electrode, and a drain electrode, a drain electrode of the first transistor, a second transistor, A first terminal electrically connected to the drain electrode of the first transistor, a source electrode of the first transistor, and a second terminal electrically connected to the source electrode of the second transistor, The gate electrode of the first transistor is connected to the gate electrode of the second transistor through a contact, and the gate electrode of the first transistor is electrically connected to the drain electrode of the first transistor. Connected from the first terminal to the second terminal through the drain electrode of the first transistor and the source electrode of the first transistor A resistance value of a first path that is a path and a second path that is a path from the first terminal to the second terminal through the drain electrode of the second transistor and the source electrode of the second transistor. A correction resistor is formed in one or both of the first path and the second path so that the resistance values of the paths of the first and second paths are the same, and is a path from the gate electrode of the first transistor to the contact. The third path or the fourth path so that the resistance value of the third path is the same as the resistance value of the fourth path that is the path from the gate electrode of the second transistor to the contact point. The present invention relates to a semiconductor device characterized in that a correction resistor is formed on one or both of the above.

  In the present invention, the correction resistor has a wiring containing the same material as the gate electrode.

  In the present invention, the correction resistor has a wiring containing the same material as the source electrode or the drain electrode.

  In the present invention, the correction resistor has a wiring containing the same material as the source region or the drain region.

  In the present invention, the parasitic resistance of the electrode includes the contact resistance of the electrode and the wiring resistance connected to the electrode.

  The semiconductor device of the present invention has a function of stably operating the amplifier circuit by correcting various parasitic resistance values with additional resistors. A stable amplifier circuit can make the operating voltage of the bias circuit uniform, and can make the electrical characteristics of the circuit uniform, so that a more accurate product can be supplied.

  This embodiment is shown in FIGS. 1, 2, 3, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12A to 12B. This will be described below with reference to FIGS. 13A to 13B, FIGS. 14A to 14B, FIG. 43, and FIG.

  However, it will be readily understood by those skilled in the art that the present invention can be implemented in many different modes, and that various modifications can be made without departing from the spirit and scope of the present invention. The Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

  Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

  The current mirror circuit shown in FIG. 1 includes at least two TFTs, a reference side TFT and an output side TFT. In order to stabilize the output of the current mirror circuit, by appropriately controlling the resistance values corresponding to the resistances of the drain side and the source side of the reference side TFT and the output side TFT, circuit characteristic fluctuations within the substrate plane can be controlled. Control.

  A current mirror circuit composed of n-channel TFTs is composed of a reference-side TFT 104 and an output-side TFT 105 (see FIG. 1). By applying the same voltage to the gate portions of the reference TFT 104 and the output TFT 105 with the terminal 103 as a reference, the current flowing in the output TFT 105 is controlled based on the current flowing in the reference TFT 104.

  At this time, the parasitic resistance 106 and the parasitic resistance 109 corresponding to the resistance of the gate part of the TFT 104 on the reference side and the TFT 105 on the output side, and the parasitic resistance 107 and the parasitic resistance 110 and the parasitic resistance 108 corresponding to the drain resistance and the source resistance are provided. If the parasitic resistance 111 is not uniform due to wiring resistance or circuit connection resistance, even if the same voltage is applied to the gate portion of the reference side TFT 104 and the output side TFT 105, the current flows to the reference side TFT 104 as designed. As a result, the same amount of current cannot be passed through the TFT 105 on the output side, causing the output current amount to have a different value from the intended purpose. This is particularly noticeable when there are a plurality of each of the reference side TFT 104 and the output side TFT 105.

  In order to correct this, the present invention appropriately controls the resistance values corresponding to the gate part, the drain part, and the source part of the TFT 104 on the reference side and the TFT 105 on the output side.

  Further, in order to reduce the variation in TFT characteristics while realizing the low voltage operation of the amplifier circuit, a description will be given using a single-stage current mirror amplifier circuit.

  As shown in FIG. 1, the semiconductor device of this embodiment includes a current mirror circuit 122 including transistors 104 and 105, a power supply (bias) 101, a terminal 123, and a circuit 123 including a terminal 103. The transistors 104 and 105 have parasitic resistances 106 to 111, and have resistances 112 to 117 for correcting them. In this specification, the resistance for correcting the parasitic resistance in this way is also referred to as “correction resistance”. In this embodiment mode, thin film transistors (TFTs) are used as the transistors 104 and 105, and the TFTs 104 and 105 are n-channel TFTs. Each of the correction resistors 112 to 117 corrects any one of the parasitic resistance of the TFT gate electrode, the parasitic resistance of one of the source electrode and the drain electrode, and the other parasitic resistance of the source electrode or the drain electrode.

  Note that the parasitic resistance of the gate electrode, the parasitic resistance of one of the source electrode or the drain electrode, and the parasitic resistance of the other of the source electrode or the drain electrode include the contact resistance of the electrode and the wiring resistance connected to the electrode, respectively. It is.

By the way, as a method of extracting the output signal format as a voltage, which is generally said to be easy to perform signal processing, there is a method of converting the output signal format into a voltage by a load resistor _RL . Specifically, as shown in FIG. 4, the conversion circuit 123, a power supply 125 which includes a current mirror circuit 122, an output terminal 124, the circuit having a load resistor _{R L,} the output current using a load resistance _{R L} to the voltage Thus, an output signal can be taken out as a voltage at the output terminal 124. A circuit in which the circuit 123 including the current mirror circuit 122 of FIG. 1 is incorporated in the circuit of FIG. 4 will be described below.

  In FIG. 1, the gate electrode of the TFT 104 constituting the current mirror circuit 122 is connected to another TFT 105 constituting the current mirror circuit 122 via the parasitic resistance 106 of the TFT 104, the parasitic resistance 109 of the TFT 105, the resistance 112, and the resistance 115. Is further electrically connected to the drain electrode (also referred to as “drain terminal”) which is one of the source electrode and the drain electrode of the TFT 104 via the parasitic resistor 106 and the resistor 112 of the TFT 104. Has been.

  The drain terminal of the TFT 104 is electrically connected to the terminal 102 via the parasitic resistor 107 and the resistor 113 of the TFT 104, and further via the parasitic resistor 107 of the TFT 104, the parasitic resistor 110 of the TFT 105, the resistor 113, and the resistor 116. Are electrically connected to the drain terminal of the TFT 105.

  A source electrode (also referred to as “source terminal”) which is the other of the source electrode and the drain electrode of the TFT 104 is electrically connected to the terminal 103 via the parasitic resistance 108 and the resistance 114 of the TFT 104, and further the parasitic resistance of the TFT 104. 108, the parasitic resistance 111 of the TFT 105, the resistance 114, and the resistance 117 are electrically connected to the source terminal of the TFT 105.

In the present embodiment, the terminal 103 of the circuit 123 including the current mirror circuit 122 is electrically connected to the low potential side of the power supply 125 through the load resistor _RL . At this time, the power supply 101 in the circuit 123 including the current mirror circuit 122 can be omitted.

  In FIG. 1, the gate electrode of the TFT 105 constituting the current mirror circuit 122 is electrically connected to the drain terminal of the TFT 104 via the parasitic resistance 109 and the resistance 115 of the TFT 105. The drain terminal of the TFT 105 is electrically connected to the terminal 102 via the parasitic resistance 110 and the resistance 116 of the TFT 105. The source terminal of the TFT 105 is electrically connected to the terminal 103 via the parasitic resistance 111 and the resistance 117 of the TFT 105.

  Further, since the gate electrodes of the TFTs 104 and 105 are connected to each other, a common potential is applied.

  FIG. 1 illustrates an example of a current mirror circuit using two TFTs. At this time, when 104 and 105 have the same characteristics, the ratio of the reference current and the output current is 1: 1.

  Circuit configurations for increasing the output value by n are shown in FIGS. The circuit configuration in FIG. 2 corresponds to the n TFTs 105 in FIG. As shown in FIG. 2, by setting the ratio of the n-channel TFT 104 and the n-channel TFT 105 to 1: n, the output value can be increased by n times. This is the same principle as increasing the channel width W of the TFT and increasing the allowable amount of current that can be passed through the TFT n times.

  For example, when designing the output value to be 100 times, a target current can be obtained by connecting one n-channel TFT 104 and 100 n-channel TFTs 105 in parallel.

  FIG. 3 shows a detailed circuit configuration of the circuit 118i (circuit 118a, circuit 118b, etc.) in FIG.

  The circuit configuration of FIG. 3 is based on the circuit configuration of FIG. 1, and the same elements are denoted by the same reference numerals. That is, the gate electrode of the TFT 105i is electrically connected to the terminal 119i through the parasitic resistor 109i and the resistor 115i. The drain terminal of the TFT 105i is electrically connected to the terminal 120i through the parasitic resistance 110i and the resistance 116i. The source terminal of the TFT 105i is electrically connected to the terminal 121i through a parasitic resistor 111i and a resistor 117i.

  Note that in order to describe the circuit 118a, the circuit 118b, and the like in FIG. 2, a circuit 118i, which is one of them, is shown in FIG. Since the circuit 118i is based on the circuit configuration of FIG. 1, the reference numerals with “i” in the reference numerals in FIG. 3 are the same as the reference numerals without “i” in FIG. That is, for example, the TFT 105 in FIG. 1 and the TFT 105i in FIG. 3 are the same, and the resistor 116 in FIG. 1 and the 116i in FIG. 3 are the same. Furthermore, in FIG. 2, the reference numerals with “a” and “b” are the same as the reference numerals without “a” and “b” in FIG. 1, respectively.

  Therefore, in FIG. 2, the n-channel TFT 105 is composed of n n-channel TFTs 105a, 105b, 105i, and the like. As a result, the current flowing through the TFT 104 is amplified n times and output.

  2 and 3, the same reference numerals are used to indicate the same components as those in FIG.

  1 illustrates the current mirror circuit 122 as an equivalent circuit using an n-channel TFT, but a p-channel TFT may be used instead of the n-channel TFT.

When the amplifier circuit is formed of a p-channel TFT, an equivalent circuit shown in FIG. 5 is obtained. As shown in FIG. 5, the current mirror circuit 203 composed of p-channel TFTs 201 and 202, the terminal 102 is electrically connected to the high potential side of the power source 101, and the terminal 103 is connected to the power source via the load resistor _RL. It is electrically connected to the low potential side of 101. When the circuit 204 including the current mirror circuit 203 is used as the circuit 123 in FIG. 4, the power supply 101 in the circuit 204 can be replaced with the power supply 125.

  6 to 11 are sectional views of the circuit 123 including the correction resistors 112 to 117 and the TFTs 104 and 105 in FIG.

  6 to 11, reference numeral 210 denotes a substrate, 212 denotes a base insulating film, and 213 denotes a gate insulating film.

  The connection electrode 285, the terminal electrode 281, the source electrode or drain electrode 282 of the TFT 104, and the source electrode or drain electrode 283 of the TFT 105 are stacked layers of a refractory metal film and a low resistance metal film (such as an aluminum alloy or pure aluminum). It has a structure. Here, the source or drain electrodes 282 and 283 have a three-layer structure in which a titanium film (Ti film), an aluminum film (Al film), and a Ti film are sequentially stacked.

  In FIG. 6, the wiring 400 and the wiring 401, the wiring 410 and the wiring 411, the wiring 420 and the wiring 421, the wiring 430 and the wiring 431, the wiring 440 and the wiring 441, the wiring 450 and the wiring 451 each form one resistance. . This one resistor corresponds to any one of the resistors 112 to 117 in FIG. That is, any one of the combinations of the wiring 400 and the wiring 401, the wiring 410 and the wiring 411, the wiring 420 and the wiring 421, the wiring 430 and the wiring 431, the wiring 440 and the wiring 441, the wiring 450 and the wiring 451 is any of the resistors 112 to 117. It corresponds to one.

  The wiring 400, the wiring 410, the wiring 420, the wiring 430, the wiring 440, and the wiring 450 are formed using the same material and the same process as the gate electrodes of the TFTs 104 and 105.

  The wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451 are formed using the same material and the same process as the source or drain electrode 282 (or 283).

  In FIG. 7, the wiring 400, the wiring 410, the wiring 420, the wiring 430, the wiring 440, and the wiring 450 are each one resistor and correspond to any one of the resistors 112 to 117 in FIG. 1.

  The wiring 400, the wiring 410, the wiring 420, the wiring 430, the wiring 440, and the wiring 450 are formed using the same material and the same process as the gate electrodes of the TFTs 104 and 105.

  In FIG. 8, a wiring 403 and a wiring 404, a wiring 413 and a wiring 414, a wiring 423 and a wiring 424, a wiring 433 and a wiring 434, a wiring 443 and a wiring 444, a wiring 453 and a wiring 454 each form one resistor. . This one resistor corresponds to any one of the resistors 112 to 117 in FIG. That is, any one of the combinations of the wiring 403 and the wiring 404, the wiring 413 and the wiring 414, the wiring 423 and the wiring 424, the wiring 433 and the wiring 434, the wiring 443 and the wiring 444, the wiring 453 and the wiring 454 is the resistance 112 to the resistance 117. It corresponds to any one.

  The wiring 403, the wiring 413, the wiring 423, the wiring 433, the wiring 443, and the wiring 453 are formed using the same material and the same process as the source region or the drain region of the TFTs 104 and 105.

  The wiring 404, the wiring 414, the wiring 424, the wiring 434, the wiring 444, and the wiring 454 are formed using the same material and the same process as the source or drain electrode 282 (or the source or drain electrode 283).

  9, each of the wiring 403, the wiring 413, the wiring 423, the wiring 433, the wiring 443, and the wiring 453 is one resistor, and corresponds to any one of the resistors 112 to 117 in FIG.

  The wiring 403, the wiring 413, the wiring 423, the wiring 433, the wiring 443, and the wiring 453 are formed using the same material and the same process as the source region or the drain region of the TFTs 104 and 105.

  In FIG. 10, the wiring 405 and the wiring 406, the wiring 415 and the wiring 416, the wiring 425 and the wiring 426, the wiring 435 and the wiring 436, the wiring 445 and the wiring 446, the wiring 455 and the wiring 456 each form one resistance. . This one resistor corresponds to any one of the resistors 112 to 117 in FIG. That is, any one of the combinations of the wiring 405 and the wiring 406, the wiring 415 and the wiring 416, the wiring 425 and the wiring 426, the wiring 435 and the wiring 436, the wiring 445 and the wiring 446, the wiring 455 and the wiring 456 has the resistance 112 to the resistance 117. It corresponds to any one.

  In FIG. 10, a wiring 405, a wiring 415, a wiring 425, a wiring 435, a wiring 445, and a wiring 455 are formed using the same material and the same process as the source region or the drain region of the TFTs 104 and 105.

  The wiring 406, the wiring 416, the wiring 426, the wiring 436, the wiring 446, and the wiring 456 are formed using the same material and the same process as the gate electrodes of the TFTs 104 and 105.

  In FIG. 11, a wiring 407, a wiring 417, a wiring 427, a wiring 437, a wiring 447, and a wiring 457 are each one resistor and correspond to any one of the resistors 112 to 117 in FIG. 1.

  The wiring 407, the wiring 417, the wiring 427, the wiring 437, the wiring 447, and the wiring 457 are formed using the same material and the same process as the source or drain electrode 282 (or the source or drain electrode 283).

In FIG. 6, the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451 have a laminated structure of a refractory metal film and a low resistance metal film.

  In FIG. 8, the wiring 404, the wiring 414, the wiring 424, the wiring 434, the wiring 444, and the wiring 454 have a laminated structure of a refractory metal film and a low resistance metal film.

  In FIG. 11, the wiring 407, the wiring 417, the wiring 427, the wiring 437, the wiring 447, the wiring 457, and a stacked structure of a refractory metal film and a low resistance metal film are formed.

  6 to 11, the connection electrode 285, the terminal electrode 281, the source electrode or drain electrode 282 of the TFT 104, and the source electrode or drain electrode 283 of the TFT 105 have a laminated structure of a refractory metal film and a low resistance metal film. It has become.

  Examples of such a low resistance metal film include an aluminum alloy or pure aluminum. In the present embodiment, a three-layer structure in which a titanium film (Ti film), an aluminum film (Al film), and a Ti film are sequentially stacked as a laminated structure of such a refractory metal film and a low-resistance metal film, To do.

  Further, instead of the laminated structure of the refractory metal film and the low resistance metal film, a single-layer conductive film can be used. As such a single-layer conductive film, titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), neodymium (Nd), cobalt (Co), zirconium (Zr), zinc (Zn), An element selected from ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), or an alloy material or a compound material containing the element as a main component A single-layer film or a single-layer film made of these nitrides, for example, titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride can be used.

Thus, the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, the wiring 451, the wiring 404, the wiring 414, the wiring 424, the wiring 434, the wiring 444, the wiring 454, the wiring 407, the wiring 417, the wiring 427, the wiring 437, the wiring 447, the wiring 457, the connection electrode 285, the terminal electrode 281, the source electrode or drain electrode 282 of the TFT 104, and the source electrode or drain electrode 283 of the TFT 105 are formed as a single layer film, so that the number of film formations can be increased. It becomes possible to decrease.

  A layout example of the wiring 400 and the wiring 401, the wiring 410 and the wiring 411, the wiring 420 and the wiring 421, the wiring 430 and the wiring 431, the wiring 440 and the wiring 441, the wiring 450 and the wiring 451 in FIG. Show.

  A layout example of the wiring 400, the wiring 410, the wiring 420, the wiring 430, the wiring 440, and the wiring 450 in FIG. 7 is illustrated in FIG.

  A layout example of the wiring 403 and wiring 404, the wiring 413 and wiring 414, the wiring 423 and wiring 424, the wiring 433 and wiring 434, the wiring 443 and wiring 444, the wiring 453 and the wiring 454 in FIG. 8 is shown in FIG. Show.

  A layout example of the wiring 403, the wiring 413, the wiring 423, the wiring 433, the wiring 443, and the wiring 453 in FIG. 9 is illustrated in FIG.

  14A shows a layout example of the wiring 405 and the wiring 406, the wiring 415 and the wiring 416, the wiring 425 and the wiring 426, the wiring 435 and the wiring 436, the wiring 445 and the wiring 446, the wiring 455 and the wiring 456 in FIG. Show.

  FIG. 14B shows a layout example of the wiring 407, the wiring 417, the wiring 427, the wiring 437, the wiring 447, and the wiring 457 in FIG.

  12A is a top view of one resistor. In FIG. 6, the wiring 400 and the wiring 401, the wiring 410 and the wiring 411, the wiring 420 and the wiring 421, the wiring 430 and the wiring 431, the wiring 440 and the wiring 441, and the wiring 450 and the wiring 451 respectively.

  Each of the wiring 400, the wiring 410, the wiring 420, the wiring 430, the wiring 440, and the wiring 450 in FIG. 6 corresponds to the wiring 470 in FIG. Each of the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451 corresponds to the wiring 471 in FIG.

  12B is a top view of one resistor, and the wiring 472 corresponds to each of the wiring 400, the wiring 410, the wiring 420, the wiring 430, the wiring 440, and the wiring 450 in FIG.

  13A is a top view of one resistor. The wiring 403 and the wiring 404, the wiring 413 and the wiring 414, the wiring 423 and the wiring 424, the wiring 433 and the wiring 434, the wiring 443 and the wiring 444, and the wiring in FIG. 453 and wiring 454 respectively.

  Each of the wiring 403, the wiring 413, the wiring 423, the wiring 433, the wiring 443, and the wiring 453 in FIG. 8 corresponds to the wiring 473 in FIG. Each of the wiring 404, the wiring 414, the wiring 424, the wiring 434, the wiring 444, and the wiring 454 corresponds to the wiring 474 in FIG.

  13B is a top view of one resistor, and the wiring 475 corresponds to each of the wiring 403, the wiring 413, the wiring 423, the wiring 433, the wiring 443, and the wiring 453 in FIG.

  14A is a top view of one resistor. The wiring 405 and the wiring 406, the wiring 415 and the wiring 416, the wiring 425 and the wiring 426, the wiring 435 and the wiring 436, the wiring 445 and the wiring 446, and the wiring in FIG. 455 and the wiring 456 respectively.

  Each of the wiring 405, the wiring 415, the wiring 425, the wiring 435, the wiring 445, and the wiring 455 in FIG. 10 corresponds to the wiring 476 in FIG. In addition, each of the wiring 406, the wiring 416, the wiring 426, the wiring 436, the wiring 446, and the wiring 456 corresponds to the wiring 477 in FIG.

  FIG. 14B is a top view of one resistor, and the wiring 478 corresponds to each of the wiring 407, the wiring 417, the wiring 427, the wiring 437, the wiring 447, and the wiring 457 in FIG.

  Note that each of the resistors 112 to 117 in FIG. 1 does not have to have the same configuration, and a resistor having a different configuration among the resistors illustrated in FIGS. 6 to 11 may be formed as necessary. For example, in order to form the circuit 123 of FIG. 1, the resistor 112 may have the configuration of the wiring 403 and the wiring 404 shown in FIG. 8, and the resistor 113 may have the configuration of the wiring 400 shown in FIG.

  In FIGS. 6 to 11, n-channel TFTs 104 and 105 are examples of top gate TFTs having a structure including one channel formation region (referred to as “single gate structure” in this specification). Variation in on-state current value may be reduced by using a structure having a plurality of formation regions.

  Further, in order to reduce the off-current value, a lightly doped drain (LDD) region may be provided in the n-channel TFTs 104 and 105. An LDD region is a region in which an impurity element is added at a low concentration between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration. When the LDD region is provided, This has the effect of relaxing the electric field in the vicinity of the drain region and preventing deterioration due to hot carrier injection.

  In addition, in order to prevent deterioration of the on-current value due to hot carriers, n-channel TFTs 104 and 105 have a structure in which an LDD region is overlapped with a gate electrode through a gate insulating film (in this specification, “GOLD (Gate− (Drain Overlapped LDD) structure ”).

  When the GOLD structure is used, the electric field in the vicinity of the drain region is further relaxed and the deterioration due to hot carrier injection is prevented as compared with the case where the GOLD structure is not overlapped with the LDD region gate electrode. By adopting such a GOLD structure, the electric field strength in the vicinity of the drain region is relaxed and hot carrier injection is prevented, which is effective in preventing a deterioration phenomenon.

  The TFTs 104 and 105 constituting the current mirror circuit 122 may be not only a top gate type TFT but also a bottom gate type TFT, for example, an inverted stagger type TFT.

  The wiring 215 is connected to a drain wiring (also referred to as a drain electrode) or a source wiring (also referred to as a source electrode) of the TFT 104. Reference numerals 216 and 217 denote insulating films, and reference numeral 285 denotes a connection electrode. Note that the insulating film 217 is preferably a silicon oxide film formed by a CVD method. When the insulating film 217 is a silicon oxide film formed by a CVD method, the fixing strength is improved.

  The terminal electrode 250 is formed in the same process as the wiring 215, and the terminal electrode 281 is formed in the same process as the connection electrode 285.

  The terminal electrode 221 is mounted on the electrode 261 of the substrate 260 with solder 264. The terminal electrode 222 is formed in the same process as the terminal electrode 221 and is mounted on the electrode 262 of the substrate 260 with solder 263.

  In FIG. 6, the wiring 400 is connected to the gate electrode of the TFT 104. A wiring 401 formed in the same process as the connection electrode 285 is connected to the drain electrode of the TFT 104.

  Further, the wiring 410 is connected to the drain electrode of the TFT 104. The wiring 411 is connected to the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 420 is connected to the source electrode of the TFT 104. The wiring 421 is connected to the terminal 103 of the circuit 123 including the current mirror circuit 122.

  The wiring 430 is connected to the gate electrode of the TFT 105. The wiring 431 is connected to the gate electrode of the TFT 104 through the wiring 400 and the wiring 401.

  The wiring 440 is connected to the drain electrode of the TFT 105. The wiring 441 is connected to the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 450 is connected to the source electrode of the TFT 105. The wiring 451 is connected to the terminal 103 of the circuit 123 including the current mirror circuit 122.

  In FIG. 7, the wiring 400 is connected to the gate electrode of the TFT 104 and the drain electrode of the TFT 104.

  The wiring 410 is connected to the drain electrode of the TFT 104 and the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 420 is connected to the source electrode of the TFT 104 and the terminal 103 of the circuit 123 including the current mirror circuit 122.

  The wiring 430 is connected to the gate electrode of the TFT 104 through the gate electrode of the TFT 105 and the wiring 400.

  The wiring 440 is connected to the drain electrode of the TFT 105 and the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 450 is connected to the source electrode of the TFT 105 and the terminal 103 of the circuit 123 including the current mirror circuit 122.

  In FIG. 8, the wiring 403 is connected to the gate electrode of the TFT 104. The wiring 404 is connected to the drain electrode of the TFT 104.

  The wiring 413 is connected to the drain electrode of the TFT 104. The wiring 414 is connected to the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 423 is connected to the source electrode of the TFT 104. The wiring 424 is connected to the terminal 103 of the circuit 123 including the current mirror circuit 122.

  The wiring 433 is connected to the gate electrode of the TFT 105. The wiring 434 is connected to the gate electrode of the TFT 104 through the wiring 403 and the wiring 404.

  The wiring 443 is connected to the drain electrode of the TFT 105. The wiring 444 is connected to the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 453 is connected to the source electrode of the TFT 105. The wiring 454 is connected to the terminal 103 of the circuit 123 including the current mirror circuit 122.

  In FIG. 9, the wiring 403 is connected to the gate electrode of the TFT 104 and the drain electrode of the TFT 104.

  The wiring 413 is connected to the drain electrode of the TFT 104 and the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 423 is connected to the source electrode of the TFT 104 and the terminal 103 of the circuit 123 including the current mirror circuit 122.

  A wiring 433 formed in the same process as the wiring 215 is connected to the gate electrode of the TFT 105 and the gate electrode of the TFT 104.

  The wiring 443 is connected to the drain electrode of the TFT 105 and the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 453 is connected to the source electrode of the TFT 105 and the terminal 103 of the circuit 123 including the current mirror circuit 122.

  In FIG. 10, the wiring 405 is connected to the gate electrode of the TFT 104, and the wiring 406 is connected to the drain electrode of the TFT 104.

  The wiring 415 is connected to the drain electrode of the TFT 104, and the wiring 416 is connected to the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 425 is connected to the source electrode of the TFT 104, and the wiring 426 is connected to the terminal 103 of the circuit 123 including the current mirror circuit 122.

  The wiring 435 is connected to the gate electrode of the TFT 105, and the wiring 436 is connected to the gate electrode of the TFT 104 through the wiring 405 and the wiring 406.

  The wiring 445 is connected to the drain electrode of the TFT 105, and the wiring 446 is connected to the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 455 is connected to the source electrode of the TFT 105, and the wiring 456 is connected to the terminal 103 of the circuit 123 including the current mirror circuit 122.

  In FIG. 11, the wiring 407 is connected to the gate electrode of the TFT 104 and the drain electrode of the TFT 104.

  The wiring 417 is connected to the drain electrode of the TFT 104 and the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 427 is connected to the source electrode of the TFT 104 and the terminal 103 of the circuit 123 including the current mirror circuit 122.

  The wiring 437 is connected to the gate electrode of the TFT 105 and the gate electrode of the TFT 104.

  The wiring 447 is connected to the drain electrode of the TFT 105 and the terminal 102 of the circuit 123 including the current mirror circuit 122.

  The wiring 457 is connected to the source electrode of the TFT 105 and the terminal 103 of the circuit 123 including the current mirror circuit 122.

  44 is a circuit diagram of the terminal 102, the terminal 103, the TFT 104, the TFT 105, and the resistors 112 to 117 in FIG. 1, and FIG. 43 is a top view of FIG. In addition, the same thing as FIG. 1 is shown with the same code | symbol.

  43 and 44, the terminal 102 is α, the drain terminal of the TFT 104 is β, the source terminal of the TFT 104 is γ, the gate electrode of the TFT 104 is φ, the drain terminal of the TFT 105 is β ′, the source terminal of the TFT 105 is γ ′, The gate electrode of the TFT 105 is φ ′, the terminal 103 is δ, and the contact point between the resistor 112 and the resistor 115 is ε.

  The resistors 112 to 117 in FIG. 43 correspond to the resistors in FIGS. 10 and 14A. The wirings 141, 142, and 143 are formed using the same material and the same process as the source or drain region of the TFT. The wirings 151 to 156 are formed using the same material and the same process as the source electrode or the drain electrode.

  As shown in FIG. 43, the number of wirings (wirings 141, 142, 143) formed of the same material as the source region or the drain region of the TFT is different in the resistors 112-117. This is because the parasitic resistors 106 to 111 have different resistance values.

  More specifically, for example, the resistor 112 is formed with the wiring 141, but the resistor 115 is not formed with any wiring made of the same material as the source region or the drain region. When wiring is formed with the same material as the source or drain region, the resistance value increases accordingly, so the resistance value is balanced by the number of wirings formed with the same material as the source or drain region. is there. That is, in the resistor 112, the resistance value is increased by the amount of the wiring 141 to balance the resistance value.

  That is, the resistance value of the parasitic resistance 106 and the resistance 112 between φ and ε needs to be equal to the resistance value of the parasitic resistance 109 and the resistance 115 between φ ′ and ε. At this time, since the parasitic resistance 109 is higher than the parasitic resistance 106 between φ and ε between φ ′ and ε by the amount of the wiring 161, the resistance value is adjusted by forming the wiring 141 in the resistor 112.

  As described above, the resistance values of the resistors 112 to 117 can be adjusted by changing the configuration.

  In the present invention, the resistance value between α-β-γ-δ and the resistance value between α-β'-γ'-δ are the same, and the resistance value between φ-ε and between φ'-ε It is important for the current mirror circuit 122 to stably operate that the resistance values of the current mirror circuit 122 are the same.

  43 and 44, the configurations of FIGS. 10 and 14A are used, but FIGS. 6 to 9 and 11 and FIGS. 12A to 12B and 13 (FIG. It goes without saying that resistors having the configurations of A) to FIGS. 13B and 14B may be used.

  Note that this embodiment mode can be combined with any description in the embodiments if necessary.

  When this embodiment is applied to a semiconductor device including a photoelectric conversion device, FIGS. 15, 16, 17A to 17C, 18A to 18C, and 19 are used. This will be described with reference to FIGS. 19A to 19B, FIGS. 20A to 20C, and FIG. In addition, the same thing as what was demonstrated in "the best form for inventing" is shown with the same code | symbol.

  First, an element is formed over a substrate (first substrate 210). Here, AN100 which is one of glass substrates is used as the substrate 210.

  Next, a silicon oxide film (thickness: 100 nm) containing nitrogen is formed as a base insulating film 212 by plasma CVD, and further a semiconductor film such as an amorphous silicon film (thickness: 54 nm) containing hydrogen without being exposed to the atmosphere. Are stacked. Alternatively, the base insulating film 212 may be stacked using a silicon oxide film, a silicon nitride film, or a silicon oxide film containing nitrogen. For example, a film in which a silicon nitride film containing oxygen is stacked with a thickness of 50 nm and a silicon oxide film containing nitrogen is stacked with a thickness of 100 nm may be formed as the base insulating film 212. Note that the silicon oxide film or silicon nitride film containing nitrogen functions as a blocking layer for preventing diffusion of impurities such as alkali metal from the glass substrate.

  Next, the amorphous silicon film is crystallized by a solid phase growth method, a laser crystallization method, a crystallization method using a catalytic metal, or the like, so that a semiconductor film having a crystal structure (crystalline semiconductor film), for example, polycrystalline A silicon film is formed. Here, a polycrystalline silicon film is obtained by a crystallization method using a catalytic element. A solution containing 10 ppm of nickel in terms of weight is added to the surface of the amorphous silicon film using a spinner. Instead of adding with a spinner, a method of spreading nickel element over the entire surface by sputtering may be used. Next, heat treatment is performed for crystallization to form a semiconductor film having a crystal structure (here, a polycrystalline silicon film). Here, after heat treatment (500 ° C., 1 hour), heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a polycrystalline silicon film.

  Next, the oxide film on the surface of the polycrystalline silicon film is removed with dilute hydrofluoric acid or the like. Thereafter, laser beam irradiation is performed to increase the crystallization rate and repair defects remaining in the crystal grains.

  Note that when an amorphous silicon film is crystallized by a laser crystallization method to obtain a crystalline semiconductor film, or after obtaining a semiconductor film having a crystal structure, laser irradiation is performed to repair defects remaining in crystal grains. When performing, the laser irradiation method described below may be used.

Laser irradiation can be performed using a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam). Laser beams that can be used here are gas lasers such as Ar laser, Kr laser, and excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) ) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ and one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta as dopants. Lasers oscillated from one or more of lasers, glass lasers, ruby lasers, alexandrite lasers, Ti: sapphire lasers, copper vapor lasers or gold vapor lasers can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonic laser beams of these fundamental waves, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. In this case, a power density of the laser is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants A laser, Ar ion laser, Kr ion laser, or Ti: sapphire laser with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as a medium is continuous. Oscillation can be performed, and pulse oscillation can also be performed at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser beam to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

  When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

  Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is a single crystal or a polycrystal, there is a certain limit to improving the laser output by increasing the concentration. However, in the case of ceramic, the size of the medium can be remarkably increased as compared with the single crystal, so that the output may be greatly improved.

  Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. As a result, amplification is increased and oscillation can be performed with high output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, it is possible to easily obtain a linear beam having a short side length of 1 mm or less and a long side length of several mm to several m. Become. In addition, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the long side direction.

  By irradiating the semiconductor film with this linear beam, the entire surface of the semiconductor film can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to arrange a slit at both ends to shield the energy attenuating portion.

  Note that in the case where laser irradiation is performed in the air or an oxygen atmosphere, an oxide film is formed on the surface by laser beam irradiation.

  Next, in addition to the oxide film formed by the laser beam irradiation, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total thickness of 1 to 5 nm. This barrier layer is formed to remove a catalyst element added for crystallization, for example, nickel (Ni) from the film. Here, the barrier layer is formed using ozone water, but the surface of the semiconductor film having a crystal structure is oxidized by a method of oxidizing the surface of the semiconductor film having a crystal structure by irradiation with ultraviolet light in an oxygen atmosphere or the oxygen plasma treatment. The barrier layer may be formed by depositing an oxide film of about 1 to 10 nm by a method, plasma CVD method, sputtering method or vapor deposition method. Further, the oxide film formed by laser beam irradiation may be removed before forming the barrier layer.

Next, an amorphous silicon film containing an argon element serving as a gettering site is formed with a thickness of 10 to 400 nm, here 100 nm, over the barrier layer by a sputtering method. Here, the amorphous silicon film containing an argon element is formed using a silicon target in an atmosphere containing argon. In the case where an amorphous silicon film containing an argon element is formed using a plasma CVD method, the film formation conditions are as follows: the flow ratio of monosilane to argon (SiH ₄ : Ar) is 1:99, and the film formation pressure is 6.665 Pa. The RF power density is 0.087 W / cm ² and the film formation temperature is 350 ° C.

  Thereafter, the catalyst element is removed (gettering) by performing a heat treatment for 3 minutes in a furnace heated to 650 ° C. As a result, the concentration of the catalytic element in the semiconductor film having a crystal structure is reduced. A lamp annealing apparatus may be used instead of the furnace.

  Next, the amorphous silicon film containing an argon element which is a gettering site is selectively removed using the barrier layer as an etching stopper, and then the barrier layer is selectively removed with dilute hydrofluoric acid. Note that during gettering, nickel tends to move to a region with a high oxygen concentration, and thus it is desirable to remove the barrier layer made of an oxide film after gettering.

  Note that in the case where the semiconductor film is not crystallized using a catalytic element, the above-described barrier layer formation, gettering site formation, heat treatment for gettering, gettering site removal, barrier layer removal, etc. This step is unnecessary.

  Next, after forming a thin oxide film with ozone water on the surface of the obtained semiconductor film having a crystalline structure (for example, a crystalline silicon film), a mask made of resist is formed using a first photomask, and a desired film is formed. Semiconductor films (referred to as “island semiconductor regions” in this specification) 231 and 232 separated into island shapes are formed by etching into a shape (see FIG. 17A). After the island-shaped semiconductor region is formed, the resist mask is removed.

Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped in order to control the threshold value of the TFT. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used.

  Next, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surfaces of the island-shaped semiconductor regions 231 and 232 are washed, and then an insulating film containing silicon as a main component to be the gate insulating film 213 is formed. Here, a silicon oxide film containing nitrogen (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 115 nm is formed by a plasma CVD method.

  Next, after a metal film is formed over the gate insulating film 213, gate electrodes 234 and 235, wirings 214 and 215, and a terminal electrode 250 are formed using a second photomask. In this embodiment, the same resistance as that in FIG. 6 is formed, so that the wiring 400, the wiring 410, the wiring 420, the wiring 430, the wiring 440, and the wiring 450 are formed simultaneously with the gate electrode 234 and the like (see FIG. 17B). ).

  The gate electrodes 234 and 235, the wirings 214 and 215, the terminal electrode 250, the wiring 400, the wiring 410, the wiring 420, the wiring 430, the wiring 440, and the wiring 450 are titanium (Ti), tungsten (W), and tantalum (Ta). , Molybdenum (Mo), neodymium (Nd), cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) An element selected from platinum (Pt), aluminum (Al), gold (Au), silver (Ag), copper (Cu), or a single layer film made of an alloy material or compound material containing the element as a main component, Alternatively, a single layer film made of these nitrides such as titanium nitride, tungsten nitride, tantalum nitride, and molybdenum nitride is used. Door can be.

  Further, a laminated film may be used instead of the single layer film. For example, as the gate electrodes 234 and 235, the wirings 214 and 215, the terminal electrode 250, the wiring 400, the wiring 410, the wiring 420, the wiring 430, the wiring 440, and the wiring 450, tantalum nitride (TaN) and tungsten (W) are each 30 nm, A film stacked at 370 nm may be used.

  Next, an impurity imparting one conductivity type is introduced into the island-shaped semiconductor regions 231 and 232, so that the source region or drain region 237 of the TFT 105 and the source region or drain region 238 of the TFT 104 are formed. In this embodiment, since an n-channel TFT is formed, n-type impurities such as phosphorus (P) and arsenic (As) are introduced into the island-shaped semiconductor regions 231 and 232 (see FIG. 17C).

  Next, after forming a first interlayer insulating film (not shown) including a silicon oxide film by CVD with a thickness of 50 nm, a step of activating the impurity element added to each island-like semiconductor region is performed. This activation process is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination thereof. By different methods.

  Next, a second interlayer insulating film 216 including a silicon nitride film containing hydrogen and oxygen is formed with a thickness of 10 nm, for example.

  Next, a third interlayer insulating film 217 made of an insulating material is formed over the second interlayer insulating film 216 (see FIG. 18A). As the third interlayer insulating film 217, an insulating film obtained by a CVD method can be used. In this embodiment, in order to improve adhesion, a silicon oxide film containing nitrogen formed with a thickness of 900 nm is formed as the third interlayer insulating film 217.

  Next, heat treatment (300 to 550 ° C. for 1 to 12 hours, for example, in a nitrogen atmosphere at 410 ° C. for 1 hour) is performed to hydrogenate the island-shaped semiconductor film. This step is performed in order to terminate dangling bonds of the island-shaped semiconductor film with hydrogen contained in the second interlayer insulating film 216. The island-shaped semiconductor film can be hydrogenated regardless of the presence of the gate insulating film 213.

  Further, as the third interlayer insulating film 217, an insulating film using siloxane and a stacked structure thereof can be used. Siloxane has a skeleton structure with a bond of silicon (Si) and oxygen (O). As a substituent, a compound containing at least hydrogen (eg, an alkyl group or an aryl group) is used. Fluorine may be used as a substituent. Alternatively, as a substituent, a compound containing at least hydrogen and fluorine may be used.

  In the case where an insulating film using siloxane and a stacked structure thereof are used as the third interlayer insulating film 217, a heat treatment for hydrogenating the island-shaped semiconductor film is performed after the second interlayer insulating film 216 is formed. Next, a third interlayer insulating film 217 can be formed.

  Next, a resist mask is formed using a third photomask, and the first interlayer insulating film, the second interlayer insulating film 216, the third interlayer insulating film 217, or the gate insulating film 213 is selectively etched. A contact hole is formed. Then, the resist mask is removed.

  Note that the third interlayer insulating film 217 may be formed as necessary. When the third interlayer insulating film 217 is not formed, the first interlayer insulating film and the second interlayer insulating film 216 are formed after the second interlayer insulating film 216 is formed. The second interlayer insulating film 216 and the gate insulating film 213 are selectively etched to form contact holes.

  Next, after a metal laminated film is formed by a sputtering method, a mask made of a resist is formed using a fourth photomask, and the metal film is selectively etched to form a wiring 284, a connection electrode 285, and a terminal electrode 281. The source electrode or drain electrode 282 of the TFT 104 and the source electrode or drain electrode 283 of the TFT 105 are formed. In this embodiment, the same resistance as that in FIG. 6 is formed, so that the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451 are formed simultaneously with the source or drain electrode 282 and the like. Then, the resist mask is removed (see FIG. 18B).

  18B, the wiring 284, the connection electrode 285, the terminal electrode 281, the source or drain electrode 282 of the TFT 104, and the source or drain electrode 283 of the TFT 105, the wiring 401, the wiring 411, the wiring 421, the wiring 431, and the wiring 441 and the wiring 451 are formed from a single-layer conductive film.

  As such a single layer, a titanium film (Ti film) is preferable from the viewpoints of heat resistance and electrical conductivity. Further, in place of the titanium film, tungsten (W), tantalum (Ta), molybdenum (Mo), neodymium (Nd), cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh) ), Palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), or a single layer film made of an alloy material or a compound material containing the element as a main component, or these A single layer film made of a nitride such as titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride can be used. The wiring 284, the connection electrode 285, the terminal electrode 281, the source or drain electrode 282 of the TFT 104, and the source or drain electrode 283 of the TFT 105, the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451 By using a layer film, the number of film formation can be reduced in the manufacturing process.

  FIG. 18C illustrates the case where a protective electrode is provided for the wiring 219, the connection electrode 220, the terminal electrode 251, the source or drain electrode 241 of the TFT 104, and the source or drain electrode 242 of the TFT 105. In FIG. 18C, the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451 are formed using a material formed at the same time as the source or drain electrode 241 and a material formed at the same time as the protective electrode. It is comprised by the laminated film of.

  First, the wiring 219, the connection electrode 220, the terminal electrode 251, the source or drain electrode 241 of the TFT 104, and the source or drain electrode 242 of the TFT 105, the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451 Each of the lower conductive films has a laminated structure of a refractory metal film and a low resistance metal film (such as an aluminum alloy or pure aluminum). Here, the lower layer conductive film of the wiring 219, the source or drain electrodes 241 and 242, and the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451 includes a titanium film (Ti film) and an aluminum film (Al A three-layer structure in which a film) and a Ti film are sequentially stacked.

  Further, a protective electrode 218, a protective electrode 245, a protective electrode 248, and a protective electrode are provided so as to cover the wiring 219, the connection electrode 220, the terminal electrode 251, the source or drain electrode 241 of the TFT 104, and the source or drain electrode 242 of the TFT 105, respectively. 246 and a protective electrode 247 are formed. Further, the upper conductive film of the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451 is formed at the same time as the protective electrode 218 and the like.

  When the photoelectric conversion layer 100 is etched, the wiring 219 is protected by the covering protective electrode 218. The material of the protective electrode 218 is preferably a conductive material whose etching rate is lower than that of the photoelectric conversion layer 100 with respect to a gas (or etchant) for etching the photoelectric conversion layer 100. In addition, the material of the protective electrode 218 is preferably a conductive material that does not react with the photoelectric conversion layer 100 to form an alloy. The other protective electrode 245, the protective electrode 248, the protective electrode 246, the protective electrode 247, and the upper conductive film of each of the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451 are the same as the protective electrode 218. It is formed by material and manufacturing process.

  For example, after forming a conductive metal film (such as titanium (Ti) or molybdenum (Mo)) that hardly reacts with a photoelectric conversion layer (typically amorphous silicon) to be formed later, A mask made of resist is formed using this photomask, and a conductive metal film is selectively etched to form a protective electrode 218 covering the wiring 284. Here, a 200-nm-thick Ti film obtained by sputtering is used. Similarly, the connection electrode 285, the terminal electrode 281, the source or drain electrode 282 of the TFT 104, the source or drain electrode 283 of the TFT 105, and the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451, respectively. The lower conductive film is also covered with a conductive metal film, and the upper conductive films of the protective electrodes 245, 248, 246, 247 and the wiring 401, the wiring 411, the wiring 421, the wiring 431, the wiring 441, and the wiring 451, respectively. It is formed. Accordingly, the conductive metal film also covers the side surface of the electrode where the second Al film is exposed, and the conductive metal film can prevent diffusion of aluminum atoms into the photoelectric conversion layer.

  Next, the photoelectric conversion layer 100 including the p-type semiconductor layer 100p, the i-type semiconductor layer 100i, and the n-type semiconductor layer 100n is formed over the third interlayer insulating film 217.

  The p-type semiconductor layer 100p may be formed by forming an amorphous silicon film containing a Group 13 impurity element such as boron (B) by a plasma CVD method.

  In FIG. 19A, the wiring 284 is electrically connected to the lowermost layer of the photoelectric conversion layer 100, in this embodiment, the p-type semiconductor layer 100p.

  In the case of forming a protective electrode, the wiring 284 and the protective electrode 218 are electrically connected to the lowermost layer of the photoelectric conversion layer 100, in this embodiment, the p-type semiconductor layer 100p.

  After the p-type semiconductor layer 100p is formed, an i-type semiconductor layer 100i and an n-type semiconductor layer 100n are further formed in order. Thus, the photoelectric conversion layer 100 including the p-type semiconductor layer 100p, the i-type semiconductor layer 100i, and the n-type semiconductor layer 100n is formed.

  As the i-type semiconductor layer 100i, for example, an amorphous silicon film may be formed by a plasma CVD method. As the n-type semiconductor layer 100n, an amorphous silicon film containing a Group 15 impurity element such as phosphorus (P) may be formed, or a Group 15 impurity element may be introduced after the amorphous silicon film is formed. Good.

  Further, as the p-type semiconductor layer 100p, the i-type semiconductor layer 100i, and the n-type semiconductor layer 100n, not only an amorphous semiconductor film but also a semi-amorphous semiconductor film may be used.

  Next, a sealing layer 224 made of an insulating material (for example, an inorganic insulating film containing silicon) is formed over the entire surface with a thickness (1 μm to 30 μm) to obtain the state shown in FIG. Here, a silicon oxide film containing nitrogen having a thickness of 1 μm is formed as the insulating material film by a CVD method. Adhesion is improved by using an insulating film formed by CVD.

  Next, after the sealing layer 224 is etched to provide openings, terminal electrodes 221 and 222 are formed by sputtering. The terminal electrodes 221 and 222 are laminated films of a titanium film (Ti film) (100 nm), a nickel film (Ni) film (300 nm), and a gold film (Au film) (50 nm). The fixing strength of the terminal electrode 221 and the terminal electrode 222 thus obtained exceeds 5N, and has a sufficient fixing strength as a terminal electrode.

  Through the above steps, the terminal electrode 221 and the terminal electrode 222 that can be connected by soldering are formed, and the structure shown in FIG. 19B is obtained.

  Next, a plurality of optical sensor chips are cut out individually. A large amount of optical sensor chips (2 mm × 1.5 mm) can be manufactured from one large-area substrate (for example, 600 cm × 720 cm).

  A cross-sectional view of one cut out optical sensor chip (2 mm × 1.5 mm) is shown in FIG. 20A, a bottom view thereof is shown in FIG. 20B, and a top view thereof is shown in FIG. 20A to 20C, FIG. 15, FIG. 16, FIG. 17A to FIG. 17C, FIG. 18A to FIG. 18C, and FIG. The same code | symbol is used for the location which is the same as 19 (B). In FIG. 20A, the total film thickness including the substrate 210, the element formation region 291 and the terminal electrode 221 and the terminal electrode 222 is 0.8 ± 0.05 mm.

  In order to reduce the total film thickness of the optical sensor chip, the substrate 210 may be thinned by CMP processing or the like, and then individually cut with a dicer to cut out a plurality of optical sensor chips.

In FIG. 20B, one electrode size of the terminal electrodes 221 and 222 is 0.6 mm × 1.1 mm, and the electrode interval is 0.4 mm. In FIG. 20C, the area of the light receiving portion 292 is 1.57 mm ² . In addition, the amplifier circuit portion 293 is provided with about 100 TFTs.

  Finally, the obtained optical sensor chip is mounted on the mounting surface of the substrate 260. Note that solder 264 and 263 are used to connect the terminal electrode 221 and the electrode 261 and the terminal electrode 222 and the electrode 262, respectively, and are previously formed on the electrodes 261 and 262 of the substrate 260 by a screen printing method or the like. After the solder and the terminal electrode are in contact with each other, the solder reflow process is performed for mounting. The solder reflow process is performed, for example, in an inert gas atmosphere at a temperature of about 255 ° C. to 265 ° C. for about 10 seconds. In addition to solder, bumps formed of metal (gold, silver, etc.) or bumps formed of conductive resin can be used. Moreover, you may mount using lead-free solder in consideration of an environmental problem.

  As described above, a semiconductor device including a photoelectric conversion device including the photoelectric conversion layer 100, a current mirror circuit 122, and a resistor that corrects parasitic resistance of the current mirror circuit 122 can be obtained.

  FIG. 32 shows a circuit diagram of this embodiment. 1 and 15 are denoted by the same reference numerals.

  The photoelectric conversion device 130 includes the photoelectric conversion layer 100. The correction resistors 112 to 117 for correcting the parasitic resistance of the current mirror circuit 122 are the wiring 400 and the wiring 401, the wiring 410 and the wiring 411, the wiring 420 and the wiring 421, the wiring 430 and the wiring 431, and the wiring 440 and the wiring, respectively. 441, which corresponds to any one of the combination of the wiring 450 and the wiring 451.

  In the semiconductor device of this embodiment, the same resistance as that shown in FIG. 6 is used, but the resistance shown in FIGS. 7 to 11 may be used. An example in which the resistor shown in FIGS. 7 to 11 is used in this embodiment is shown in FIGS. 21 to 25, the same components as those in FIGS. 6 to 11 are denoted by the same reference numerals.

  For example, as shown in FIG. 24, the resistors (wiring 405 and wiring 406, wiring 415 and wiring 416, wiring 425 and wiring 426, wiring 435 and wiring 436, wiring 445 and wiring 446, wiring 455 and wiring 456 shown in FIG. ) Is used in this embodiment, the wiring 405, the wiring 415, the wiring 425, the wiring 435, the wiring 445, and the wiring 455 are the same when the island-shaped semiconductor region 231 shown in FIG. Then, an island-shaped semiconductor region is formed, and an impurity imparting one conductivity type shown in FIG. 17C is introduced. Further, the wiring 406, the wiring 416, the wiring 426, the wiring 436, the wiring 446, and the wiring 456 may be formed at the same time as the gate electrode 234 and the like illustrated in FIG.

  Moreover, you may form the resistance of a present Example combining the resistance of a different structure shown in FIGS. 6-11 as needed. In that case, a material and a manufacturing process necessary for forming the resistor may be based on the above description.

  Note that this embodiment can be combined with any description in Embodiment Mode and other embodiments.

  In this embodiment, an example in which an amplifier circuit is formed using a p-channel TFT will be described with reference to FIGS. Note that the same portions as those in the embodiment mode and the first embodiment are denoted by the same reference numerals, and may be formed based on the manufacturing steps described in the embodiment mode and the first embodiment, respectively.

  In this embodiment, an example in which the resistance shown in FIG. 11 is applied as a resistance for correcting the parasitic resistance is shown. However, the present embodiment is not limited to this, and the resistors shown in FIGS. 6 to 10 may be used.

  In the case where the amplifier circuit, for example, the current mirror circuit 203 is formed using the p-channel TFTs 201 and 202, an impurity imparting one conductivity type to the island-shaped semiconductor regions of the embodiment mode and the first embodiment is changed to a p-type impurity, For example, it may be replaced with boron (B).

  FIG. 5 shows an equivalent circuit diagram of the photosensor of this embodiment in which the current mirror circuit 203 is made of p-channel TFTs 201 and 202, and FIG.

  5 and 26, the terminal electrodes 221 and 222 are connected to the photoelectric conversion layer 208 and the p-channel TFTs 201 and 202, respectively. The p-channel TFT 201 is electrically connected to the anode side electrode of the photoelectric conversion layer 208. The photoelectric conversion layer 208 is formed by sequentially stacking an n-type semiconductor layer 208n, an i-type semiconductor layer 208i, and a p-type semiconductor layer 208p on a second electrode (anode side electrode) connected to the p-channel TFT 201, The electrode (cathode side electrode) may be formed.

  Alternatively, a photoelectric conversion layer in which the stacking order is reversed may be used. After sequentially stacking a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer on the first electrode (cathode side electrode), a p-channel type is formed. A second electrode (anode side electrode) connected to the TFT 201 may be formed, and a cathode side terminal electrode connected to the first electrode may be formed.

  As shown in FIG. 26, p-type impurities such as boron (B) are introduced into the island-shaped semiconductor regions of the p-channel TFTs 201 and 202, and the p-channel TFT 201 has a source region or a drain region 271, A source region or drain region 272 is formed in the p-channel TFT 202.

  The wiring 284, the connection electrode 285, the terminal electrode 281, the source or drain electrode 283 of the TFT 201, and the source or drain electrode 282 of the TFT 202 are formed using a single-layer conductive film as described in Embodiment 1. .

  Similarly to FIG. 16, instead of the wiring 284, the connection electrode 285, the terminal electrode 281, the source or drain electrode 283 of the TFT 201, and the source or drain electrode 282 of the TFT 202, the wiring 284 and its protective electrode 218, connection Even if the electrode 285 and its protective electrode 245, the terminal electrode 281 and its protective electrode 248, the source or drain electrode 283 and its protective electrode 247 of the TFT 201, and the source or drain electrode 282 and its protective electrode 246 of the TFT 202 are formed. Good. Each manufacturing method is based on the embodiment mode or Example 1.

  In this embodiment, the wiring 407, the wiring 417, the wiring 427, the wiring 437, the wiring 447, and the wiring 457 are each formed using the same material and the same process as the source or drain electrode 282 and the like.

  Note that this embodiment can be combined with any description in Embodiment Mode and other embodiments.

  In this embodiment, an example of an optical sensor in which an amplifier circuit is formed using a bottom-gate TFT and a manufacturing method thereof are illustrated in FIGS. 27A to 27D and FIGS. 28A to 28C. This will be described with reference to FIGS. 29A to 29B, FIGS. 30, 31, 38, 39, 40, 41, and 42. FIG. In addition, the same thing as embodiment and Example 1-2 is shown with the same code | symbol.

  First, the base insulating film 212 and the metal film 311 are formed over the substrate 210 (see FIG. 27A). In this embodiment, for example, a film in which tantalum nitride (TaN) and tungsten (W) are stacked by 30 nm and 370 nm is used as the metal film 311.

  In addition to the above, as the metal film 311, titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), neodymium (Nd), cobalt (Co), zirconium (Zr), zinc (Zn) , Ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), aluminum (Al), gold (Au), silver (Ag), copper (Cu) Or a single layer film made of an alloy material or a compound material containing the element as a main component, or a single layer film made of these nitrides, for example, titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride Can be used.

  Note that the metal film 311 may be formed directly on the substrate 210 without forming the base insulating film 212 on the substrate 210.

  Next, gate electrodes 312 and 313, wirings 214 and 215, and a terminal electrode 250 are formed using the metal film 311.

  Through the same process as the gate electrode 312 and the like, the wiring 500, the wiring 510, the wiring 520, the wiring 530, the wiring 540, and the wiring 550 are formed using the metal film 311 (see FIG. 27B).

  Next, a gate insulating film 314 is formed to cover the gate electrodes 312 and 313, the wirings 214 and 215, the terminal electrode 250, the wiring 500, the wiring 510, the wiring 520, the wiring 530, the wiring 540, and the wiring 550. In this embodiment, an insulating film containing silicon as a main component, for example, a silicon oxide film containing nitrogen with a thickness of 115 nm by a plasma CVD method (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) is used to form the gate insulating film 314.

  Next, island-shaped semiconductor regions 315 and 316 are formed over the gate insulating film 314. The island-shaped semiconductor regions 315 and 316 may be formed using a material and a manufacturing process similar to those of the island-shaped semiconductor regions 231 and 232 described in Embodiment 1 (see FIG. 27C).

  After the island-shaped semiconductor regions 315 and 316 are formed, a mask 318 is formed so as to cover regions other than the source region or drain region 321 of the TFT 301 and the source region or drain region 322 of the TFT 302, and an impurity imparting one conductivity type Is introduced (see FIG. 27D). As an impurity of one conductivity type, phosphorus (P) or arsenic (As) is used as an n-type impurity when forming an n-channel TFT, and as a p-type impurity when forming a p-channel TFT. Boron (B) may be used. In this embodiment, phosphorus (P) which is an n-type impurity is introduced into the island-shaped semiconductor regions 315 and 316, the channel region between the source region or the drain region 321 of the TFT 301 and the source region and the drain region, and the source of the TFT 302. A channel formation region is formed between the region or the drain region 322 and the source region and the drain region.

  Next, the mask 318 is removed, and a first interlayer insulating film, a second interlayer insulating film 216, and a third interlayer insulating film 217 (not shown) are formed (see FIG. 28A). The materials and manufacturing steps of the first interlayer insulating film, the second interlayer insulating film 216, and the third interlayer insulating film 217 may be based on the description in Embodiment 1.

  Next, contact holes are formed in the first interlayer insulating film, the second interlayer insulating film 216, and the third interlayer insulating film 217, a single-layer metal film is formed, and the metal film is selectively etched. The wiring 284, the connection electrode 285, the terminal electrode 281, the source or drain electrode 341 of the TFT 301, and the source or drain electrode 342 of the TFT 302, the wiring 501, the wiring 511, the wiring 521, the wiring 531, the wiring 541, and the wiring 551 Is formed.

  In addition, a wiring 284, a connection electrode 285, a terminal electrode 281, a source or drain electrode 341 of the TFT 301, and a source or drain electrode 342 of the TFT 302, a wiring 501, a wiring 511, a wiring 521, a wiring 531, a wiring 541, and a wiring 551 are provided. Instead of a single-layer conductive film, a laminated film may be used. An example in which these are formed using a stacked film is shown in FIG.

  In FIG. 28C, instead of the wiring 284, the connection electrode 285, the terminal electrode 281 and the source or drain electrode 341 of the TFT 301 and the source or drain electrode 342 of the TFT 302, the wiring 219 and its protective electrode 218 are connected. An electrode 220 and its protective electrode 245, a terminal electrode 251 and its protective electrode 248, a TFT 301 source or drain electrode 331 and its protective electrode 336, and a TFT 302 source or drain electrode 332 and its protective electrode 337 are formed.

  In FIG. 28C, the wiring 501, the wiring 511, the wiring 521, the wiring 531, the wiring 541, and the wiring 551 are formed by stacking different conductive films.

  Through the above steps, bottom-gate TFTs 301 and 302 can be manufactured. A current mirror circuit 303 can be formed by the bottom gate TFTs 301 and 302.

  Resistances for correcting the parasitic resistance of the current mirror circuit are formed by the wiring 500 and the wiring 501, the wiring 510 and the wiring 511, the wiring 520 and the wiring 521, the wiring 530 and the wiring 531, the wiring 540 and the wiring 541, the wiring 550 and the wiring 551. Has been. 27C and 27D is a combination of a wiring formed in the same process as the gate electrode and a wiring formed in the same process as the source or drain electrode. ing. However, the resistance for correcting the parasitic resistance of the current mirror circuit is not limited to the structure shown in FIGS. 27C and 27D, and the structure formed only by the wiring formed in the same process as the gate electrode, TFT A structure in which a wiring formed in the same process as the source region or drain region of the TFT and a wiring formed in the same process as the source electrode or drain electrode are combined, and a wiring formed in the same process as the source region or drain region of the TFT A structure formed by only the same process as the gate electrode and a wiring formed in the same process as the source or drain region of the TFT, and formed in the same process as the source or drain electrode It may be configured to be formed only by the formed wiring.

  Next, the photoelectric conversion layer 100 including the p-type semiconductor layer 100p, the i-type semiconductor layer 100i, and the n-type semiconductor layer 100n is formed over the third interlayer insulating film 217 (see FIG. 29A). Embodiments and other examples may be referred to for the material, manufacturing process, and the like of the photoelectric conversion layer 100.

  Next, a sealing layer 224 and terminal electrodes 221 and 222 are formed (see FIG. 29B). The terminal electrode 221 is connected to the n-type semiconductor layer 100n, and the terminal electrode 222 is formed in the same process as the terminal electrode 221.

  Further, a substrate 260 having electrodes 261 and 262 is mounted with solder 263 and 264. Note that the electrode 261 on the substrate 260 is mounted on the terminal electrode 221 with solder 264. Further, the electrode 262 of the substrate 260 is mounted on the terminal electrode 222 with solder 263 (see FIG. 30).

  FIG. 31 shows an example in which the substrate 260 having the electrodes 261 and 262 is mounted in FIG.

  FIG. 38 shows a case where the resistor for correcting the parasitic resistance of the current mirror circuit is formed by only the wiring formed in the same process as the gate electrode 312 and the like. Each of the wiring 500, the wiring 510, the wiring 520, the wiring 530, the wiring 540, and the wiring 550 functions as one resistor.

  Further, the resistance for correcting the parasitic resistance of the current mirror circuit is a combination of a wiring formed in the same process as the source region or the drain region 321 and a wiring formed in the same process as the source or drain electrode 341 or the like. Is shown in FIG. The wiring 503, the wiring 513, the wiring 523, the wiring 533, the wiring 543, and the wiring 553 are formed in the same process as the source region or the drain region 321 and the like. The wiring 504, the wiring 514, the wiring 524, the wiring 534, the wiring 544, and the wiring 554 are formed in the same process as the source or drain electrode 341 and the like. A combination of the wiring 503 and the wiring 504, the wiring 513 and the wiring 514, the wiring 523 and the wiring 524, the wiring 533 and the wiring 534, the wiring 543 and the wiring 544, the wiring 553 and the wiring 554 each functions as one resistor.

  Further, FIG. 40 shows a structure in which a resistor for correcting the parasitic resistance of the current mirror circuit is formed only by wiring formed in the same process as the source region or the drain region 321 or the like. The wiring 503, the wiring 513, the wiring 523, the wiring 533, the wiring 543, and the wiring 553 are formed in the same process as the source region or the drain region 321 and each function as one resistor.

  In addition, a configuration in which a resistor for correcting the parasitic resistance of the current mirror circuit is combined with a wiring formed in the same process as the gate electrode 312 and the wiring formed in the same process as the source region or the drain region 321 is illustrated in FIG. 41. The wiring 505, the wiring 515, the wiring 525, the wiring 535, the wiring 545, and the wiring 555 are formed in the same process as the gate electrode 312 and the like. The wiring 506, the wiring 516, the wiring 526, the wiring 536, the wiring 546, and the wiring 556 are formed in the same process as the source region or the drain region 321 and the like. A combination of the wiring 505 and the wiring 506, the wiring 515 and the wiring 516, the wiring 525 and the wiring 526, the wiring 535 and the wiring 536, the wiring 545 and the wiring 546, and the wiring 555 and the wiring 556 each function as one resistor.

  Further, FIG. 42 shows a configuration in which the resistance for correcting the parasitic resistance of the current mirror circuit is formed only by the wiring formed in the same process as the source electrode or the drain electrode 341 or the like. The wiring 507, the wiring 517, the wiring 527, the wiring 537, the wiring 547, and the wiring 557 are formed in the same process as the source or drain electrode 341 and the like, and each function as one resistor.

  Note that this embodiment can be combined with any description in Embodiment Mode and other embodiments.

  In this embodiment, examples in which the photoelectric conversion device obtained by the present invention is incorporated into various electronic devices will be described. Examples of electronic devices to which the present invention is applied include computers, displays, mobile phones, and televisions. Specific examples of these electronic devices are shown in FIGS. 33, 34 (A) to 34 (B), 35 (A) to 35 (B), 36 and 37.

  FIG. 33 shows a cellular phone, which includes a main body (A) 701, a main body (B) 702, a housing 703, operation keys 704, an audio input unit 705, an audio output unit 706, a circuit board 707, a display panel (A) 708, and a display. A panel (B) 709, a hinge 710, a light-transmitting material portion 711, and a photoelectric conversion element 712 are included. The present invention can be applied to the photoelectric conversion element 712.

  The photoelectric conversion element 712 detects light transmitted through the light-transmitting material portion 711, performs brightness control of the display panel (A) 708 and the display panel (B) 709 in accordance with the detected illuminance of external light, or performs photoelectric conversion. The illumination of the operation key 704 is controlled in accordance with the illuminance obtained by the element 712. Thereby, current consumption of the mobile phone can be suppressed.

  34A and 34B show another example of a mobile phone. 34A and 34B, 721 is a main body, 722 is a housing, 723 is a display panel, 724 is an operation key, 725 is an audio output unit, 726 is an audio input unit, and 727 and 728 are photoelectric conversions. It is an element.

  In the mobile phone shown in FIG. 34A, the luminance of the display panel 723 and the operation key 724 can be controlled by detecting external light with the photoelectric conversion element 727 provided in the main body 721.

  34B, a photoelectric conversion element 728 is provided inside the main body 721 in addition to the structure in FIG. The luminance of the backlight provided in the display panel 723 can also be detected by the photoelectric conversion element 728.

  FIG. 35A illustrates a computer, which includes a main body 731, a housing 732, a display portion 733, a keyboard 734, an external connection port 735, a pointing mouse 736, and the like.

  FIG. 35B shows a display device such as a television receiver. This display device includes a housing 741, a support base 742, a display portion 743, and the like.

  FIG. 36 shows a detailed structure in the case where a liquid crystal panel is used as the display portion 733 provided in the computer of FIG. 35A and the display portion 743 of the display device shown in FIG.

  A liquid crystal panel 762 illustrated in FIG. 36 is incorporated in a housing 761, and includes substrates 751a and 751b, a liquid crystal layer 752 sandwiched between the substrates 751a and 751b, polarization filters 755a and 755b, a backlight 753, and the like. Yes. In the housing 761, a photoelectric conversion element formation region 754 including a photoelectric conversion element is formed.

  The photoelectric conversion element formation region 754 manufactured using the present invention senses the amount of light from the backlight 753, and the information is fed back to adjust the luminance of the liquid crystal panel 762.

  FIGS. 37A and 37B are diagrams showing an example in which the optical sensor of the present invention is incorporated in a camera, for example, a digital camera. FIG. 37A is a perspective view seen from the front side of the digital camera, and FIG. 37B is a perspective view seen from the rear side. In FIG. 37A, the digital camera includes a release button 801, a main switch 802, a finder window 803, a flash 804, a lens 805, a lens barrel 806, and a housing 807.

  In FIG. 37B, a viewfinder eyepiece window 811, a monitor 812, and operation buttons 813 are provided.

  When the release button 801 is pressed down to a half position, the focus adjustment mechanism and the exposure adjustment mechanism are operated, and when the release button 801 is pressed down to the lowest position, the shutter is opened.

  A main switch 802 switches on / off the power of the digital camera when pressed or rotated.

  The viewfinder window 803 is an apparatus for confirming a shooting range and a focus position from the viewfinder eyepiece window 811 shown in FIG.

  The flash 804 is arranged at the upper front of the digital camera. When the subject brightness is low, the release button is pressed to open the shutter and simultaneously emit auxiliary light.

  The lens 805 is disposed in front of the digital camera. The lens includes a focusing lens, a zoom lens, and the like, and constitutes a photographing optical system together with a shutter and a diaphragm (not shown). In addition, an imaging element such as a CCD (Charge Coupled Device) is provided behind the lens.

  The lens barrel 806 moves the lens position in order to focus the focusing lens, the zoom lens, and the like. During photographing, the lens barrel 805 is extended to move the lens 805 forward. Further, when carrying the camera, the lens 805 is moved down to be compact. In this embodiment, the structure is such that the subject can be zoomed by extending the lens barrel. However, the present invention is not limited to this structure, and the lens barrel is configured by the configuration of the imaging optical system in the housing 807. It is also possible to use a digital camera that can perform zoom shooting without extending the camera.

  The viewfinder eyepiece window 811 is provided on the upper rear surface of the digital camera, and is a window provided for eye contact when confirming the photographing range and the focus position.

  The operation buttons 813 are various function buttons provided on the rear surface of the digital camera, and include a setup button, a menu button, a display button, a function button, a selection button, and the like.

  When the optical sensor of the present invention is incorporated in the camera shown in FIGS. 37A and 37B, the optical sensor can detect the presence and intensity of light, thereby adjusting the exposure of the camera. Can do.

  The optical sensor of the present invention can be applied to other electronic devices such as a projection television and a navigation system. In other words, it can be used for any object that needs to detect light.

  Note that this embodiment can be combined with any description in Embodiment Mode and other embodiments.

According to the present invention, it is possible to manufacture a semiconductor device or a photoelectric conversion device that can suppress product variation while improving the stability of circuit operation. In addition, by incorporating the semiconductor device or the photoelectric conversion device of the present invention, it is possible to obtain an electric device with high stability and reliability of circuit operation.

1 is a circuit diagram of a semiconductor device of the present invention. 1 is a circuit diagram of a semiconductor device of the present invention. 1 is a circuit diagram of a semiconductor device of the present invention. 1 is a circuit diagram of a semiconductor device of the present invention. 1 is a circuit diagram of a semiconductor device of the present invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. 4 is a top view of an element functioning as a resistance of a circuit of a semiconductor device of the present invention. FIG. 4 is a top view of an element functioning as a resistance of a circuit of a semiconductor device of the present invention. FIG. 4 is a top view of an element functioning as a resistance of a circuit of a semiconductor device of the present invention. FIG. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. 1 is a circuit diagram of a semiconductor device of the present invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. 1 is a top view of a semiconductor device of the present invention. 1 is a circuit diagram of a semiconductor device of the present invention.

Explanation of symbols

100 photoelectric conversion layer 100p p-type semiconductor layer 100i i-type semiconductor layer 100n n-type semiconductor layer 101 power supply 102 terminal 103 terminal 104 TFT
105 TFT
105a TFT
105b TFT
105i TFT
106 parasitic resistor 107 parasitic resistor 108 parasitic resistor 109 parasitic resistor 109i parasitic resistor 110 parasitic resistor 110i parasitic resistor 111 parasitic resistor 111i parasitic resistor 112 resistor 113 resistor 114 resistor 115 resistor 115i resistor 116 resistor 116i resistor 117 resistor 117i resistor 118a circuit 118b circuit 118i Circuit 119a Terminal 119b Terminal 119i Terminal 120a Terminal 120b Terminal 120i Terminal 121a Terminal 121b Terminal 121i Terminal 122 Current mirror circuit 123 Circuit 124 Output terminal 125 Power supply 130 Photoelectric conversion device 141 Wiring 142 Wiring 143 Wiring 151 Wiring 152 Wiring 153 Wiring 153 Wiring 154 Wiring 155 Wiring 156 Wiring 161 Wiring 201 TFT
202 TFT
203 current mirror circuit 204 circuit 208 photoelectric conversion layer 208p p-type semiconductor layer 208i i-type semiconductor layer 208n n-type semiconductor layer 210 substrate 212 base insulating film 213 gate insulating film 214 wiring 215 wiring 216 insulating film 217 insulating film 218 protective electrode 219 wiring 220 connecting electrode 221 terminal electrode 222 terminal electrode 224 sealing layer 231 island-like semiconductor region 232 island-like semiconductor region 234 gate electrode 235 gate electrode 237 source region or drain region 238 source region or drain region 241 source electrode or drain electrode 242 source electrode Or drain electrode 245 protective electrode 246 protective electrode 247 protective electrode 248 protective electrode 250 terminal electrode 251 terminal electrode 260 substrate 261 electrode 262 electrode 263 solder 264 solder 271 source region or Rain region 272 source region or drain region 281 terminal electrode 282 the source or drain electrode 283 the source or drain electrode 284 interconnect 285 connecting electrode 291 element forming region 292 light receiving section 293 amplifying circuit unit 301 TFT
302 TFT
303 current mirror circuit 311 metal film 312 gate electrode 313 gate electrode 314 gate insulating film 315 island semiconductor region 316 island semiconductor region 318 mask 321 source region or drain region 322 source region or drain region 331 source electrode or drain electrode 332 source electrode Or drain electrode 336 protective electrode 337 protective electrode 341 source electrode or drain electrode 342 source electrode or drain electrode 400 wiring 401 wiring 403 wiring 404 wiring 405 wiring 406 wiring 407 wiring 410 wiring 411 wiring 413 wiring 414 wiring 415 wiring 416 wiring 417 wiring 420 Wiring 421 Wiring 423 Wiring 424 Wiring 425 Wiring 426 Wiring 427 Wiring 430 Wiring 431 Wiring 433 Wiring 434 Wiring 435 Wiring 436 Wiring Wiring 437 wiring 440 wiring 441 wiring 443 wiring 444 wiring 445 wiring 446 wiring 447 wiring 450 wiring 451 wiring 453 wiring 454 wiring 455 wiring 456 wiring 457 wiring 470 wiring 471 wiring 472 wiring 473 wiring 474 wiring 475 wiring 476 wiring 477 wiring 478 wiring Wiring 501 wiring 503 wiring 504 wiring 505 wiring 506 wiring 507 wiring 510 wiring 511 wiring 513 wiring 514 wiring 515 wiring 516 wiring 517 wiring 520 wiring 521 wiring 523 wiring 524 wiring 525 wiring 526 wiring 527 wiring 530 wiring 531 wiring 535 wiring 534 wiring 535 wiring 534 Wiring 536 Wiring 537 Wiring 540 Wiring 541 Wiring 543 Wiring 544 Wiring 545 Wiring 546 Wiring 550 Wiring 551 Wiring 553 Wiring 5 4 wire 555 wire 556 wire 557 wire 701 body (A)
702 Body (B)
703 Housing 704 Operation key 705 Audio output unit 706 Audio input unit 707 Circuit board 708 Display panel (A)
709 Display panel (B)
710 Hinge 711 Translucent material portion 712 Photoelectric conversion element 721 Main body 722 Case 723 Display panel 724 Operation key 725 Audio output portion 726 Audio input portion 727 Photoelectric conversion element 728 Photoelectric conversion element 731 Main body 732 Case 733 Display portion 734 Keyboard 735 External connection port 736 Pointing mouse 741 Case 742 Support base 743 Display unit 751a Substrate 751b Substrate 752 Liquid crystal layer 753 Backlight 754 Photoelectric conversion element formation region 755a Polarization filter 755b Polarization filter 761 Case 762 Liquid crystal panel 801 Release button 802 Main switch 803 Viewfinder window 804 Flash 805 Lens 806 Lens barrel 807 Housing 811 Viewfinder eyepiece window 812 Monitor 813 Operation button R _L Load resistance

Claims (5)

A current mirror circuit having at least two thin film transistors;
The thin film transistor has a channel formation region, an island-shaped semiconductor film having a source region or a drain region, a gate insulating film, a gate electrode, a source electrode or a drain electrode,
The current mirror circuit has a parasitic resistance;
A correction resistor for correcting the parasitic resistance is installed, or
The semiconductor device according to claim 1, wherein the correction resistor corrects a parasitic resistance of the gate electrode, a parasitic resistance of the source electrode, and a parasitic resistance of the drain electrode. A first transistor including a gate electrode, a source electrode, and a drain electrode;
A second transistor including a gate electrode, a source electrode, and a drain electrode;
A first terminal electrically connected to a drain electrode of the first transistor and a drain electrode of the second transistor;
A source electrode of the first transistor, a second terminal electrically connected to the source electrode of the second transistor,
Have
The gate electrode of the first transistor is connected to the gate electrode of the second transistor through a contact, and the gate electrode of the first transistor is electrically connected to the drain electrode of the first transistor. Connected,
A resistance value of a first path which is a path from the first terminal to the second terminal through the drain electrode of the first transistor and the source electrode of the first transistor; The resistance of the second path, which is the path from the terminal to the second terminal through the drain electrode of the second transistor and the source electrode of the second transistor, is the same. Forming a correction resistor in one or both of the path and the second path;
The resistance value of the third path, which is the path from the gate electrode of the first transistor to the contact point, and the resistance value of the fourth path, which is the path from the gate electrode of the second transistor to the contact point, are the same. The semiconductor device is characterized in that a correction resistor is formed in one or both of the third path and the fourth path. In claim 1 or claim 2,
The semiconductor device according to claim 1, wherein the correction resistor has a wiring containing the same material as the gate electrode. In claim 1 or claim 2,
The semiconductor device according to claim 1, wherein the correction resistor includes a wiring including the same material as the source electrode or the drain electrode. In claim 1 or claim 2,
The semiconductor device according to claim 1, wherein the correction resistor includes a wiring containing the same material as the source region or the drain region.

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