JP2005123512A - 半導体装置 - Google Patents
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- 230000015556 catabolic process Effects 0.000 claims abstract description 159
- 238000002955 isolation Methods 0.000 claims abstract description 67
- 239000012212 insulator Substances 0.000 claims abstract description 17
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- 230000008054 signal transmission Effects 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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Abstract
【解決手段】 半導体装置100は,低電位基準回路領域1と高電位基準回路領域2とを備え,高電位基準回路領域2が高耐圧分離領域3に取り囲まれる構造を構成している。高耐圧分離領域3の外縁に形成されたトレンチ4にて低電位基準回路領域1と高電位基準回路領域2とが分離されている。トレンチ4は,その内部が絶縁物にて充填されており,低電位基準回路領域1と高電位基準回路領域2とを絶縁している。また,高耐圧分離領域3は,トレンチ4にて区画されており,区画された部位に高耐圧NMOS5や高耐圧PMOS6が設けられている。
【選択図】 図1
Description
第1の形態に係る半導体装置100は,図1の平面図に示す構造を有している。なお,図16で示した従来の半導体装置と同一記号の構成要素は,その構成要素と同一機能を有するものである。半導体装置100は,低電位基準回路領域1と高電位基準回路領域2とを備え,高電位基準回路領域2が高耐圧分離領域3に取り囲まれる構造(リサーフ構造)を構成している。この高耐圧分離領域3により,低電位基準回路領域1と高電位基準回路領域2とが分離されている。さらに,高耐圧分離領域3の外縁にはトレンチ4が形成されている。このトレンチ4の中は,酸化シリコン等の絶縁物で充填されている。そのため,高電位基準回路領域2は低電位基準回路領域1と絶縁されている。また,高耐圧分離領域3は,その一部がトレンチ4にて区画されており,区画された部位に高耐圧NMOS5あるいは高耐圧PMOS6が設けられている。これらのMOSは,低電位基準回路領域1と高電位基準回路領域2との間の信号伝達(レベルシフト)を行うためのものである。具体的には,低電位基準回路領域1から高電位基準回路領域2へのレベルシフトには,ドレイン配線5dを高電位基準回路領域2内に配置した高耐圧NMOS5が利用される。一方,高電位基準回路領域2から低電位基準回路領域1へのレベルシフトには,ドレイン配線6dを低電位基準回路領域1内に配置した高耐圧PMOS6が利用される。
2L>√(2εVPT/qNP ) (1)
式(1)中,“ε”はシリコンの誘電率,“VPT”はパンチスルー降伏に対する耐圧,“q”は電子の電荷量,“NP ”はP型基板の濃度をそれぞれ意味している。例えば,パンチスルー耐圧VPT=50V,1000V級の高耐圧半導体装置で一般的に使用される基板濃度NP =1.0×1014cm-3をそれぞれ式(1)に適用すると,2L≒26μmとなる。一方,本形態の半導体装置100では,トレンチ4としてシリコン酸化膜を使用した場合,一般的に3MV/cm以下となる膜厚を選択すればよく,例えば耐圧50Vを得るためにはおよそ170nmあれば足りる。よって,特許文献2の半導体装置と比較して,面積ロスが小さいことがわかる。
第2の形態に係る半導体装置200は,図6の平面図に示す構造を有している。半導体装置200は,低電位基準回路領域1と高電位基準回路領域2とを備え,第1の形態の半導体装置100と同様に高電位基準回路領域2が高耐圧分離領域3に取り囲まれる構造を構成している。さらには,高耐圧分離領域3の一部にトレンチ41,42が形成されており,高耐圧分離領域3が複数の領域に区画されている。そして,区画された部位に高耐圧NMOS5あるいは高耐圧PMOS6が設けられている。第1の形態の半導体装置100との相違点は,トレンチ41,42がそれぞれ高耐圧NMOS5,高耐圧PMOS6の一部を包囲していないことである。具体的には,ソース配線側にトレンチが形成されていない。また,高耐圧分離領域3の外縁に形成されていたトレンチが存在しない。
第3の形態に係る半導体装置300は,図8の平面図に示す構造を有している。半導体装置300は,低電位基準回路領域1と高電位基準回路領域2とを備え,第1の形態の半導体装置100と同様に高電位基準回路領域2が高耐圧分離領域3に取り囲まれる構造を構成している。また,高耐圧分離領域3の一部に高耐圧NMOS5が設けられている。また,外壁トレンチ43と内壁トレンチ44とを設けている。本形態の半導体装置300には,第1の形態の半導体装置100と異なり,高耐圧分離領域3内を区画するトレンチが存在しない。そのため,トレンチの近傍に発生し易い結晶欠陥等に伴う耐圧の低下を防止することができる。
第4の形態に係る半導体装置400は,図10の平面図に示す構造を有している。半導体装置400は,低電位基準回路領域1と高電位基準回路領域2とを備え,高電位基準回路領域2が高耐圧分離領域3に取り囲まれる構造を構成している。この高耐圧分離領域3により,低電位基準回路領域1と高電位基準回路領域2とが分離されている。さらに,高耐圧分離領域3内には高耐圧分離領域3の形状に合わせたループ状のトレンチ群40が形成されている。トレンチ群40の各トレンチの中は絶縁物で充填されている。また,高耐圧分離領域3には,トレンチ4にて区画された部位が設けられており,その区画された部位にレベルシフト用の高耐圧NMOS5あるいは高耐圧PMOS6が設けられている。
第5の形態に係る半導体装置500は,図14の平面図に示す構造を有している。すなわち,半導体装置500は,低電位基準回路領域1と高電位基準回路領域2とを備えている。そして,高電位基準回路領域2が複数の高耐圧NMOS5(あるいは高耐圧PMOS6)に囲まれた構造を構成している。各高耐圧NMOS5は,トレンチ4にて囲まれている。
第6の形態に係る半導体装置600は,図15の平面図に示す構造を有している。すなわち,半導体装置600は,低電位基準回路領域1と高電位基準回路領域2とを備えている。そして,高電位基準回路領域2がトレンチ4に囲まれた構造を構成している。勿論,トレンチ4の中は絶縁物で充填されている。すなわち,低電位基準回路領域1と高電位基準回路領域2との間の領域を絶縁体で充填している。また,トレンチ4にて区画された部位にレベルシフト用の高耐圧NMOS5や高耐圧PMOS6が設けられている。
2 高電位基準回路領域(高電位基準回路,第2領域)
3 高耐圧分離領域(第3領域)
4 トレンチ(絶縁隔壁)
5 高耐圧NMOS(中継半導体素子,第4領域)
6 高耐圧PMOS(中継半導体素子,第4領域)
7 P- 型基板(基板領域,半導体基板)
40 トレンチ群(絶縁隔壁群)
50d ドレインN+ 領域(ドレイン)
50g ゲートポリシリコン(ゲート)
50s ソースN+ 領域(ソース)
75 埋め込み絶縁層(絶縁膜)
100 半導体装置
Claims (14)
- 低電位基準回路と高電位基準回路とを混載させ,両者間で信号の伝達を行う半導体装置において,
前記低電位基準回路の領域と前記高電位基準回路の領域との間に位置する高耐圧分離領域と,
前記低電位基準回路と前記高電位基準回路との間の信号の伝達を媒介する中継半導体素子と,
前記低電位基準回路の領域と前記高電位基準回路の領域との少なくとも一方の領域と,前記中継半導体素子との間に位置し,トレンチ状の溝に絶縁物が充填されたものである絶縁隔壁とを備え,
前記中継半導体素子の出力配線が前記絶縁隔壁を跨いで出力側の回路領域に配されていることを特徴とする半導体装置。 - 請求項1に記載する半導体装置において,
前記低電位基準回路および前記高電位基準回路の下方に位置する基板領域を有し,
前記絶縁隔壁は,その底部が前記基板領域にまで達しているとともに厚さ方向から見て前記中継半導体素子を包囲していることを特徴とする半導体装置。 - 請求項1または請求項2に記載する半導体装置において,
前記低電位基準回路の領域と前記高電位基準回路の領域との間に位置し,前記低電位基準回路の領域から前記高電位基準回路の領域までの間を複数の領域に区画する絶縁隔壁群を備えることを特徴とする半導体装置。 - 低電位基準回路と高電位基準回路とを混載させ,両者間で信号の伝達を行う半導体装置において,
前記低電位基準回路と前記高電位基準回路との間の信号の伝達を媒介し,トレンチ状の溝に絶縁物が充填された絶縁隔壁に包囲された中継半導体素子を備え,
前記中継半導体素子が複数設けられ,それらを環状に組み合わせることで前記低電位基準回路の領域と前記高電位基準回路の領域とが区画されており,それらの中継半導体素子の出力配線が前記絶縁隔壁を跨いで出力側の回路領域に配されていることを特徴とする半導体装置。 - 請求項1または請求項4に記載する半導体装置において,
前記低電位基準回路および前記高電位基準回路の下方に位置する基板領域と,
前記低電位基準回路および前記高電位基準回路と前記基板領域との間に位置し,前記低電位基準回路および前記高電位基準回路と前記基板領域とを絶縁する絶縁層を有し,
前記絶縁隔壁は,その底部が前記絶縁層にまで達しているとともに厚さ方向から見て前記中継半導体素子を包囲していることを特徴とする半導体装置。 - 第1導電型の半導体基板と,
前記半導体基板の主表面上に形成され,低電位基準回路領域をなす第2導電型の第1領域と,
前記第1領域と離間して前記半導体基板の上に形成され,高電位基準回路領域をなす第2導電型の第2領域と,
前記第1領域と前記第2領域との間に位置し,表面から見て前記第1領域または前記第2領域のうちの一方を取り囲むように環状に形成され,高耐圧終端領域をなす第3領域と,
前記第3領域と環状構造を一体化する形で配置され,前記第1領域と前記第2領域との間の信号伝達を媒介する中継半導体素子領域をなす第4領域と,
前記第1領域または前記第2領域のうちの少なくとも一方と前記第4領域との間に位置し,トレンチ状の溝に絶縁物が充填された絶縁隔壁とを備え,
前記第4領域の中継半導体素子の出力配線が,前記絶縁隔壁を跨いで出力側の回路領域に配されていることを特徴とする半導体装置。 - 第1導電型または第2導電型の半導体基板と,
前記半導体基板の主表面上に形成された絶縁膜と,
前記絶縁膜上に形成され,低電位基準回路領域をなす第2導電型の第1領域と,
前記第1領域と離間して前記絶縁膜上に形成され,高電位基準回路領域をなす第2導電型の第2領域と,
前記第1領域と前記第2領域との間に位置し,表面から見て前記第1領域または前記第2領域のうちの一方を取り囲むように環状に形成され,高耐圧終端領域をなす第3領域と,
前記第3領域と環状構造を一体化する形で配置され,前記第1領域と前記第2領域との間の信号伝達を媒介する中継半導体素子領域をなす第4領域と,
前記第1領域または前記第2領域のうちの少なくとも一方と前記第4領域との間に位置し,トレンチ状の溝に絶縁物が充填された絶縁隔壁とを備え,
前記第4領域の中継半導体素子の出力配線が,前記絶縁隔壁を跨いで出力側の回路領域に配されていることを特徴とする半導体装置。 - 請求項6または請求項7に記載する半導体装置において,
前記絶縁隔壁は,その底部が下方に位置する前記半導体基板または前記絶縁膜に達しているとともに,表面から見て前記第4領域の中継半導体素子の周囲を,少なくとも3方向包囲していることを特徴とする半導体装置 - 請求項6または請求項7に記載する半導体装置において,
前記第3領域が,PN接合により高耐圧を維持する接合分離型の構造をなすことを特徴とする半導体装置。 - 請求項6または請求項7に記載する半導体装置において,
前記第3領域が,複数の絶縁隔壁群により高耐圧を維持する絶縁分離型の構造をなすことを特徴とする半導体装置。 - 請求項10に記載する半導体装置において,
前記絶縁隔壁群により区画された領域は,前記絶縁隔壁を誘電体膜とするコンデンサ構造を有し,前記第1領域側から前記第2領域側に向けて漸進的に電位が上昇するように形成されていることを特徴とする半導体装置。 - 第1導電型の半導体基板と,
前記半導体基板の主表面上に形成され,低電位基準回路領域をなす第2導電型の第1領域と,
前記第1領域と離間して前記半導体基板上に形成され,高電位基準回路領域をなす第2導電型の第2領域と,
前記第1領域と前記第2領域との間に位置し,表面から見て前記第1領域または前記第2領域のうちの一方を取り囲むように環状に組み合わされて形成され,中継半導体素子領域をなす複数の第4領域と,
前記第1領域または前記第2領域のうちの少なくとも一方と前記第4領域との間に位置し,トレンチ状の溝に絶縁物が充填された絶縁隔壁とを備え,
前記第4領域の中継半導体素子の出力配線が,前記絶縁隔壁を跨いで出力側の回路領域に配されていることを特徴とする半導体装置。 - 第1導電型または第2導電型の半導体基板と,
前記半導体基板の主表面上に形成された絶縁膜と,
前記絶縁膜上に形成され,低電位基準回路領域をなす第2導電型の第1領域と,
前記第1領域と離間して前記絶縁膜上に形成され,高電位基準回路領域をなす第2導電型の第2領域と,
前記第1領域と前記第2領域との間に位置し,表面から見て前記第1領域または前記第2領域のうちの一方を取り囲むように環状に組み合わされて形成され,中継半導体素子領域をなす複数の第4領域と,
前記第1領域または前記第2領域のうちの少なくとも一方と前記第4領域との間に位置し,トレンチ状の溝に絶縁物が充填された絶縁隔壁とを備え,
前記第4領域の中継半導体素子の出力配線が,前記絶縁隔壁を跨いで出力側の回路領域に配されていることを特徴とする半導体装置。 - 請求項12または請求項13に記載する半導体装置において,
前記絶縁隔壁は,その底部が下方に位置する前記半導体基板または前記絶縁膜に達しているとともに,表面から見て前記第4領域の中継半導体素子の周囲を,少なくとも3方向包囲していることを特徴とする半導体装置
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US10/576,292 US7538407B2 (en) | 2003-10-20 | 2004-10-08 | Semiconductor apparatus |
PCT/JP2004/015328 WO2005038921A1 (en) | 2003-10-20 | 2004-10-08 | Semiconductor apparatus |
CN200480030738A CN100587955C (zh) | 2003-10-20 | 2004-10-08 | 半导体装置 |
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US10217861B2 (en) | 2016-03-18 | 2019-02-26 | Fuji Electric Co., Ltd. | High voltage integrated circuit with high voltage junction termination region |
JP2018195640A (ja) * | 2017-05-15 | 2018-12-06 | 三菱電機株式会社 | 半導体装置、半導体装置の製造方法、および電力変換装置 |
JP2022010220A (ja) * | 2018-12-28 | 2022-01-14 | 三菱電機株式会社 | 半導体装置 |
JP7160167B2 (ja) | 2018-12-28 | 2022-10-25 | 三菱電機株式会社 | 半導体装置 |
US11562995B2 (en) | 2019-04-11 | 2023-01-24 | Fuji Electric Co., Ltd. | Semiconductor integrated circuit |
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WO2005038921A1 (en) | 2005-04-28 |
KR20060099528A (ko) | 2006-09-19 |
JP4654574B2 (ja) | 2011-03-23 |
KR100767075B1 (ko) | 2007-10-15 |
CN100587955C (zh) | 2010-02-03 |
EP1676320A1 (en) | 2006-07-05 |
US20070085595A1 (en) | 2007-04-19 |
US7538407B2 (en) | 2009-05-26 |
CN1871705A (zh) | 2006-11-29 |
EP1676320B1 (en) | 2015-01-28 |
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