JP2005109483A - 埋込み軽ドープ・ドレイン領域を含む金属酸化膜半導体デバイス - Google Patents
埋込み軽ドープ・ドレイン領域を含む金属酸化膜半導体デバイス Download PDFInfo
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Abstract
【解決手段】MOSデバイスは、第1の導電型の半導体層と、この半導体層内に形成された第2の導電型のソース領域と、この半導体層内に形成され、かつソース領域から離隔された第2の導電型のドレイン領域とを含む。半導体層の上部表面の近傍に、かつ少なくとも部分的にソース領域とドレイン領域の間にゲートが形成される。このMOSデバイスは、さらに半導体層内のゲート領域とドレイン領域の間に形成された第2の導電型の埋込みLDD領域を含む。この埋込みLDD領域はドレイン領域から横方向に離隔され、この埋込みLDD領域内の半導体層の上部表面の近傍に第1の導電型の第2のLDD領域が形成される。第2のLDD領域は、ゲートに自己整合され、かつゲートから横方向に離隔され、その結果ゲートは第2のLDD領域に対して重ならない。
【選択図】図2
Description
Claims (10)
- 第1の導電型の半導体層と、
前記半導体層内に形成された第2の導電型のソース領域と、
前記半導体層内に形成され、前記ソース領域から離隔された前記第2の導電型のドレイン領域と、
前記半導体層の上部表面に近接して、少なくとも部分的に前記ソース領域と前記ドレイン領域の間に形成されたゲートと、
前記半導体層内の前記ゲート領域と前記ドレイン領域の間に形成され、前記ドレイン領域から横方向に離隔された、前記第2の導電型の埋込み軽ドープ・ドレイン(LDD)領域と、
前記埋込みLDD領域内に、前記半導体層の前記上部表面の近傍に形成され、前記ゲートに自己整合され、前記ゲートが前記第2のLDD領域に対して重ならないように前記ゲートから横方向に離隔された、前記第1の導電型の第2のLDD領域とを含む、
金属酸化膜半導体(MOS)デバイス。 - 前記半導体層の前記上部表面の近傍に、少なくとも部分的に前記ゲート領域と前記ドレイン領域の間に形成され、前記ソース領域に電気的に接続され、前記ゲートから横方向に離隔され、前記ゲートに対して実質上重ならないシールド構造体をさらに含む、請求項1に記載のデバイス。
- 前記シールド構造体が、前記ゲートと実質上同時に形成される、請求項2に記載のデバイス。
- 前記ゲートの下の第1の絶縁層および前記シールド構造体の下の第2の絶縁層が、他の絶縁層と異なる厚さで形成される、請求項2に記載のデバイス。
- 前記半導体層の前記上部表面の近傍に、少なくとも部分的に前記第2のLDD領域と前記ドレイン領域の間に形成された整合構造体をさらに含み、前記ドレイン領域が、前記整合構造体の第1の縁部に自己整合され、前記第2のLDD領域が、前記整合構造体の第2の縁部に自己整合され、その結果前記第2のLDD領域が前記ドレイン領域に自己整合する、請求項1に記載のデバイス。
- 少なくとも1つの金属酸化膜半導体(MOS)デバイスを含む集積回路であって、前記少なくとも1つのMOSデバイスが、
第1の導電型の半導体層と、
前記半導体層内に形成された第2の導電型のソース領域と、
前記半導体層内に形成され、前記ソース領域から離隔された前記第2の導電型のドレイン領域と、
前記半導体層の上部表面の近傍に、少なくとも部分的に前記ソース領域とドレイン領域の間に形成されたゲートと、
前記半導体層内の前記ゲート領域と前記ドレイン領域の間に形成され、前記ドレイン領域から横方向に離隔された、前記第2の導電型の埋込み軽ドープ・ドレイン(LDD)領域と、
前記埋込みLDD領域内に、前記半導体層の前記上部表面のすぐ近傍に形成された第2のLDD領域、前記ゲートに自己整合され、前記ゲートが前記第2のLDD領域に対して重ならないように、前記ゲートから横方向に離隔された、前記第1の導電型の第2のLDD領域とを含む、集積回路。 - 金属酸化膜半導体(MOS)デバイスを形成する方法であって、
第2の導電型の半導体層内に、第1の導電型の埋込み軽ドープ・ドレイン(LDD)領域を形成する工程と、
前記半導体層の上部表面上にゲートを形成する工程と、
前記埋込みLDD領域内に、前記半導体層の前記上部表面の近傍に、前記ゲートに自己整合され、前記ゲートが前記第2のLDD領域に対して重ならないように、前記ゲートから横方向に離隔された、前記第2の導電型の第2のLDD領域を形成する工程と、
前記半導体層内に、前記第1の導電型のソースおよびドレイン領域を形成する工程とを含み、前記ゲートが、少なくとも部分的に前記ソース領域とドレイン領域の間に形成される、方法。 - 前記第2のLDD領域を形成する前記工程が、
前記絶縁層の少なくとも一部分の上の、少なくとも部分的に前記ゲート領域と前記ドレイン領域の間に、前記ゲートに自己整合されたシールド構造体を形成する工程と、
前記第2のLDD領域が前記シールド構造体に自己整合するように、前記埋込みLDD領域内に前記第2のLDD領域を形成する工程とを含む、請求項7に記載の方法。 - 前記第2のLDD領域を形成した後に、前記シールド構造体を除去する工程をさらに含む、請求項8に記載の方法。
- 前記シールド構造体を除去する工程と、
前記シールド構造体の下の絶縁層の少なくとも一部分を除去する工程と
前記除去されたシールド構造体が形成された前記絶縁層の少なくとも一部分の上に、新しいシールド構造体を形成する工程とをさらに含む、請求項8に記載の方法。
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US10/675,633 US6927453B2 (en) | 2003-09-30 | 2003-09-30 | Metal-oxide-semiconductor device including a buried lightly-doped drain region |
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JP2008098624A (ja) * | 2006-09-15 | 2008-04-24 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
US8735997B2 (en) | 2006-09-15 | 2014-05-27 | Semiconductor Components Industries, Llc | Semiconductor device having drain/source surrounded by impurity layer and manufacturing method thereof |
KR101520951B1 (ko) | 2009-04-16 | 2015-05-15 | 페어차일드 세미컨덕터 코포레이션 | 자기 정렬된 수직 ldd 및 후면 드레인을 가지는 ldmos |
WO2021241072A1 (ja) * | 2020-05-29 | 2021-12-02 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置 |
Also Published As
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US6927453B2 (en) | 2005-08-09 |
TW200512935A (en) | 2005-04-01 |
US20050191815A1 (en) | 2005-09-01 |
JP2013225685A (ja) | 2013-10-31 |
JP5547361B2 (ja) | 2014-07-09 |
TWI325175B (en) | 2010-05-21 |
US20050067655A1 (en) | 2005-03-31 |
US7297606B2 (en) | 2007-11-20 |
KR20050031914A (ko) | 2005-04-06 |
KR101099907B1 (ko) | 2011-12-28 |
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