JP2005109474A - 均一なミスフィット転位密度を含む緩和SiGe被膜上の引っ張り歪みシリコンおよびその形成方法 - Google Patents
均一なミスフィット転位密度を含む緩和SiGe被膜上の引っ張り歪みシリコンおよびその形成方法 Download PDFInfo
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- JP2005109474A JP2005109474A JP2004275965A JP2004275965A JP2005109474A JP 2005109474 A JP2005109474 A JP 2005109474A JP 2004275965 A JP2004275965 A JP 2004275965A JP 2004275965 A JP2004275965 A JP 2004275965A JP 2005109474 A JP2005109474 A JP 2005109474A
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 108
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 69
- 239000010703 silicon Substances 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 238000002513 implantation Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000006911 nucleation Effects 0.000 abstract description 8
- 238000010899 nucleation Methods 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 239000000243 solution Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 5
- 238000013459 approach Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005280 amorphization Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
【解決手段】圧縮歪みSiGe層がシリコン基板上に形成される。SiGe層上に原子をイオン注入してEOR損傷を与える。この歪みSiGe層を緩和するためにアニールを実施する。このアニール中、格子間型転位ループ(interstitial dislocation loop)がSiGe層内に均一に分布するものとして形成される。この格子間型転位ループが、SiGe層とシリコン基板の間でのミスフィット転位の核生成の基礎となる。格子間型転位ループが均一に分布するので、このミスフィット転位も均一に分布し、それによってSiGe層が緩和される。引っ張り歪みシリコン層が緩和SiGe層上に形成される。
【選択図】図3
Description
12 SiGe層
14 アモルファス層
16 格子間型転位ループ
18 ミスフィット転位
20 シリコン層
Claims (20)
- 圧縮歪みSiGe層をシリコン基板上に形成するステップと、
前記SiGe層中に均一に分布した格子間型転位ループを形成するように原子をイオン注入するステップと、
前記SiGe層中に均一に分布したミスフィット転位を形成するためにアニールするステップとを含む、半導体デバイスの製造方法。 - 前記SiGe層を形成するステップが、前記シリコン基板上にSiGe層をエピタキシャル成長させるステップを含む、請求項1に記載の方法。
- 前記SiGe層が約100Å〜10000Åの厚さで形成される、請求項2に記載の方法。
- 前記SiGe層上に引っ張り歪みシリコン層を形成するステップをさらに含む、請求項1に記載の方法。
- 前記原子をイオン注入するステップが前記SiGe層内にEOR損傷を引き起こす、請求項1に記載の方法。
- 前記原子をイオン注入するステップが前記SiGe層の表面部分内にアモルファス層を形成させる、請求項1に記載の方法。
- 前記原子がGeまたはSiである、請求項1に記載の方法。
- 前記原子が、約1×1014原子/cm2〜1×1016原子/cm2の注入濃度、約5KeV〜100KeVの注入エネルギでイオン注入される、請求項1に記載の方法。
- 前記アニール・ステップが、約500℃〜1100℃の温度で約1秒〜30分間、実施される、請求項1に記載の方法。
- 前記格子間型転位ループの密度が、約1×105ループ/cm2〜1×1012ループ/cm2である、請求項1に記載の方法。
- 前記ミスフィット転位の密度が、約1×105#/cm2〜1×1012#/cm2である、請求項10に記載の方法。
- 圧縮歪みSiGe層をシリコン基板上に形成するステップと、
前記SiGe層上に制御可能に原子をイオン注入し、それによってその内部に均一に分布したEORを生じさせるステップと、
前記SiGe層中に均一に分布した格子間型転位ループを形成するためにアニールするステップであって、前記均一に分布した格子間型転位ループが前記SiGe層中に均一に分布したミスフィット転位を核生成させるステップと、
前記SiGe層上に引っ張り歪みシリコン層を形成するステップとを含む、半導体基板の形成方法。 - 前記原子をイオン注入するステップが前記SiGe層の表面部分内にアモルファス層を形成させる、請求項12に記載の方法。
- 前記原子がGeまたはSiである、請求項12に記載の方法。
- 前記原子が、約1×1014原子/cm2〜1×1016原子/cm2の注入濃度、約5KeV〜100KeVの注入エネルギでイオン注入される、請求項12に記載の方法。
- 前記アニール・ステップが、約500℃〜1100℃の温度で約1秒〜30分間、実施される、請求項12に記載の方法。
- シリコン基板と、
前記シリコン基板上に形成され、均一に分布したミスフィット転位を含む緩和SiGe層と、
前記緩和SiGe層上に形成され引っ張り歪みを受けたシリコン層とを備える、半導体デバイス。 - 前記SiGe層中の前記ミスフィット転位の密度が、約1×105#/cm2〜1×1012#/cm2である、請求項17に記載の方法。
- 前記ミスフィット転位が、上から見てグリッド形状に配列されている、請求項17に記載の方法。
- 前記SiGe層が約100Å〜10000Åの厚さで形成される、請求項17に記載の方法。
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US10/667,603 US6872641B1 (en) | 2003-09-23 | 2003-09-23 | Strained silicon on relaxed sige film with uniform misfit dislocation density |
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Cited By (3)
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JP2007227887A (ja) * | 2006-01-17 | 2007-09-06 | Soi Tec Silicon On Insulator Technologies Sa | 半導体材料で作られた基板の表面上または基板内の歪みを調節するプロセス |
JP2009503813A (ja) * | 2005-07-22 | 2009-01-29 | ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア | シリコンゲルマニウムバッファ層における転位位置を制御するための方法 |
JP2010532585A (ja) * | 2007-06-29 | 2010-10-07 | エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド | 高ドープ基板の拡散制御 |
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US20050064686A1 (en) | 2005-03-24 |
CN1326207C (zh) | 2007-07-11 |
US6872641B1 (en) | 2005-03-29 |
US7964865B2 (en) | 2011-06-21 |
US20050164477A1 (en) | 2005-07-28 |
CN1601699A (zh) | 2005-03-30 |
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