JP2005101771A5 - - Google Patents

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Publication number
JP2005101771A5
JP2005101771A5 JP2003330572A JP2003330572A JP2005101771A5 JP 2005101771 A5 JP2005101771 A5 JP 2005101771A5 JP 2003330572 A JP2003330572 A JP 2003330572A JP 2003330572 A JP2003330572 A JP 2003330572A JP 2005101771 A5 JP2005101771 A5 JP 2005101771A5
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JP
Japan
Prior art keywords
circuit
data
clock
buffer
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2003330572A
Other languages
English (en)
Japanese (ja)
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JP2005101771A (ja
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Publication date
Application filed filed Critical
Priority to JP2003330572A priority Critical patent/JP2005101771A/ja
Priority claimed from JP2003330572A external-priority patent/JP2005101771A/ja
Priority to CNB2004100782912A priority patent/CN100337449C/zh
Priority to US10/944,938 priority patent/US7135897B2/en
Publication of JP2005101771A publication Critical patent/JP2005101771A/ja
Publication of JP2005101771A5 publication Critical patent/JP2005101771A5/ja
Withdrawn legal-status Critical Current

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JP2003330572A 2003-09-22 2003-09-22 クロック乗せ替え回路および方法 Withdrawn JP2005101771A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003330572A JP2005101771A (ja) 2003-09-22 2003-09-22 クロック乗せ替え回路および方法
CNB2004100782912A CN100337449C (zh) 2003-09-22 2004-09-21 时钟再同步器
US10/944,938 US7135897B2 (en) 2003-09-22 2004-09-21 Clock resynchronizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003330572A JP2005101771A (ja) 2003-09-22 2003-09-22 クロック乗せ替え回路および方法

Publications (2)

Publication Number Publication Date
JP2005101771A JP2005101771A (ja) 2005-04-14
JP2005101771A5 true JP2005101771A5 (https=) 2006-08-24

Family

ID=34308913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003330572A Withdrawn JP2005101771A (ja) 2003-09-22 2003-09-22 クロック乗せ替え回路および方法

Country Status (3)

Country Link
US (1) US7135897B2 (https=)
JP (1) JP2005101771A (https=)
CN (1) CN100337449C (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7248848B2 (en) * 2004-06-30 2007-07-24 Matthews Phillip M Communication apparatus including dual timer units
US20080075057A1 (en) * 2006-09-25 2008-03-27 Mediatek Inc. Frequency correction burst detection
JP5878069B2 (ja) * 2012-04-11 2016-03-08 アイキューブド研究所株式会社 データ転送装置、データ転送方法、およびプログラム
US9997220B2 (en) * 2016-08-22 2018-06-12 Micron Technology, Inc. Apparatuses and methods for adjusting delay of command signal path

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0656997B2 (ja) 1986-11-29 1994-07-27 富士電機株式会社 エラステイツクバツフア回路
US5340644A (en) 1990-10-05 1994-08-23 Hercules Incorporated Organosilicon compositions
US5497405A (en) * 1993-07-01 1996-03-05 Dsc Communications Corporation Open loop desynchronizer
US5631920A (en) * 1993-11-29 1997-05-20 Lexmark International, Inc. Spread spectrum clock generator
DE19820572A1 (de) * 1998-05-08 1999-11-11 Alcatel Sa Desynchronisiereinrichtung für ein synchrones digitales Nachrichtenübertragungssystem
KR19990086737A (ko) * 1998-05-29 1999-12-15 이계철 비동기식 선입선출 시스템의 제어 장치
JP3447586B2 (ja) * 1998-10-22 2003-09-16 Ｎｅｃエレクトロニクス株式会社 クロック同期化方法及びその装置
US6865241B1 (en) * 1999-12-15 2005-03-08 Lexmark International, Inc. Method and apparatus for sampling digital data at a virtually constant rate, and transferring that data into a non-constant sampling rate device
JP3815948B2 (ja) * 2000-04-20 2006-08-30 シャープ株式会社 Ｆｉｆｏメモリ制御回路
CN1153217C (zh) * 2001-06-07 2004-06-09 扬智科技股份有限公司 非同步fifo控制器

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