JP2005101771A - クロック乗せ替え回路および方法 - Google Patents

クロック乗せ替え回路および方法 Download PDF

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Publication number
JP2005101771A
JP2005101771A JP2003330572A JP2003330572A JP2005101771A JP 2005101771 A JP2005101771 A JP 2005101771A JP 2003330572 A JP2003330572 A JP 2003330572A JP 2003330572 A JP2003330572 A JP 2003330572A JP 2005101771 A JP2005101771 A JP 2005101771A
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Japan
Prior art keywords
data
output
clock
buffer
circuit
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2003330572A
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English (en)
Japanese (ja)
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JP2005101771A5 (https=
Inventor
Koki Imamura
幸喜 今村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2003330572A priority Critical patent/JP2005101771A/ja
Priority to CNB2004100782912A priority patent/CN100337449C/zh
Priority to US10/944,938 priority patent/US7135897B2/en
Publication of JP2005101771A publication Critical patent/JP2005101771A/ja
Publication of JP2005101771A5 publication Critical patent/JP2005101771A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop

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  • Synchronisation In Digital Transmission Systems (AREA)
JP2003330572A 2003-09-22 2003-09-22 クロック乗せ替え回路および方法 Withdrawn JP2005101771A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003330572A JP2005101771A (ja) 2003-09-22 2003-09-22 クロック乗せ替え回路および方法
CNB2004100782912A CN100337449C (zh) 2003-09-22 2004-09-21 时钟再同步器
US10/944,938 US7135897B2 (en) 2003-09-22 2004-09-21 Clock resynchronizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003330572A JP2005101771A (ja) 2003-09-22 2003-09-22 クロック乗せ替え回路および方法

Publications (2)

Publication Number Publication Date
JP2005101771A true JP2005101771A (ja) 2005-04-14
JP2005101771A5 JP2005101771A5 (https=) 2006-08-24

Family

ID=34308913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003330572A Withdrawn JP2005101771A (ja) 2003-09-22 2003-09-22 クロック乗せ替え回路および方法

Country Status (3)

Country Link
US (1) US7135897B2 (https=)
JP (1) JP2005101771A (https=)
CN (1) CN100337449C (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013219646A (ja) * 2012-04-11 2013-10-24 I-Cubed Research Center Inc データ転送装置、データ転送方法、およびプログラム

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7248848B2 (en) * 2004-06-30 2007-07-24 Matthews Phillip M Communication apparatus including dual timer units
US20080075057A1 (en) * 2006-09-25 2008-03-27 Mediatek Inc. Frequency correction burst detection
US9997220B2 (en) * 2016-08-22 2018-06-12 Micron Technology, Inc. Apparatuses and methods for adjusting delay of command signal path

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0656997B2 (ja) 1986-11-29 1994-07-27 富士電機株式会社 エラステイツクバツフア回路
US5340644A (en) 1990-10-05 1994-08-23 Hercules Incorporated Organosilicon compositions
US5497405A (en) * 1993-07-01 1996-03-05 Dsc Communications Corporation Open loop desynchronizer
US5631920A (en) * 1993-11-29 1997-05-20 Lexmark International, Inc. Spread spectrum clock generator
DE19820572A1 (de) * 1998-05-08 1999-11-11 Alcatel Sa Desynchronisiereinrichtung für ein synchrones digitales Nachrichtenübertragungssystem
KR19990086737A (ko) * 1998-05-29 1999-12-15 이계철 비동기식 선입선출 시스템의 제어 장치
JP3447586B2 (ja) * 1998-10-22 2003-09-16 Ｎｅｃエレクトロニクス株式会社 クロック同期化方法及びその装置
US6865241B1 (en) * 1999-12-15 2005-03-08 Lexmark International, Inc. Method and apparatus for sampling digital data at a virtually constant rate, and transferring that data into a non-constant sampling rate device
JP3815948B2 (ja) * 2000-04-20 2006-08-30 シャープ株式会社 Ｆｉｆｏメモリ制御回路
CN1153217C (zh) * 2001-06-07 2004-06-09 扬智科技股份有限公司 非同步fifo控制器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013219646A (ja) * 2012-04-11 2013-10-24 I-Cubed Research Center Inc データ転送装置、データ転送方法、およびプログラム

Also Published As

Publication number Publication date
CN1601994A (zh) 2005-03-30
US20050062525A1 (en) 2005-03-24
US7135897B2 (en) 2006-11-14
CN100337449C (zh) 2007-09-12

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