JP2005093909A - 基板処理方法及び基板処理装置 - Google Patents

基板処理方法及び基板処理装置 Download PDF

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Publication number
JP2005093909A
JP2005093909A JP2003328226A JP2003328226A JP2005093909A JP 2005093909 A JP2005093909 A JP 2005093909A JP 2003328226 A JP2003328226 A JP 2003328226A JP 2003328226 A JP2003328226 A JP 2003328226A JP 2005093909 A JP2005093909 A JP 2005093909A
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Japan
Prior art keywords
chamber
metal
film
silicon compound
substrate processing
Prior art date
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Pending
Application number
JP2003328226A
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English (en)
Japanese (ja)
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JP2005093909A5 (https=
Inventor
Yasuo Kobayashi
林 保 男 小
Takeshi Hashimoto
本 毅 橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP2003328226A priority Critical patent/JP2005093909A/ja
Priority to PCT/JP2004/012647 priority patent/WO2005029562A1/ja
Priority to CNA2004800268715A priority patent/CN1853259A/zh
Priority to KR1020067005453A priority patent/KR100855767B1/ko
Priority to US10/571,256 priority patent/US20070032073A1/en
Publication of JP2005093909A publication Critical patent/JP2005093909A/ja
Publication of JP2005093909A5 publication Critical patent/JP2005093909A5/ja
Pending legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/50Alloying conductive materials with semiconductor bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation

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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2003328226A 2003-09-19 2003-09-19 基板処理方法及び基板処理装置 Pending JP2005093909A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2003328226A JP2005093909A (ja) 2003-09-19 2003-09-19 基板処理方法及び基板処理装置
PCT/JP2004/012647 WO2005029562A1 (ja) 2003-09-19 2004-09-01 基板処理方法及び基板処理装置
CNA2004800268715A CN1853259A (zh) 2003-09-19 2004-09-01 基板处理方法和基板处理装置
KR1020067005453A KR100855767B1 (ko) 2003-09-19 2004-09-01 기판처리방법
US10/571,256 US20070032073A1 (en) 2003-09-19 2004-09-01 Method of substrate processing and apparatus for substrate processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003328226A JP2005093909A (ja) 2003-09-19 2003-09-19 基板処理方法及び基板処理装置

Publications (2)

Publication Number Publication Date
JP2005093909A true JP2005093909A (ja) 2005-04-07
JP2005093909A5 JP2005093909A5 (https=) 2006-10-26

Family

ID=34372894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003328226A Pending JP2005093909A (ja) 2003-09-19 2003-09-19 基板処理方法及び基板処理装置

Country Status (5)

Country Link
US (1) US20070032073A1 (https=)
JP (1) JP2005093909A (https=)
KR (1) KR100855767B1 (https=)
CN (1) CN1853259A (https=)
WO (1) WO2005029562A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214538A (ja) * 2006-01-11 2007-08-23 Renesas Technology Corp 半導体装置およびその製造方法
US7867789B2 (en) * 2005-07-18 2011-01-11 Applied Materials, Inc. Contact clean by remote plasma and repair of silicide surface

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100920054B1 (ko) * 2008-02-14 2009-10-07 주식회사 하이닉스반도체 반도체 소자의 제조방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613403A (ja) * 1992-03-02 1994-01-21 Digital Equip Corp <Dec> Mos集積回路上の自己整列珪化コバルト
JPH0738104A (ja) * 1993-07-22 1995-02-07 Toshiba Corp 半導体装置の製造方法
JP2001053055A (ja) * 1999-08-13 2001-02-23 Tokyo Electron Ltd 処理装置及び処理方法
JP2001244214A (ja) * 2000-01-29 2001-09-07 Samsung Electronics Co Ltd シリサイド膜を備えた半導体素子の製造方法
JP2001274111A (ja) * 1999-11-09 2001-10-05 Applied Materials Inc サリサイド・プロセス用の化学的プラズマ洗浄

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0950973A (ja) * 1995-08-10 1997-02-18 Sony Corp シリサイド層の形成方法
US6114216A (en) * 1996-11-13 2000-09-05 Applied Materials, Inc. Methods for shallow trench isolation
US6706334B1 (en) * 1997-06-04 2004-03-16 Tokyo Electron Limited Processing method and apparatus for removing oxide film
US6494959B1 (en) * 2000-01-28 2002-12-17 Applied Materials, Inc. Process and apparatus for cleaning a silicon surface
US6335249B1 (en) * 2000-02-07 2002-01-01 Taiwan Semiconductor Manufacturing Company Salicide field effect transistors with improved borderless contact structures and a method of fabrication
JP4493796B2 (ja) * 2000-03-30 2010-06-30 東京エレクトロン株式会社 誘電体膜の形成方法
KR100434110B1 (ko) * 2002-06-04 2004-06-04 삼성전자주식회사 반도체 장치의 제조방법
KR100452273B1 (ko) * 2002-10-22 2004-10-08 삼성전자주식회사 챔버의 클리닝 방법 및 반도체 소자 제조 방법
KR100688493B1 (ko) * 2003-06-17 2007-03-02 삼성전자주식회사 폴리실리콘 콘택 플러그를 갖는 금속-절연막-금속캐패시터 및 그 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613403A (ja) * 1992-03-02 1994-01-21 Digital Equip Corp <Dec> Mos集積回路上の自己整列珪化コバルト
JPH0738104A (ja) * 1993-07-22 1995-02-07 Toshiba Corp 半導体装置の製造方法
JP2001053055A (ja) * 1999-08-13 2001-02-23 Tokyo Electron Ltd 処理装置及び処理方法
JP2001274111A (ja) * 1999-11-09 2001-10-05 Applied Materials Inc サリサイド・プロセス用の化学的プラズマ洗浄
JP2001244214A (ja) * 2000-01-29 2001-09-07 Samsung Electronics Co Ltd シリサイド膜を備えた半導体素子の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7867789B2 (en) * 2005-07-18 2011-01-11 Applied Materials, Inc. Contact clean by remote plasma and repair of silicide surface
US9147578B2 (en) 2005-07-18 2015-09-29 Applied Materials, Inc. Contact clean by remote plasma and repair of silicide surface
JP2007214538A (ja) * 2006-01-11 2007-08-23 Renesas Technology Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
KR100855767B1 (ko) 2008-09-01
US20070032073A1 (en) 2007-02-08
WO2005029562A1 (ja) 2005-03-31
CN1853259A (zh) 2006-10-25
KR20060090224A (ko) 2006-08-10

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