CN1853259A - 基板处理方法和基板处理装置 - Google Patents

基板处理方法和基板处理装置 Download PDF

Info

Publication number
CN1853259A
CN1853259A CNA2004800268715A CN200480026871A CN1853259A CN 1853259 A CN1853259 A CN 1853259A CN A2004800268715 A CNA2004800268715 A CN A2004800268715A CN 200480026871 A CN200480026871 A CN 200480026871A CN 1853259 A CN1853259 A CN 1853259A
Authority
CN
China
Prior art keywords
film
metal
silicon compound
substrate processing
processing method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2004800268715A
Other languages
English (en)
Chinese (zh)
Inventor
小林保男
桥本毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of CN1853259A publication Critical patent/CN1853259A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/50—Alloying conductive materials with semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CNA2004800268715A 2003-09-19 2004-09-01 基板处理方法和基板处理装置 Pending CN1853259A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP328226/2003 2003-09-19
JP2003328226A JP2005093909A (ja) 2003-09-19 2003-09-19 基板処理方法及び基板処理装置

Publications (1)

Publication Number Publication Date
CN1853259A true CN1853259A (zh) 2006-10-25

Family

ID=34372894

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2004800268715A Pending CN1853259A (zh) 2003-09-19 2004-09-01 基板处理方法和基板处理装置

Country Status (5)

Country Link
US (1) US20070032073A1 (https=)
JP (1) JP2005093909A (https=)
KR (1) KR100855767B1 (https=)
CN (1) CN1853259A (https=)
WO (1) WO2005029562A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7550381B2 (en) 2005-07-18 2009-06-23 Applied Materials, Inc. Contact clean by remote plasma and repair of silicide surface
JP2007214538A (ja) * 2006-01-11 2007-08-23 Renesas Technology Corp 半導体装置およびその製造方法
KR100920054B1 (ko) * 2008-02-14 2009-10-07 주식회사 하이닉스반도체 반도체 소자의 제조방법

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW209308B (en) * 1992-03-02 1993-07-11 Digital Equipment Corp Self-aligned cobalt silicide on MOS integrated circuits
JPH0738104A (ja) * 1993-07-22 1995-02-07 Toshiba Corp 半導体装置の製造方法
JPH0950973A (ja) * 1995-08-10 1997-02-18 Sony Corp シリサイド層の形成方法
US6114216A (en) * 1996-11-13 2000-09-05 Applied Materials, Inc. Methods for shallow trench isolation
US6706334B1 (en) * 1997-06-04 2004-03-16 Tokyo Electron Limited Processing method and apparatus for removing oxide film
JP4057198B2 (ja) * 1999-08-13 2008-03-05 東京エレクトロン株式会社 処理装置及び処理方法
JP2001274111A (ja) * 1999-11-09 2001-10-05 Applied Materials Inc サリサイド・プロセス用の化学的プラズマ洗浄
US6494959B1 (en) * 2000-01-28 2002-12-17 Applied Materials, Inc. Process and apparatus for cleaning a silicon surface
KR100316721B1 (ko) * 2000-01-29 2001-12-12 윤종용 실리사이드막을 구비한 반도체소자의 제조방법
US6335249B1 (en) * 2000-02-07 2002-01-01 Taiwan Semiconductor Manufacturing Company Salicide field effect transistors with improved borderless contact structures and a method of fabrication
JP4493796B2 (ja) * 2000-03-30 2010-06-30 東京エレクトロン株式会社 誘電体膜の形成方法
KR100434110B1 (ko) * 2002-06-04 2004-06-04 삼성전자주식회사 반도체 장치의 제조방법
KR100452273B1 (ko) * 2002-10-22 2004-10-08 삼성전자주식회사 챔버의 클리닝 방법 및 반도체 소자 제조 방법
KR100688493B1 (ko) * 2003-06-17 2007-03-02 삼성전자주식회사 폴리실리콘 콘택 플러그를 갖는 금속-절연막-금속캐패시터 및 그 제조방법

Also Published As

Publication number Publication date
KR100855767B1 (ko) 2008-09-01
US20070032073A1 (en) 2007-02-08
WO2005029562A1 (ja) 2005-03-31
JP2005093909A (ja) 2005-04-07
KR20060090224A (ko) 2006-08-10

Similar Documents

Publication Publication Date Title
CN1260786C (zh) 形成硅化钴的方法和装置组
US6811448B1 (en) Pre-cleaning for silicidation in an SMOS process
US5963833A (en) Method for cleaning semiconductor wafers and
CN101075577B (zh) 半导体装置的制造方法
CN1216415C (zh) 沉积金属薄膜的方法和包括超临界干燥/清洁组件的金属沉积组合工具
CN1967780A (zh) 用于制作场效应晶体管的栅极电介质的方法
JP4084790B2 (ja) シリサイド薄膜を有する半導体素子の製造方法
CN1230769A (zh) 半导体器件制造方法
JP4914573B2 (ja) 高誘電体ゲート絶縁膜及び金属ゲート電極を有する電界効果トランジスタの製造方法
CN1853259A (zh) 基板处理方法和基板处理装置
CN1507018A (zh) 半导体集成电路器件的制造方法
KR20100036255A (ko) 반도체 웨이퍼의 보호 방법 및 반도체 장치의 제조 방법
US20230010499A1 (en) Integrated wet clean for gate stack development
CN1855388A (zh) 以添加物改善金属硅化物热稳定度的方法
JP3033525B2 (ja) 半導体装置の製造方法
CN1707755A (zh) 使用氮化铝膜制造半导体器件的栅极的方法
CN113327888A (zh) 半导体结构的制造方法
CN1700422A (zh) 改善金属硅化物工艺产生桥连现象的清洗方法
JP2005093909A5 (https=)
US20230115130A1 (en) Methods for preparing metal silicides
CN1713401A (zh) 一种锗硅肖特基二极管及其制作方法
KR101057757B1 (ko) 반도체 소자의 제조 방법
Jung et al. The effect of precleaning treatments on the formation of Ti silicide
CN101211768A (zh) 栅极电极及其形成方法
CN1862779A (zh) 金属硅化物的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication