JP2005045258A - Si1−xGex層の選択的エッチングを用いるシリコンオンナッシング(SON)MOSFETの製造 - Google Patents
Si1−xGex層の選択的エッチングを用いるシリコンオンナッシング(SON)MOSFETの製造 Download PDFInfo
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- 238000005530 etching Methods 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229910006990 Si1-xGex Inorganic materials 0.000 title 1
- 229910007020 Si1−xGex Inorganic materials 0.000 title 1
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 96
- 239000010703 silicon Substances 0.000 claims abstract description 96
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 95
- 238000000034 method Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 27
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 16
- 230000007547 defect Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Abstract
【解決手段】 本発明による方法は、シリコン基板を準備する工程と、該シリコン基板上にエピタキシャルSi1−xGex層を成長させる工程と、該エピタキシャルSi1−xGex層上に薄いエピタキシャル上部シリコン層を成長させる工程と、該上部シリコンおよびSi1−xGexを該シリコン基板内部までトレンチエッチングする工程と、該Si1−xGex層を選択的にエッチングする工程と、CVDによってSiO2の層を堆積して、該第1のトレンチを充填する工程と、トレンチエッチングして、第2のトレンチを形成する工程と、残りの該Si1−xGex層を選択的にエッチングする工程と、該第2のトレンチを充填する工程と、現在の技術レベルのCMOS製造技術によって構造を完成させる工程とを含む。
【選択図】 図14
Description
R.Koh、「Buried Layer Engineering to Reduce the Drain−Induced Barrier Lowering of Sub−0.05um SOI−MOSFET」(Jpn.J.Appl.Phys.、Vol.38、P.2294(1999) R.Chauら、「A 50nm Depleted−Substrate CMOS Transistor」(IEDM、p.621、2001) M.Jurczakら、「SON(Silicon−on−Nothing)−A New Device Architecture for the ULSI Era」(VLSI Tech.Dig.、p.29、1999) M.Jurczakら、「Silicon−on−Nothing(SON)−an innovative Process for Advanced CMOS」(IEEE Trans.El.Dev.Vol.47、pp2179−2187(2000)) T.Satoら、「SON(Silicon on Nothing)MOSFET Using ESS(Empty Space in Silicon)Technique for SoC Application」(IEDM、p.809、2001)
Si1−xGex層の選択的エッチングを用いるシリコンオンナッシング(SON)MOSFETの製造方法は、シリコン基板を準備する工程と、該シリコン基板上にエピタキシャルSi1−xGex層を成長させる工程と、該エピタキシャルSi1−xGex層上に薄いエピタキシャル上部シリコン層を成長させる工程と、該上部シリコンおよびSi1−xGexを該シリコン基板内部までトレンチエッチングして、第1のトレンチを形成する工程と、エアーギャップを形成するように実質的に全てのSi1−xGexを除去するために、該Si1−xGex層を選択的にエッチングする工程と、CVDによってSiO2の層を堆積して、該第1のトレンチを充填する工程と、トレンチエッチングして、第2のトレンチを形成する工程と、残りの該Si1−xGex層を選択的にエッチングする工程と、CVDによってSiO2の第2の層を堆積して、該第2のトレンチを充填する工程であって、これにより、ソース、ドレインおよびチャネルを該基板から切り離す、工程と、現在の技術レベルのCMOS製造技術によって構造を完成させる工程とを含む。
Si1−xGex層の選択的エッチングを用いるシリコンオンナッシング(SON)MOSFETの製造方法は、シリコン基板を準備する工程と、該シリコン基板上にエピタキシャルSi1−xGex層を成長させる工程と、該エピタキシャルSi1−xGex層上に薄いエピタキシャル上部シリコン層を成長させる工程と、該上部シリコンおよびSi1−xGexを該シリコン基板内部までトレンチエッチングして、第1のトレンチを形成する工程と、エアーギャップを形成するように実質的に全てのSi1−xGexを除去するために、該Si1−xGex層を選択的にエッチングする工程と、CVDによってSiO2の層を堆積して、該第1のトレンチを充填する工程と、トレンチエッチングして、第2のトレンチを形成する工程と、残りの該Si1−xGex層を選択的にエッチングする工程と、CVDによってSiO2の第2の層を堆積して、該第2のトレンチを充填する工程であって、これにより、ソース、ドレインおよびチャネルを該基板から切り離す、工程と、現在の技術レベルのCMOS製造技術によって構造を完成させる工程とを含む。
34 上部シリコン層
36 ゲート誘電層
38 ポリシリコン
46 エアーギャップ
56 酸化物
58 第2のポリシリコン層
Claims (9)
- Si1−xGex層の選択的エッチングを用いるシリコンオンナッシング(SON)MOSFETの製造方法であって、
シリコン基板を準備する工程と、
該シリコン基板上にエピタキシャルSi1−xGex層を成長させる工程と、
該エピタキシャルSi1−xGex層上に薄いエピタキシャル上部シリコン層を成長させる工程と、
該上部シリコンおよびSi1−xGexを該シリコン基板内部までトレンチエッチングして、第1のトレンチを形成する工程と、
エアーギャップを形成するようにほとんどのSi1−xGexを除去するために、該Si1−xGex層を選択的にエッチングする工程と、
CVDによってSiO2の層を堆積して、該第1のトレンチを充填する工程と、
トレンチエッチングして、第2のトレンチを形成する工程と、
該Si1−xGex層の残りを選択的にエッチングする工程と、
CVDによってSiO2の第2の層を堆積して、第2のトレンチを充填する工程であって、ソース、ドレインおよびチャネルを該基板から切り離す、工程と、
現在の技術レベルのCMOS製造技術によって構造を完成させる工程と
を包含する、方法。 - Si1−xGexの厚さは、緩和が起きず、前記Si1−xGex層において欠陥が形成されないようにSi1−xGexの限界の厚さよりも薄く、約3〜50nmの間の厚さである、請求項1に記載の方法。
- 前記エッチングの時間は、前記上部シリコン層のはがれを防止するため、前記構造の少なくとも一部のSiGeが残るように前記第1のエッチング工程の間制御される、請求項1に記載の方法。
- 前記シリコン基板上にエピタキシャルSi1−xGex層を成長させる工程は、約10%〜80%の間のGe含有量を有するSi1−xGex層を成長させる工程を含む、請求項1に記載の方法。
- 前記エピタキシャルSi1−xGex層上に薄いエピタキシャル上部シリコン層を成長させる工程は、約3nm〜100nmの間の厚さを有するシリコン層を成長させる工程を含む、請求項1に記載の方法。
- Si1−xGex層の選択的エッチングを用いるシリコンオンナッシング(SON)MOSFETの製造方法であって、
シリコン基板を準備する工程と、
該シリコン基板上にエピタキシャルSi1−xGex層を成長させる工程であって、Si1−xGexの厚さが、緩和が起きず、該Si1−xGex層において欠陥が形成されないようにSi1−xGexの限界の厚さよりも薄い、工程と、
該エピタキシャルSi1−xGex層上に薄いエピタキシャル上部シリコン層を成長させる工程と、
該上部シリコンおよびSi1−xGexを該シリコン基板内部までトレンチエッチングして、第1のトレンチを形成する工程と、
エアーギャップを形成するようにほとんどのSi1−xGexを除去するために、該Si1−xGex層を選択的にエッチングする工程と、
CVDによってSiO2の層を堆積して、該第1のトレンチを充填する工程と、
トレンチエッチングして、第2のトレンチを形成する工程と、
該Si1−xGex層の残りを選択的にエッチングする工程と、
CVDによってSiO2の第2の層を堆積して、該第2のトレンチを充填する工程であって、ソース、ドレインおよびチャネルを該基板から切り離す、工程と、
公知のCMOS製造技術によって構造を完成させる工程と
を包含する、方法。 - 前記エッチングの時間が、前記上部シリコン層のはがれを防止するため、前記構造の少なくとも一部のSiGeが残るように前記第1のエッチング工程の間制御される、請求項6に記載の方法。
- 前記シリコン基板上にエピタキシャルSi1−xGex層を成長させる工程は、約10%〜80%の間のGe含有量を有するSi1−xGex層を成長させる工程を含む、請求項6に記載の方法。
- 前記エピタキシャルSi1−xGex層上に薄いエピタキシャル上部シリコン層を成長させる工程は、約3nm〜100nmの間の厚さを有するシリコン層を成長させる工程を含む、請求項6に記載の方法。
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FR2791178B1 (fr) * | 1999-03-19 | 2001-11-16 | France Telecom | NOUVEAU DISPOSITIF SEMI-CONDUCTEUR COMBINANT LES AVANTAGES DES ARCHITECTURES MASSIVE ET soi, ET PROCEDE DE FABRICATION |
FR2795555B1 (fr) * | 1999-06-28 | 2002-12-13 | France Telecom | Procede de fabrication d'un dispositif semi-conducteur comprenant un empilement forme alternativement de couches de silicium et de couches de materiau dielectrique |
FR2799307B1 (fr) * | 1999-10-01 | 2002-02-15 | France Telecom | Dispositif semi-conducteur combinant les avantages des architectures massives et soi, procede de fabrication |
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-
2003
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Cited By (4)
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JP2007035908A (ja) * | 2005-07-27 | 2007-02-08 | Seiko Epson Corp | 半導体基板の製造方法及び、半導体装置の製造方法 |
JP2007059804A (ja) * | 2005-08-26 | 2007-03-08 | Seiko Epson Corp | 半導体装置の製造方法 |
US8114755B2 (en) | 2007-06-26 | 2012-02-14 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
JP2011158511A (ja) * | 2010-01-29 | 2011-08-18 | Kyocera Kinseki Corp | 光学デバイス |
Also Published As
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JP4428520B2 (ja) | 2010-03-10 |
US7015147B2 (en) | 2006-03-21 |
US20050020085A1 (en) | 2005-01-27 |
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