WO2008087576A1

WO2008087576A1 - Semiconductor substrate processing

Info

Publication number: WO2008087576A1
Application number: PCT/IB2008/050112
Authority: WO
Inventors: Gilberto Curatola
Original assignee: Nxp B.V.
Priority date: 2007-01-16
Filing date: 2008-01-14
Publication date: 2008-07-24

Abstract

A semiconductor processing method comprising the sequential steps of: i) providing a semiconductor substrate; ii) forming a first layer of a semiconductor material on a surface of the substrate; iii) forming a second layer of a semiconductor material on a surface of the first layer; iv) selectively removing by etching at least a portion of the first layer; and v) forming a dielectric layer between the second layer and the semiconductor substrate in place of the removed portion of the first layer.

Description

DESCRIPTION

SEMICONDUCTOR SUBSTRATE PROCESSING

The invention relates to semiconductor processing, and in particular to fabrication methods for the formation of semiconductor-on-insulator (SOI) substrates for devices fabricated thereon.

Scaling of conventional planar field-effect transistor technology, e.g. commonly referred to as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or more generally as IGFET (Insulated Gate Field Effect Transistor) technology, is increasingly difficult as feature sizes are reduced. This is particularly the case where feature sizes are reduced below around 45nm, where short channel effects begin to seriously deteriorate transistor performance.

In the effort of pursuing future targets, for example those suggested by the International Technology Roadmap for semiconductors (www.itrs.net), new materials such as high-k (high permittivity) dielectrics and metal gate electrodes are proposed to overcome issues related to scaling. Furthermore, different device architectures such as partially- and fully-depleted silicon-on-insulator substrates and multiple gate fin-FETS are being studied and developed.

The use of an insulating substrate has the advantage of providing an increased immunity to short channel effects for conventional bulk MOSFETs.

One known method of fabricating SOI substrates is that of the Separation by IMplantation of OXygen (SIMOX) process, currently an industry standard way of fabricating a silicon layer on top of an insulated substrate. This process involves deep oxygen ion implantation on a silicon substrate, which creates a subsurface silicon oxide layer. This oxide layer insulates the top surface layer of silicon, on or in which transistors are then formed, from the underlying silicon substrate.

It is an object of the invention to provide an alternative to the currently used SIMOX process. The invention provides a semiconductor processing method comprising the sequential steps of: i) providing a semiconductor substrate; ii) forming a first layer of a semiconductor material on a surface of the substrate; iii) forming a second layer of a semiconductor material on a surface of the first layer; iv) selectively removing by etching at least a portion of the first layer; and v) forming a dielectric layer between the second layer and the semiconductor substrate in place of the removed portion of the first layer.

The invention will be described by way of example and with reference to the accompanying drawings, in which: figure 1 shows a schematic cross-sectional view of a multi-layered substrate; figure 1 a shows a schematic plan view of a portion of a multi- layered substrate; figure 1 b shows a schematic cross-sectional view of the portion of a multi-layered substrate of figure 1 a; figure 2 shows a schematic cross-sectional view of the multi-layered substrate of figure 1 after an etching processing step; figure 3 shows a schematic cross-sectional view of the multi-layered substrate of figure 2 after an oxidation processing step; figure 4 shows a schematic cross-sectional view of the substrate of figure 3 after a further etching processing step; figure 5 shows a schematic cross-sectional view of the substrate of figure 4 after deposition of an insulating layer and a gate electrode layer; figure 6 shows a schematic cross-sectional view of a doped contact passing through to a layer within a multi-layer substrate; figure 7 shows a schematic cross-sectional view of an SOI transistor on a multi-layered substrate; and figure 8 illustrates simulated data showing drain-source current as a function of gate-source voltage for various silicon-on-insulator devices. Throughout the present specification, unless required otherwise by the context, the expression 'substrate' is used to refer not only to the original (e.g. silicon wafer) substrate, but also to include any subsequently deposited and / or defined layers up to the relevant point in the process being described.

Starting from a conventional silicon semiconductor substrate, a stack is built up consisting of four layers, each layer formed on the preceding layer by epitaxial growth. Figure 1 illustrates the different layers forming the stack structure. A SiGe (silicon germanium) layer 12 is formed on the silicon substrate 1 1 , followed by a highly n+ doped silicon layer 13 and a further SiGe layer 14. Finally, a Si top layer 15 is formed.

Due to the larger lattice constant of germanium with respect to silicon, the thickness of the SiGe layers as well as the molar fraction of Ge in the layers should preferably be maintained below suitable levels to maintain epitaxial growth of the layers and preferably to keep internal stresses low. Preferably the mole fraction of Ge in the SiGe layers is no greater than around 0.3, i.e. with a stoichiometry of Si_xGei-_x the value of x is kept no smaller than 0.7. More preferably, the value of x is kept no smaller than 0.8.

The thickness for the SiGe layer is limited by the possible strain relaxation and consequent formation of defects if the layer thickness exceeds a maximum tolerable value. This value is dependent mainly on the Ge content in the layer and also on the thermal budget. For a commonly used germanium mole fraction (i.e. where x > 0.7) a reasonable thickness of the SiGe layer is around 10-15nm.

A portion of an exemplary substrate after the above process is shown in plan view in figure 1 a. One or more trenches 16 are formed in the substrate to allow access to the sides of the SiGe layers. In the embodiment illustrated, trenches 16 are formed on either side of an area 17 within which a device is to be formed. The trenches may be formed by conventional masking and etching processes. A cross-section through the portion of the substrate is shown in figure 1 b. The trenches 16 extend through all four layers 12, 13, 14, 15 to expose the edges of the layers to allow for further processing. Following the above process, a selective etch step is carried out. This selective etch process removes the sacrificial SiGe layers 12, 14 by lateral etching in preference to the surrounding silicon 1 1 , 15 and doped silicon layer 13. The selective etch process is preferably a dry etch. The trenches 16 allow the etchant access to the SiGe layers 12, 14. The remaining layers 13, 15 are held in place by the surrounding material.

It is to be understood that SiGe is illustrated as a particular example of a material that is known to be suitable for both epitaxial growth on silicon and for selective etching so that the SiGe can be removed and replaced in preference to silicon. Other materials, however, may be suitable, whether in combination with silicon or other semiconductor materials.

SiGe is a preferred material for the sacrificial layers 12, 14 for several reasons, including: 1 ) SiGe is already used in standard CMOS processing for ultra-scaled technology node (i.e. 45nm and smaller); 2) the lattice mismatch between Si and Ge is only 4%, which avoids defects and dislocations forming in relatively thick strained layers; and 3) the etch selectivity of Ge with respect to Si is usefully high. The use of other sacrifical material, such as nitrides, may however also be feasible with suitable selective etchants.

Semiconductor materials other than silicon may alternatively be used, with one or more suitable sacrificial layer materials chosen for comparable etch selectivity.

Following the selective etch process, the layered structure shown in figure 2 is created, with the original SiGe layers having been removed leaving gaps 22, 24. The silicon layers 13, 15 are maintained in position relative to the substrate 1 1 by material either side of the device area 17 (figure 1 a). The lateral extent of etch may be as far as necessary to provide a suitable size of device area and sufficient to provide adequate isolation of the layers of the device area.

After an oxidation process, the structure shown in figure 3 is formed, where oxide layers 32, 34 are created in place of the original SiGe layers. These oxide layers may be formed by oxidising the exposed silicon surfaces in the gaps 22, 24, for example by rapid thermal oxidation (RTO). Alternative methods of forming dielectric layers 32, 34 may be used. Such alternative methods may include, for example, chemical vapour deposition (CVD) of an oxide or a nitride material. The dielectric layers may be formed using tetraethoxysilane (TEOS), silicon nitride or a combination of silicon dioxide and silicon nitride.

Devices can then be fabricated on the substrate in the device area 17 formed as a result of the above process. Such devices may, for example, be planar SOI devices or multi-gate fin-FETs.

Figures 4 and 5 illustrate exemplary process stages in the formation of a fin-FET following substrate processing according to the above. The top silicon layer 15 (figure 3) is patterned and etched, e.g. by standard photolithographic techniques, to produce a fin 45. The oxide layer 34 may be used as a stop layer for the etching process to produce the fin 45.

A further oxide layer 51 is formed over the fin 45 to form the insulating gate layer of the fin-FET. A metal or polysilicon layer 52 is then formed over the oxide layer 51 to form the gate electrode of the fin-FET. The source and drain electrodes and associated doped regions are formed using conventional techniques.

As is conventional in bipolar technology, to contact a buried collector layer a further processing step may be included to contact the n+ doped silicon layer 13 between the oxide layers 32, 34. Such a structure is schematically illustrated in figure 6. This figure shows a cross-section taken orthogonally to the one shown in figure 5. A highly n+ doped contact 61 is formed, extending through the silicon layer 15, the oxide layer 34, and extending into the n+ doped silicon layer 13. This contact 61 may for example be formed by masking, etching and ion implantation. An etching step may be performed to provide the contact definition, i.e. a small channel provided through the silicon and oxide layers 34, followed by deposition of a highly doped n+ silicon or polysilicon material in the channel.

Providing this additional contact 61 allows for electronic tuning of transistor performance, for example by altering the threshold voltage, by means of altering a voltage applied to the control electrode 62. This facility allows for a 'back-bias' contact not possible through existing SOI technology. The back-bias contact may be separate for each device on the substrate.

An alternative SOI device is shown in schematic cross-section in figure 7. The top silicon layer 15 of the multi-layer substrate is used as the base for an IGFET type transistor structure. The process follows the conventional steps of patterning of gate 71 and electrode 73, spacer 72 formation and source and drain implantation (the doping regions for which are indicated by boundary lines 74).

The highly doped silicon layer 13 in conjunction with the two oxide layers 32, 34, allows for a reduction in short channel effects in devices formed on the multi-layer substrate structure. Shown in figure 8 is a comparison of simulated characteristics of three different device architectures: i) a conventional SOI device with a 150nm buried oxide layer (square symbols); ii) a conventional SOI device with a 5 nm buried oxide layer (circle symbols); and iii) a SOI device as described herein with a multi-layer substrate having an oxide layer thicknesses of 5nm and a doped silicon interlayer of 10nm (star symbols).

Each of the sets of data are shown in terms of drain-source current ID_S as a function of gate-source voltage V_Gs- The oxide thickness, channel thickness, body thickness and doping in the silicon body are the same for the three different considered structures. In each case, the two curves shown illustrate the effect of increasing the source-drain voltage VDS from 50 mV (lower curves) to 1 V.

As is clearly shown from the results in figure 8, short channel effects are significantly reduced by using a substrate structure according to the invention.

It is expected that self-heating, which is a major concern in the case of standard SOI technology, will be reduced by the invention due to the very thin oxide layer beneath the silicon body allowing better dispersion of heat in the transistor. Other embodiments are intended to be within the scope of the invention, as defined by the appended claims.

Claims

1 . A semiconductor processing method comprising the sequential steps of: i) providing a semiconductor substrate; ii) forming a first layer of a semiconductor material on a surface of the substrate; iii) forming a second layer of a semiconductor material on a surface of the first layer; iv) selectively removing by etching at least a portion of the first layer; and v) forming a dielectric layer between the second layer and the semiconductor substrate in place of the removed portion of the first layer.

2. The method of claim 1 wherein step v) comprises oxidising the resulting exposed surface of the semiconductor substrate and the resulting exposed surface of the second layer.

3. The method of claim 1 wherein step v) comprises depositing the dielectric layer in the gap between the substrate and the second layer of semiconductor material.

4. The method of claim 3 wherein the dielectric layer comprises an oxide.

5. The method of claim 3 or claim 4 wherein the dielectric layer comprises a nitride.

6. The method of any of claims 3 to 5 wherein step v) comprises a chemical vapour deposition process.

7. The method of claim 1 further including, after step iii) and before step iv): iiia) forming a third layer of a semiconductor material on the second layer; and iiib) forming a fourth layer of a semiconductor material on a surface of the third layer, wherein step iv) comprises removal of the first and third layers and step v) comprises forming a first and a second dielectric layer in place of the first and third semiconductor layers respectively.

8. The method of claim 7 wherein step v) comprises oxidising the resulting exposed surfaces of the semiconductor substrate, the second layer and the fourth layer to form the first and second dielectric layers in place of the first and third semiconductor layers.

9. The method of claim 7 wherein step v) comprises depositing the first dielectric layers in the gap between the substrate and the second layer, and depositing the second dielectric layer between the second layer and the fourth layer.

10. The method of claim 9 wherein the first and second dielectric layers comprise an oxide material.

1 1 . The method of claim 9 or claim 10 wherein the first and second dielectric layers comprise a nitride material.

12. The method of claim 9 wherein step v) comprises a chemical vapour deposition process.

13. The method of claim 1 wherein the first and second layers are formed by epitaxial growth.

14. The method of claim 7 wherein the first, second, third and fourth layers are formed by epitaxial growth.

15. The method of claim 1 or claim 7 wherein both the semiconductor substrate and the second layer are composed of silicon.

16. The method of claim 1 wherein the first layer is composed of silicon and germanium.

17. The method of claim 7 wherein the third and fifth layers are both composed of silicon and germanium.

18. The method of claim 16 wherein the molar fraction of germanium in the third and fifth layers is not greater than around 0.2.

19. The method of claim 7 wherein the second layer is composed of doped silicon.