CN102222693B - FinFET device and manufacturing method thereof - Google Patents
FinFET device and manufacturing method thereof Download PDFInfo
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- CN102222693B CN102222693B CN201010150059.0A CN201010150059A CN102222693B CN 102222693 B CN102222693 B CN 102222693B CN 201010150059 A CN201010150059 A CN 201010150059A CN 102222693 B CN102222693 B CN 102222693B
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- work function
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- tuning layer
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Abstract
The invention provides a FinFET (FinField-effecttransistor) device which comprises a substrate, a fin structure arranged on the substrate and a work function adjustment layer which covers the substrate and the lower part of the fin structure. The invention also provides a manufacturing method of FinFET device. The method comprises the following steps: providing a substrate; forming a fin structure on the substrate; covering the substrate and the lower part of the fin structure to form a work function adjustment layer. According to the invention, the use of high density trap doping is avoided, through the work function adjustment layer which can adjusts the work function formed in the lower part of the fin structure of the FinFET, high junction leakage and high junction capacitance of the lower part of a channel in the fin are inhibited.
Description
Technical field
The present invention relates generally to semiconductor device art.More specifically, a kind of FinFET and the manufacture method thereof that regulate surface work function and reduce the leakage current in bottom channel is related to.
Background technology
Double grids MOSFET is the MOSFET that a device comprises two grid.These devices are called FinFET, because their structure comprises the thin fin extended from substrate.Traditional MOSFET technology can be used successfully to manufacture silica-based FinFET.General FinFET manufactures on substrate, has the insulating barrier in substrate, and this insulating barrier has the thin fin extended from substrate, such as, etches in the silicon layer of substrate.The raceway groove of FET is formed in this vertical fins.On fin, (or parcel fin) has grid.The benefit of double grid is all have grid in the both sides of raceway groove, obtains the grid that can control raceway groove from both sides.The other benefit of FinFET include reducing the electric current of short-channel effect and Geng Gao.Other FinFET structure can comprise three or more effective grid.
In existing FinFET manufacturing process, the people such as such as T.S.Park in Solid-StateElectronics 49 (2005) 377-383 by name " Body-tied triple-gate NMOSFETfabrication using bulk Si wafer " paper in and the people such as K.Okano disclose in " Process Integration Technology and Device Characteristics of CMOSFinFET on Bulk Silicon Substrate with sub-10nm Fin Width and 20nm GateLenth " by name in IEEE 2005, as Fig. 1, Fig. 2 be shown in traditional FinFET technique, due to the doping of very high trap, (N-shaped doping is used for PMOS, p-type doping is used for NMOS), therefore grid structure can not control work function and the leakage current of raceway groove bottom, therefore very high junction leakage and high junction capacitance can be caused, thus affect device performance.
Therefore, need a kind ofly to avoid using the doping of the trap of high concentration thus the FinFET avoiding high junction leakage and high junction capacitance to occur and manufacture method thereof.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention proposes a kind of FinFET, comprising: substrate; Fin structure is over the substrate set; And cover the work function tuning layer of described substrate and fin structure bottom.Described work function tuning layer can be individual layer or multilayer, and when described work function tuning layer is individual layer, for nmos device, described work function tuning layer comprises P type workfunction material; For PMOS device, described work function tuning layer comprises N-type workfunction material.Described P type workfunction material employing work function is that the material between 4.9-5.8 electronvolt is formed, and such as, comprising: Al
2o
3.Described N-type workfunction material employing work function is that the material between 3.9-4.3 electronvolt is formed, and such as, comprising: LaO, La
2o
3, SrO or its combination.When described work function tuning layer is multilayer, for nmos device, described work function tuning layer can comprise insulating barrier and P type workfunction material; For PMOS device, described work function tuning layer can comprise insulating barrier and N-type workfunction material.Such as, described P type workfunction material comprises: Al
2o
3; Described N-type workfunction material comprises: LaO, La
2o
3, SrO or its combination, or La, Sr or its combination etc.
In addition, present invention also offers a kind of method forming manufacture FinFET, comprise the steps: to provide substrate; Form fin structure over the substrate; Work function tuning layer is formed at the bottom covering described substrate and fin structure.
Owing to avoiding the trap doping using high concentration, being formed by the sidewall of the bottom of the fin structure at FinFET can the work function regulating course of regulatory work function, and the high junction leakage of the bottom of the raceway groove in fin and high junction capacitance can be made to be inhibited.
Accompanying drawing explanation
Fig. 1 shows each fabrication stage structure chart of FinFET of the prior art;
Fig. 2 shows the structure chart of another FinFET of the prior art and the relation between leakage current density and thickness thereof.
Fig. 3 shows the flow chart of each fabrication stage according to FinFET of the present invention;
Fig. 4-12 shows the flow chart of each fabrication stage according to FinFET of the present invention.
Embodiment
Relate generally to semiconductor device of the present invention, relates more specifically to the method for FinFET element and manufacture FinFET (such as, the part of device or device).But be understandable that, the invention provides specific embodiment as an example to instruct wider inventive concept, instruction of the present invention easily can be applied to additive method or equipment by those skilled in the art.In addition, be understandable that, the method and apparatus discussed in the present invention comprises some traditional structure and/or techniques.Because these Structure and energy are known in the field, so only discuss in the details of general rank.In addition, conveniently with the object of example, reuse reference symbol in the accompanying drawings, such repeats any required combination not indicating the feature in accompanying drawing or step.In addition, in following description fisrt feature on second feature or above structure can comprise the embodiment that the first and second features directly contact, also can comprise additional feature and be formed in embodiment between the first and second features, such first and second features may not be direct contacts.The term FinFET adopted in the present invention, comprises any fin base, multiple-gate transistor.FinFET element can comprise FinFET (as transistor) or its any part (as fin).
Fig. 3 shows the flow chart of the formation method of the FinFET according to the first embodiment of the present invention.
The method starts from step S101, which provides substrate 202.With reference to figure 4, in one embodiment, substrate comprises silicon substrate (as wafer).Substrate can be the silicon of crystal structure.In other examples, substrate can comprise the semiconductor of other elements as germanium, or comprises compound semiconductor as carborundum, GaAs, indium arsenide and indium phosphide.In one embodiment, substrate comprises silicon-on-insulator (SOI) substrate.SOI substrate can use note oxygen separating (SIMOX), bonding chip and/or other method manufactures be applicable to.
In step S102, form fin 204 on the substrate 202.In one embodiment, fin is silicon fin (Si fin).Fin is passable, such as, is formed by etching silicon layer on substrate.Silicon layer can be the silicon layer (as on insulating barrier) of SOI substrate.With reference to the example of figure 5, in one embodiment, can have one or more fin 204, described fin 204 comprises silicon.Multiple fin 204 can pass through composition silicon layer (such as, the upper strata silicon layer of the silicon-on-insulator-silicon lamination of SOI substrate) and manufacture.Fin 204 can comprise the cap layers be arranged on fin.In one embodiment, cap layers can be silicon nitride, silica, silicon oxynitride or its combination, and/or other suitable materials.
Applicable technique can be used to comprise photoetching for fin 204 and etching technics manufactures.Photoetching process can be included in substrate formed photoresist oxidant layer (resist) (as, on silicon layer), exposure resist, on composition, carries out post exposure bake technique, and development resist is to form the masking element comprising resist.Then masking element may be used for fin 204 to etch in silicon layer.Fin 204 can use reactive ion etching (RIE) and/or other technique etchings be applicable to.
In step S103, work function tuning layer 206 is formed at the bottom covering described substrate 202 and fin 204.For nmos device, P type work function material is adopted to form work function tuning layer 206; For PMOS device, adopt N-type work function material.Work function tuning layer 206 can be individual layer or sandwich construction.When described work function tuning layer is individual layer, insulating material is adopted to form work function tuning layer 206.Specifically, when described work function tuning layer is individual layer, for nmos device, described work function tuning layer is the material with high work function, such as work function close to or be greater than the valence band edge of silicon, as, be greater than 4.9 electronvolt, be preferably between 4.9-5.8 electronvolt, it can be but be not limited to the compound of aluminium, such as Al
2o
3.For PMOS device, described work function tuning layer is the material with low work function, such as work function is near or below the conduction band edge of silicon, as, be less than 4.3 electronvolt, be preferably between 3.9-4.3 electronvolt, it can be but be not limited to the combination of the oxide of rare earth material or the oxide of rare earth material and rare earth material, such as, can be but be not limited to LaO, La
2o
3, the material such as SrO.When described work function tuning layer is multilayer, for nmos device, described work function tuning layer can comprise insulating barrier and P type workfunction material, and wherein, described P type workfunction material is such as Al
2o
3; For PMOS device, described work function tuning layer can comprise insulating barrier and N-type workfunction material, and wherein, described N-type work function material is such as LaO, La
2o
3, SrO or its combination.In addition, when work function tuning layer is multilayer, due to the existence of insulating barrier, workfunction material can be not only insulating material, also can be conductor or semi-conducting material, or their combination in any.Such as, for PMOS device, at this moment described work function tuning layer also can be rare earth material, such as, can be but be not limited to La, Sr or its combination.
Then procedure of processing as required can form nitride layer 208 on device, and insulating barrier 210, and form grid structure further, comprise gate dielectric layer 212 and gate electrode 214.
Above-described each layer by being formed in different processing steps, also can be formed by a processing technology.Such as, first can cover described substrate 202 and fin 204 forms work function tuning layer 206, as shown in Figure 6, can utilize as photoetching composition, oxidation, deposition, etching and/or other technique be applicable to are formed.Then cover described work function tuning layer 206 and form nitride layer 208, on described nitride layer, form insulating barrier 210 afterwards, such as SiO
2, as shown in Figure 7.Carry out chemico-mechanical polishing, to expose the nitride layer 208 on fin 204.Then etch, to remove the nitride layer on it, and stop on work function regulating course 206, as shown in Figure 8.After this, by photoetching and etching technics, the insulating barrier of the lateral wall circumference on fin 204 top and nitride layer are removed, optionally, using workfunction layers as etching stop layer, thus expose the workfunction layers of the sidewall on fin 204 top, as shown in Figure 9.And then the workfunction layers of the sidewall on etching fin 204 top, thus expose described fin structure, as shown in Figure 10.
By can form the work function tuning layer 206 of the bottom covering described substrate 202 and fin 204 in a processing technology with upper type.
After this can be for further processing, such as on the sidewall on the top of described fin 204, form grid structure, such as gate dielectric layer 212 and gate electrode 214, as shown in Figure 11,12.And form source area and drain region (not shown) further, thus complete the manufacture of described FinFET.Grid structure also can have other layer multiple, such as, and cap layers, boundary layer and/or other structures be applicable to.Gate dielectric layer 212 can comprise dielectric substance as the dielectric of silica, silicon nitride, silicon oxynitride, high-k (high-k) and/or its combination.The example of high-k material comprises hafnium silicate, hafnium oxide, zirconia, aluminium oxide, hafnium oxide-aluminium (HfO
2-Al
2o
3) alloy and/or its combination.Gate dielectric layer 212 can use as photoetching composition, oxidation, deposition, etching and/or other technique be applicable to are formed.Gate electrode 214 can comprise polysilicon, SiGe, metal, comprises metallic compound as Mo, Cu, W, Ti, Ta, TiN, TiAlN, TaN, NiSi, CoSi and/or the electric conducting material that other are applicable to known in the art.Form gate electrode 214 can use as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma reinforced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), high-density plasma CVD (HD CVD), atomic layer CVD (ALCVD) technique and/or other techniques be applicable to that such as photoetching and/or etching technics can be followed.
In addition, according to embodiments of the invention, additionally provide a kind of FinFET, this device comprises substrate 202; Fin structure 204 is over the substrate set; And cover the work function tuning layer 206 of described substrate and fin structure bottom.Especially, described work function tuning layer can be single or multiple lift.When described work function tuning layer is individual layer, for nmos device, described work function tuning layer comprises P type workfunction material; For PMOS device, described work function tuning layer comprises N-type workfunction material.Described P type workfunction material employing work function is that the material between 4.9-5.8 electronvolt is formed, and such as, comprising: Al
2o
3.Described N-type workfunction material employing work function is that the material between 3.9-4.3 electronvolt is formed, and such as, comprising: LaO, La
2o
3, SrO or its combination.When described work function tuning layer is multilayer, for nmos device, described work function tuning layer comprises insulating barrier and P type workfunction material; For PMOS device, described work function tuning layer comprises insulating barrier and N-type workfunction material.Described P type workfunction material comprises: Al
2o
3; Described N-type workfunction material comprises: LaO, La
2o
3, SrO or its combination.Because work function tuning layer includes insulating barrier, therefore described N-type workfunction material and described P type workfunction material can be one in insulation, conductor and semi-conducting material or its combination.Such as, for PMOS device, at this moment described work function tuning layer also can be rare earth material, such as, can be but be not limited to La, Sr or its combination.
Owing to avoiding the trap doping using high concentration, form the work function regulating course that can regulate surface work function by the sidewall of the bottom of the fin structure at FinFET, the high junction leakage of the bottom of the raceway groove in fin and high junction capacitance can be made to be inhibited.
Above by reference to the accompanying drawings according to embodiments of the invention.Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection range of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other examples, those of ordinary skill in the art should easy understand maintenance scope in while, the order of processing step can change.
In addition, range of application of the present invention is not limited to the technique of the specific embodiment described in specification, mechanism, manufacture, material composition, means, method and step.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique existed at present or be about to develop, mechanism, manufacture, material composition, means, method or step later, wherein their perform the identical function of the corresponding embodiment cardinal principle that describes with the present invention or obtain the identical result of cardinal principle, can apply according to the present invention to them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.
Claims (15)
1. a FinFET, comprising:
Substrate;
Fin structure is over the substrate set; And
Only cover the work function tuning layer of described substrate and fin structure bottom, described work function tuning layer is single or multiple lift;
Only cover the grid structure on described fin structure top, described grid structure comprises gate dielectric layer and gate electrode;
Wherein, described device is PMOS device; When described work function tuning layer is individual layer, described work function tuning layer comprises N-type workfunction material; When described work function tuning layer is multilayer, described work function tuning layer comprises insulating barrier and N-type workfunction material.
2. device according to claim 1, when described work function tuning layer is individual layer, described N-type workfunction material employing work function is that the material between 3.9-4.3 electronvolt is formed.
3. device according to claim 2, wherein said N-type workfunction material comprises: LaO, La
2o
3, SrO or its combination.
4. device according to claim 1, when described work function tuning layer is multilayer, described N-type workfunction material can be one in insulation, conductor and semi-conducting material or its combination.
5. device according to claim 4, wherein said N-type workfunction material comprises: LaO, La
2o
3, SrO, La, Sr or its combination.
6. device according to claim 1, also comprises:
Nitride layer, described nitride layer is in described work function tuning layer and cover the work function tuning layer sidewall of described fin structure bottom.
7. device according to claim 6, also comprises: cover described nitride layer and the insulating barrier do not contacted with described fin structure.
8. device according to claim 7, also comprises: the grid structure on described fin structure.
9. form the method manufacturing FinFET, comprise the steps:
Substrate is provided;
Form fin structure over the substrate;
Cover described substrate and described fin structure formation work function tuning layer;
Remove the work function tuning layer on the top of described fin structure, thus expose described fin structure;
Described work function tuning layer is single or multiple lift;
Only cover the described fin structure come out and form grid structure, described grid structure comprises gate dielectric layer and gate electrode;
Wherein, described device is PMOS device; When described work function tuning layer is individual layer, described work function tuning layer comprises N-type workfunction material; When described work function tuning layer is multilayer, described work function tuning layer comprises insulating barrier and N-type workfunction material.
10. method according to claim 9, when described work function tuning layer is individual layer, described N-type workfunction material employing work function is that the material between 3.9-4.3 electronvolt is formed.
11. methods according to claim 10, wherein said N-type workfunction material comprises: LaO, La
2o
3, SrO or its combination.
12. methods according to claim 9, when described work function tuning layer is multilayer, described N-type workfunction material can be one in insulation, conductor and semi-conducting material or its combination.
13. methods according to claim 12, wherein said N-type workfunction material comprises: LaO, La
2o
3, SrO, La, Sr or its combination.
14. methods according to claim 9, also comprise: in described work function tuning layer and cover described fin structure bottom work function tuning layer sidewall formed nitride layer.
15. methods according to claim 14, also comprise: cover described nitride layer and form the insulating barrier do not contacted with described fin structure.
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| CN201010150059.0A CN102222693B (en) | 2010-04-15 | 2010-04-15 | FinFET device and manufacturing method thereof |
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| CN102222693B true CN102222693B (en) | 2015-03-25 |
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| CN103681507B (en) * | 2012-09-20 | 2017-02-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| US9064857B2 (en) * | 2012-12-19 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | N metal for FinFET |
| CN103413758B (en) | 2013-07-17 | 2017-02-08 | 华为技术有限公司 | Manufacturing method for semiconductor fin ray and manufacturing method for FinFET device |
| US9252014B2 (en) | 2013-09-04 | 2016-02-02 | Globalfoundries Inc. | Trench sidewall protection for selective epitaxial semiconductor material formation |
| CN108807535B (en) * | 2017-05-05 | 2021-07-13 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1655365A (en) * | 2004-02-10 | 2005-08-17 | 三星电子株式会社 | Fin FET structure |
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| US8124483B2 (en) * | 2007-06-07 | 2012-02-28 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
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| CN1655365A (en) * | 2004-02-10 | 2005-08-17 | 三星电子株式会社 | Fin FET structure |
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