CN114899143A - FDSOI source-drain epitaxial growth method - Google Patents

FDSOI source-drain epitaxial growth method Download PDF

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Publication number
CN114899143A
CN114899143A CN202210394301.1A CN202210394301A CN114899143A CN 114899143 A CN114899143 A CN 114899143A CN 202210394301 A CN202210394301 A CN 202210394301A CN 114899143 A CN114899143 A CN 114899143A
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China
Prior art keywords
silicon
fdsoi
layer
source
epitaxial growth
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CN202210394301.1A
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Chinese (zh)
Inventor
岳双强
汪韬
李妍
辻直树
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202210394301.1A priority Critical patent/CN114899143A/en
Publication of CN114899143A publication Critical patent/CN114899143A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands

Abstract

The invention discloses an FDSOI source-drain epitaxial growth method, which comprises the following steps: manufacturing FDSOI according to the prior art until a first layer of isolation side wall is deposited; etching to remove the first isolation side walls on the top of the insulating silicon and the top of the grid, and reserving the first isolation side walls on two sides of the grid; growing a silicon epitaxy on the top of the insulator silicon, and opening a trench window; epitaxially growing a first material in the NMOS source drain region; the second material of the PMOS source drain region grows in an epitaxial mode, and the thickness of the residual germanium-silicon layer after cleaning before the growth of the germanium-silicon is larger than the minimum value of the thickness required by the epitaxial growth of the PMOS source drain; and etching to remove the epitaxial silicon beside the bottom of the first layer of isolation side wall.

Description

FDSOI source-drain epitaxial growth method
Technical Field
The invention relates to the field of semiconductors, in particular to an active drain epitaxial growth method of a Semiconductor On Insulator (SOI).
Background
A field effect transistor is a voltage control type semiconductor device, and mainly includes a planar field effect transistor (MOSFET), a fin field effect transistor (FinFET, released 1999), and an SOI-based ultra-thin silicon-on-insulator transistor (FDSOI, released 2000). With the continuous rapid development of integrated circuits, the critical dimensions of devices in the circuits are continuously reduced, the film thicknesses of corresponding component elements are also continuously reduced, and Fully Depleted Silicon On Insulator (FDSOI) becomes an option for overcoming short channel effects.
In the FDSOI technology, a substrate structure comprises a semiconductor main body layer, a medium buried layer and a semiconductor top layer, wherein the medium buried layer is formed on the surface of the semiconductor main body layer, and the semiconductor top layer is formed on the surface of the medium buried layer; usually, Si is used as the material of the semiconductor body layer and the semiconductor top layer. The semiconductor top layer is generally called as an SOI layer and has an ultrathin structure, a semiconductor device is formed by utilizing the ultrathin semiconductor top layer to obtain an ultrathin transistor, a channel region formed by the semiconductor top layer at the bottom of a grid structure of the ultrathin transistor is completely exhausted when the device works, a floating body effect can be eliminated, the short channel effect of the transistor can be well controlled, and the power supply voltage can be reduced.
The gate length of the FDSOI planar transistor can be reduced to below 14 nm, and a large number of early electrical simulation results show that in the structure, in order to reduce the reduction Degree (DIBL) of the transistor drain induced barrier, the thickness of a buried dielectric layer (namely, the BOX thickness) and the thickness of top silicon of the FDSOI substrate need to be reduced at the same time. However, in the current FDSOI device process, due to the ultra-thin channel, the PMOS SiGe substrate is etched away by HM ET before Spacer1 ET and S/D EPI growth, which results in S/D EPI not growing, and subsequent CT penetrates through the BOX, which results in device failure.
Disclosure of Invention
In this summary, a series of simplified form concepts are introduced that are simplifications of the prior art in this field, which will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention aims to provide a method for increasing the substrate thickness required by EPI growth of FDSOI PMOS.
In order to solve the technical problem, the FDSOI source-drain epitaxial growth method provided by the invention comprises the following steps:
s1, manufacturing FDSOI according to the prior art until depositing the first layer of isolation side wall;
s2, etching to remove the first isolation side walls on the top of the insulator silicon and the top of the grid, and reserving the first isolation side walls on two sides of the grid;
s3, growing silicon epitaxy on the top of the insulator silicon, and opening a groove window;
s4, the first material of the NMOS source and drain areas grows epitaxially;
s5, epitaxially growing a second material in the PMOS source drain region, wherein the thickness of the residual germanium-silicon layer after cleaning before the growth of the germanium-silicon is larger than the minimum value of the thickness required by the epitaxial growth of the PMOS source drain;
and S6, etching to remove the epitaxial silicon beside the bottom of the first layer of isolation side wall, and executing subsequent processes by adopting the prior art.
Optionally, the FDSOI source-drain epitaxial growth method is further improved, the first material is silicon or germanium-silicon, and the second material is germanium-silicon.
Optionally, the FDSOI source-drain epitaxial growth method is further improved, and the first layer of isolation side wall is a silicon nitride isolation side wall.
Optionally, the FDSOI source-drain epitaxial growth method is further improved, and when step S4 is implemented, a hard mask layer is deposited to cover the PMOS region, silicon epitaxy is grown, an NMOS source-drain region is formed by an etching process, and the hard mask layer is removed.
Optionally, the FDSOI source-drain epitaxial growth method is further improved, and the hard mask layer is a silicon nitride layer or a silicon oxynitride layer.
Optionally, the FDSOI source-drain epitaxial growth method is further improved, when step S5 is implemented, a hard mask layer is deposited to cover the NMOS region, cleaning is performed, a germanium-silicon epitaxy is grown, a PMOS source-drain region is formed by an etching process, and the hard mask layer is removed.
Optionally, the FDSOI source-drain epitaxial growth method is further improved, and the hard mask layer is a silicon nitride layer or a silicon oxynitride layer.
Optionally, the FDSOI source-drain epitaxial growth method is further improved, and when step S6 is implemented, epitaxial silicon near the bottom of the sidewall is removed by blanket etching within the shortest time that the process can achieve.
Optionally, the FDSOI source-drain epitaxial growth method is further improved and is used for manufacturing processes of FDSOI with the thickness of 45nm, 40nm, 32nm, 28nm, 22nm, 20nm or less than 16 nm.
The main improvement point of the invention is that an EPI growth path is added after the first layer of isolation side wall ET by manufacturing FDSOI in the prior art until the first layer of isolation side wall ET is deposited, so as to ensure that enough substrate is present before the epitaxial S/D EPI growth of the source and drain region, and the epitaxial growth of the source and drain region can be smoothly carried out, thereby preventing the source and drain region open and CT from punching through the BOX. By adopting the technical scheme of the invention, the yield of the FDSOI can be improved and the performance of the device can be ensured under the condition of increasing little cost.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is a first schematic diagram of the present invention.
FIG. 2 is a second schematic diagram of the present invention.
FIG. 3 is a third schematic diagram of the present invention.
FIG. 4 is a fourth schematic diagram of the intermediate structure of the present invention.
FIG. 5 is a fifth schematic diagram of the present invention.
Fig. 6 is a sixth schematic diagram of the present invention.
Description of the reference numerals
1-substrate silicon
2-buried layer silicon oxide
3-silicon germanium on insulator
4-silicon on insulator
5-first layer isolation side wall (silicon nitride)
6-grid stack
Epitaxial silicon on germanium-silicon-on-7-insulator
8-silicon nitride hard mask layer
Epitaxial silicon germanium on 9-silicon germanium on insulator.
Detailed Description
Other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure of the present specification, wherein the following description is given by way of specific embodiments. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
A first embodiment;
the FDSOI source-drain epitaxial growth method provided by the invention comprises the following steps:
s1, manufacturing FDSOI according to the prior art until depositing the first layer of isolation side wall;
s2, etching to remove the first isolation side walls on the top of the insulator silicon and the top of the grid, and reserving the first isolation side walls on two sides of the grid;
s3, growing silicon epitaxy on the top of the insulator silicon, and opening a groove window;
s4, the first material of the NMOS source and drain areas grows epitaxially;
s5, epitaxially growing a second material in the PMOS source drain region, wherein the thickness of the residual germanium-silicon layer after cleaning before the growth of the germanium-silicon is larger than the minimum value of the thickness required by the epitaxial growth of the PMOS source drain;
and S6, etching to remove the epitaxial silicon beside the bottom of the first layer of isolation side wall, and executing subsequent processes by adopting the prior art.
Further, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, parameters, components, regions, layers and/or sections, these elements, parameters, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or section from another element, parameter, component, region, layer or section. Thus, a first element, parameter, component, region, layer or section discussed below could be termed a second element, parameter, component, region, layer or section without departing from the teachings of exemplary embodiments according to the present invention.
A second embodiment;
the FDSOI source-drain epitaxial growth method provided by the invention comprises the following steps:
s1, manufacturing FDSOI according to the prior art until depositing the first layer of isolation side wall;
s2, etching to remove the first isolation side walls on the top of the insulator silicon and the top of the grid, and reserving the first isolation side walls on two sides of the grid;
s3, growing silicon epitaxy on the top of the insulator silicon, and opening a groove window;
s4, growing the NMOS source and drain region silicon or germanium silicon epitaxially;
s5, growing germanium and silicon epitaxy of the PMOS source drain region, wherein the thickness of the germanium and silicon layer left after cleaning before growing the germanium and silicon is larger than the minimum value of the thickness required by the PMOS source drain epitaxy;
and S6, etching to remove the epitaxial silicon beside the bottom of the first layer of isolation side wall, and executing subsequent processes by adopting the prior art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
A third embodiment;
the FDSOI source-drain epitaxial growth method provided by the invention comprises the following steps:
s1, manufacturing FDSOI according to the prior art until depositing the first layer of isolation side wall;
s2, etching to remove the first isolation side walls on the top of the insulator silicon and the top of the grid, and reserving the first isolation side walls on two sides of the grid;
s3, growing silicon epitaxy on the top of the insulator silicon, and opening a groove window;
s4, the NMOS source drain region silicon or germanium silicon epitaxial growth includes: depositing a hard mask layer to cover the PMOS region, growing silicon epitaxy, forming an NMOS source drain region by an etching process, removing the hard mask layer and the like;
s5, growing germanium and silicon epitaxy of the PMOS source drain region, wherein the thickness of the germanium and silicon layer left after cleaning before growing the germanium and silicon is larger than the minimum value of the thickness required by the PMOS source drain epitaxy;
and S6, etching to remove the epitaxial silicon beside the bottom of the first layer of isolation side wall, and executing subsequent processes by adopting the prior art.
Wherein the hard mask layer is a silicon nitride layer or a silicon oxynitride layer.
A fourth embodiment;
the FDSOI source-drain epitaxial growth method provided by the invention comprises the following steps:
s1, manufacturing FDSOI according to the prior art until depositing the first layer of isolation side wall;
s2, etching to remove the first isolation side walls on the top of the insulator silicon and the top of the grid, and reserving the first isolation side walls on two sides of the grid;
s3, growing silicon epitaxy on the top of the insulator silicon, and opening a groove window;
s4, growing the NMOS source and drain region silicon or germanium silicon epitaxially;
s5, growing germanium and silicon epitaxy of PMOS source and drain regions, including: depositing a hard mask layer to cover the NMOS region, cleaning, growing a germanium-silicon epitaxy, forming a PMOS source drain region by an etching process, and removing the hard mask layer; the thickness of the residual germanium-silicon layer after cleaning before the growth of the germanium-silicon is larger than the minimum value of the thickness required by the epitaxial growth of the PMOS source drain;
and S6, etching to remove the epitaxial silicon beside the bottom of the first layer of isolation side wall, and executing subsequent processes by adopting the prior art.
Wherein the hard mask layer is a silicon nitride layer or a silicon oxynitride layer.
A fifth embodiment;
the FDSOI source-drain epitaxial growth method provided by the invention comprises the following steps:
s1, manufacturing FDSOI according to the prior art until depositing the first layer of isolation side wall;
s2, etching to remove the first isolation side walls on the top of the insulator silicon and the top of the grid, and reserving the first isolation side walls on two sides of the grid;
s3, growing silicon epitaxy on the top of the insulator silicon, and opening a groove window;
s4, the NMOS source drain region silicon or germanium silicon epitaxial growth includes: depositing a hard mask layer to cover the PMOS region, growing silicon epitaxy, forming an NMOS source drain region by an etching process, removing the hard mask layer and the like;
s5, growing germanium and silicon epitaxy of PMOS source and drain regions, including: depositing a hard mask layer to cover the NMOS region, cleaning, growing a germanium-silicon epitaxy, forming a PMOS source drain region by an etching process, and removing the hard mask layer; the thickness of the residual germanium-silicon layer after cleaning before the growth of the germanium-silicon is larger than the minimum value of the thickness required by the epitaxial growth of the PMOS source drain;
and S6, etching to remove the epitaxial silicon beside the bottom of the first layer of isolation side wall, and executing subsequent processes by adopting the prior art.
Wherein the hard mask layer is a silicon nitride layer or a silicon oxynitride layer.
A sixth embodiment;
the FDSOI source-drain epitaxial growth method provided by the invention comprises the following steps:
s1, manufacturing FDSOI according to the prior art until depositing the first layer of isolation side wall;
s2, etching to remove the first isolation side walls on the top of the insulator silicon and the top of the grid, and reserving the first isolation side walls on two sides of the grid;
s3, growing silicon epitaxy on the top of the insulator silicon, and opening a groove window;
s4, the NMOS source drain region silicon or germanium silicon epitaxial growth includes: depositing a hard mask layer to cover the PMOS region, growing silicon epitaxy, forming an NMOS source drain region by an etching process, removing the hard mask layer and the like;
s5, growing germanium and silicon epitaxy of PMOS source and drain regions, including: depositing a hard mask layer to cover the NMOS region, cleaning, growing a germanium-silicon epitaxy, forming a PMOS source drain region by an etching process, and removing the hard mask layer; the thickness of the residual germanium-silicon layer after cleaning before the growth of the germanium-silicon is larger than the minimum value of the thickness required by the epitaxial growth of the PMOS source drain;
and S6, removing the epitaxial silicon beside the bottom of the side wall by blanket etching in the shortest time which can be achieved by the process, and executing the subsequent process by adopting the prior art.
Wherein the hard mask layer is a silicon nitride layer or a silicon oxynitride layer.
Optionally, the FDSOI source-drain epitaxial growth method in the first to fifth embodiments is used in a manufacturing process of FDSOI with a thickness of 45nm, 40nm, 32nm, 28nm, 22nm, 20nm or less than 16 nm.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (9)

1. An FDSOI source-drain epitaxial growth method is characterized by comprising the following steps:
s1, manufacturing FDSOI according to the prior art until the first layer of isolation side wall is deposited;
s2, etching to remove the first isolation side walls on the top of the insulator silicon and the top of the grid, and reserving the first isolation side walls on two sides of the grid;
s3, growing silicon epitaxy on the top of the insulator silicon, and opening a groove window;
s4, the first material of the NMOS source and drain areas grows epitaxially;
s5, epitaxially growing a second material in the PMOS source and drain region, wherein the thickness of the residual germanium-silicon layer after cleaning before the growth of the germanium-silicon is larger than the minimum value of the thickness required by the epitaxial growth of the PMOS source and drain;
and S6, etching and removing the epitaxial silicon beside the bottom of the first layer of isolation side wall.
2. The FDSOI source drain epitaxial growth method of claim 1, wherein: the first material is silicon or silicon germanium, and the second material is silicon germanium.
3. The FDSOI source drain epitaxial growth method of claim 1, wherein: the first layer of isolation side wall is a silicon nitride isolation side wall.
4. The FDSOI source drain epitaxial growth method of claim 3, wherein: and S4, depositing a hard mask layer to cover the PMOS region, growing silicon epitaxy, forming an NMOS source and drain region by an etching process, and removing the hard mask layer.
5. The FDSOI source drain epitaxial growth method of claim 4, wherein: the hard mask layer is a silicon nitride layer or a silicon oxynitride layer.
6. The FDSOI source drain epitaxial growth method of claim 3, wherein: and S5, depositing a hard mask layer to cover the NMOS region, cleaning, growing germanium-silicon epitaxy, forming a PMOS source/drain region by an etching process, and removing the hard mask layer.
7. The FDSOI source drain epitaxial growth method of claim 6, wherein: the hard mask layer is a silicon nitride layer or a silicon oxynitride layer.
8. The FDSOI source drain epitaxial growth method of claim 1, wherein: when step S6 is performed, the epitaxial silicon beside the bottom of the sidewall is removed by blanket etching in the shortest time that the process can reach.
9. The FDSOI source-drain epitaxial growth method of any of claims 1-8, characterized in that: it is used for the manufacturing process of 45nm, 40nm, 32nm, 28nm, 22nm, 20nm or less than 16nm FDSOI.
CN202210394301.1A 2022-04-14 2022-04-14 FDSOI source-drain epitaxial growth method Pending CN114899143A (en)

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