JP2004531900A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2004531900A5 JP2004531900A5 JP2003507886A JP2003507886A JP2004531900A5 JP 2004531900 A5 JP2004531900 A5 JP 2004531900A5 JP 2003507886 A JP2003507886 A JP 2003507886A JP 2003507886 A JP2003507886 A JP 2003507886A JP 2004531900 A5 JP2004531900 A5 JP 2004531900A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- copper
- depositing
- cover
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 15
- 229910052802 copper Inorganic materials 0.000 claims 15
- 239000010949 copper Substances 0.000 claims 15
- 239000000956 alloy Substances 0.000 claims 11
- 229910045601 alloy Inorganic materials 0.000 claims 11
- 238000005275 alloying Methods 0.000 claims 11
- 238000000151 deposition Methods 0.000 claims 11
- 238000000034 method Methods 0.000 claims 11
- 238000000137 annealing Methods 0.000 claims 5
- 239000002184 metal Substances 0.000 claims 5
- 229910052751 metal Inorganic materials 0.000 claims 5
- 239000006104 solid solution Substances 0.000 claims 4
- 230000004888 barrier function Effects 0.000 claims 3
- 229910052763 palladium Inorganic materials 0.000 claims 3
- 229910052718 tin Inorganic materials 0.000 claims 3
- 230000008021 deposition Effects 0.000 claims 2
- 238000001755 magnetron sputter deposition Methods 0.000 claims 2
- 238000005240 physical vapour deposition Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/884,027 | 2001-06-20 | ||
| US09/884,027 US6656834B1 (en) | 2001-06-20 | 2001-06-20 | Method of selectively alloying interconnect regions by deposition process |
| PCT/US2002/012773 WO2003001589A2 (en) | 2001-06-20 | 2002-04-02 | A method of selectively alloying interconnect regions by depostion process |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2004531900A JP2004531900A (ja) | 2004-10-14 |
| JP2004531900A5 true JP2004531900A5 (enExample) | 2006-01-05 |
| JP4886165B2 JP4886165B2 (ja) | 2012-02-29 |
Family
ID=25383816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003507886A Expired - Lifetime JP4886165B2 (ja) | 2001-06-20 | 2002-04-02 | デポジション処理によって、相互接続領域を選択的に合金にする方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6656834B1 (enExample) |
| EP (1) | EP1407488A2 (enExample) |
| JP (1) | JP4886165B2 (enExample) |
| KR (1) | KR20040012912A (enExample) |
| CN (1) | CN100490113C (enExample) |
| TW (1) | TW575909B (enExample) |
| WO (1) | WO2003001589A2 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4647184B2 (ja) * | 2002-12-27 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| KR100573897B1 (ko) * | 2003-12-30 | 2006-04-26 | 동부일렉트로닉스 주식회사 | 반도체 제조 방법 |
| JP4764606B2 (ja) * | 2004-03-04 | 2011-09-07 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US7327033B2 (en) * | 2004-08-05 | 2008-02-05 | International Business Machines Corporation | Copper alloy via bottom liner |
| US8164190B2 (en) * | 2009-06-25 | 2012-04-24 | International Business Machines Corporation | Structure of power grid for semiconductor devices and method of making the same |
| KR101131352B1 (ko) | 2009-08-31 | 2012-04-04 | 삼성전기주식회사 | 인쇄회로기판의 제조방법 |
| CN102005384B (zh) * | 2010-09-16 | 2012-02-01 | 哈尔滨工程大学 | 铜金属化自形成阻挡层低温退火方法 |
| US10461026B2 (en) | 2016-06-30 | 2019-10-29 | International Business Machines Corporation | Techniques to improve reliability in Cu interconnects using Cu intermetallics |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2850380B2 (ja) * | 1989-07-11 | 1999-01-27 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
| KR0165813B1 (ko) * | 1995-04-12 | 1999-02-01 | 문정환 | 접속홀의 플러그 형성 방법 |
| KR19980032463A (ko) * | 1996-10-03 | 1998-07-25 | 윌리엄비.켐플러 | 개선된 전자이주 능력을 위한 비아(ｖｉａ) 패드와 캡 |
| US5913147A (en) * | 1997-01-21 | 1999-06-15 | Advanced Micro Devices, Inc. | Method for fabricating copper-aluminum metallization |
| JP3479199B2 (ja) * | 1997-03-19 | 2003-12-15 | 沖電気工業株式会社 | 半導体素子の多層配線の製造方法 |
| US5930669A (en) * | 1997-04-03 | 1999-07-27 | International Business Machines Corporation | Continuous highly conductive metal wiring structures and method for fabricating the same |
| JPH10294317A (ja) | 1997-04-18 | 1998-11-04 | Matsushita Electric Ind Co Ltd | 積層配線構造体およびその製造方法 |
| US6037257A (en) | 1997-05-08 | 2000-03-14 | Applied Materials, Inc. | Sputter deposition and annealing of copper alloy metallization |
| US6387805B2 (en) * | 1997-05-08 | 2002-05-14 | Applied Materials, Inc. | Copper alloy seed layer for copper metallization |
| US6130161A (en) | 1997-05-30 | 2000-10-10 | International Business Machines Corporation | Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity |
| US6069068A (en) * | 1997-05-30 | 2000-05-30 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
| US6249055B1 (en) | 1998-02-03 | 2001-06-19 | Advanced Micro Devices, Inc. | Self-encapsulated copper metallization |
| US5981382A (en) * | 1998-03-13 | 1999-11-09 | Texas Instruments Incorporated | PVD deposition process for CVD aluminum liner processing |
| US6268289B1 (en) * | 1998-05-18 | 2001-07-31 | Motorola Inc. | Method for protecting the edge exclusion of a semiconductor wafer from copper plating through use of an edge exclusion masking layer |
| US6144096A (en) | 1998-10-05 | 2000-11-07 | Advanced Micro Devices, Inc. | Low resistivity semiconductor barrier layers and manufacturing method therefor |
| US6242349B1 (en) | 1998-12-09 | 2001-06-05 | Advanced Micro Devices, Inc. | Method of forming copper/copper alloy interconnection with reduced electromigration |
-
2001
- 2001-06-20 US US09/884,027 patent/US6656834B1/en not_active Expired - Lifetime
-
2002
- 2002-04-02 JP JP2003507886A patent/JP4886165B2/ja not_active Expired - Lifetime
- 2002-04-02 EP EP02780866A patent/EP1407488A2/en not_active Ceased
- 2002-04-02 WO PCT/US2002/012773 patent/WO2003001589A2/en not_active Ceased
- 2002-04-02 KR KR10-2003-7016123A patent/KR20040012912A/ko not_active Ceased
- 2002-04-02 CN CNB028120493A patent/CN100490113C/zh not_active Expired - Lifetime
- 2002-06-14 TW TW91112994A patent/TW575909B/zh not_active IP Right Cessation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2002103782A3 (en) | Barrier enhancement process for copper interconnects | |
| EP0877421A2 (en) | Sputter deposition and annealing of copper alloy metallization M | |
| TWI255873B (en) | Methods for forming copper interconnect structures by co-plating of noble metals and structures formed thereby | |
| JP2003511858A5 (enExample) | ||
| US20080280151A1 (en) | Copper diffusion barrier | |
| WO2008027186A3 (en) | Integrated process for sputter deposition of a conductive barrier layer, especially an alloy of ruthenium and tantalum, underlying copper or copper alloy seed layer | |
| JP2001516153A5 (enExample) | ||
| US8169077B2 (en) | Dielectric interconnect structures and methods for forming the same | |
| HK76392A (en) | Process for the manufacture of a titanium/titanium nitride double layer for use as a contact and barrier layer in very large scale integrated circuits | |
| TWI256723B (en) | Process for manufacturing multiple layer wiring substrate onto which thin film capacitor is incorporated | |
| JP2004531900A5 (enExample) | ||
| US20010036734A1 (en) | Method of formation of conductive lines on integrated circuits | |
| KR20090035127A (ko) | 반도체 소자의 금속배선 형성방법 | |
| JP2682668B2 (ja) | 半導体装置の金属化層間の相互接続を提供する方法及び装置 | |
| US6245668B1 (en) | Sputtered tungsten diffusion barrier for improved interconnect robustness | |
| JP2570857B2 (ja) | 半導体装置の製造方法 | |
| KR980005571A (ko) | 반도체 소자의 플러그(Plug) 형성 방법 | |
| EP0987752A3 (en) | Improved-reliability damascene interconnects and process of manufacture | |
| US6475900B2 (en) | Method for manufacturing a metal interconnection having enhanced filling capability | |
| KR970030333A (ko) | 반도체소자의 도전 배선 콘택 제조방법 | |
| JPH0414874A (ja) | 半導体集積回路装置の金属配線構造の形成方法 | |
| KR100291717B1 (ko) | 반도체디바이스의금속배선방법 | |
| KR100574922B1 (ko) | 반도체장치의 다층배선구조 및 그 제조방법 | |
| KR100197669B1 (ko) | 반도체 소자의 금속배선 형성방법 | |
| JP3288010B2 (ja) | 半導体素子の金属配線形成方法 |