JP2004513221A - 銅シード層の異常を克服し表面形状サイズ及びアスペクト比を調整する方法と装置 - Google Patents

銅シード層の異常を克服し表面形状サイズ及びアスペクト比を調整する方法と装置 Download PDF

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Publication number
JP2004513221A
JP2004513221A JP2001586638A JP2001586638A JP2004513221A JP 2004513221 A JP2004513221 A JP 2004513221A JP 2001586638 A JP2001586638 A JP 2001586638A JP 2001586638 A JP2001586638 A JP 2001586638A JP 2004513221 A JP2004513221 A JP 2004513221A
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Japan
Prior art keywords
substrate
conductive material
layer
seconds
aspect ratio
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JP2001586638A
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English (en)
Japanese (ja)
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JP2004513221A5 (enExample
Inventor
ヘイ，　ピーター
ワック，　ヤン−サン，　レオ
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Applied Materials Inc
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Applied Materials Inc
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Publication of JP2004513221A publication Critical patent/JP2004513221A/ja
Publication of JP2004513221A5 publication Critical patent/JP2004513221A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18—Electroplating using modulated, pulsed or reversing current
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers
    • H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089—Stacks of seed layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2001586638A 2000-05-23 2001-05-10 銅シード層の異常を克服し表面形状サイズ及びアスペクト比を調整する方法と装置 Withdrawn JP2004513221A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US20650000P 2000-05-23 2000-05-23
PCT/US2001/015200 WO2001090446A2 (en) 2000-05-23 2001-05-10 Method and apparatus to overcome anomalies in copper seed layers and to tune for feature size and aspect ratio

Publications (2)

Publication Number Publication Date
JP2004513221A true JP2004513221A (ja) 2004-04-30
JP2004513221A5 JP2004513221A5 (enExample) 2005-06-02

Family

ID=22766672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001586638A Withdrawn JP2004513221A (ja) 2000-05-23 2001-05-10 銅シード層の異常を克服し表面形状サイズ及びアスペクト比を調整する方法と装置

Country Status (5)

Country Link
US (1) US6808612B2 (enExample)
EP (1) EP1337693A2 (enExample)
JP (1) JP2004513221A (enExample)
TW (1) TW492078B (enExample)
WO (1) WO2001090446A2 (enExample)

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US10214826B2 (en) * 2013-01-29 2019-02-26 Novellus Systems, Inc. Low copper electroplating solutions for fill and defect control
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US9496145B2 (en) 2014-03-19 2016-11-15 Applied Materials, Inc. Electrochemical plating methods
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US20160309596A1 (en) * 2015-04-15 2016-10-20 Applied Materials, Inc. Methods for forming cobalt interconnects
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US11203816B1 (en) * 2020-10-23 2021-12-21 Applied Materials, Inc. Electroplating seed layer buildup and repair

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Also Published As

Publication number Publication date
US6808612B2 (en) 2004-10-26
WO2001090446A3 (en) 2003-06-12
WO2001090446A2 (en) 2001-11-29
TW492078B (en) 2002-06-21
US20020011415A1 (en) 2002-01-31
EP1337693A2 (en) 2003-08-27

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