WO2003085713A1 - Homogeneous copper-tin alloy plating for enhancement of electro-migration resistance in interconnects - Google Patents

Homogeneous copper-tin alloy plating for enhancement of electro-migration resistance in interconnects Download PDF

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Publication number
WO2003085713A1
WO2003085713A1 PCT/US2003/002224 US0302224W WO03085713A1 WO 2003085713 A1 WO2003085713 A1 WO 2003085713A1 US 0302224 W US0302224 W US 0302224W WO 03085713 A1 WO03085713 A1 WO 03085713A1
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Prior art keywords
plating
copper
tin
method
plating solution
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PCT/US2003/002224
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French (fr)
Inventor
Deenesh Padhi
Sivakami Ramanathan
Chris R. Mcguirk
Srinivas Gandikota
Girish Dixit
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Applied Materials, Inc.
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Priority to US37051202P priority Critical
Priority to US60/370,512 priority
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Publication of WO2003085713A1 publication Critical patent/WO2003085713A1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/56Electroplating: Baths therefor from solutions of alloys
    • C25D3/58Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of copper
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48After-treatment of electroplated surfaces
    • C25D5/50After-treatment of electroplated surfaces by heat-treatment
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors coated first with a seed layer, e.g. for filling vias

Abstract

Embodiments of the invention may generally provide a method for plating a homogenous copper tin alloy onto a semiconductor substrate. The method generally includes providing a plating solution to a plating cell, wherein the plating solution contains an acid, a copper ion source, and a tin ion source, the copper ion source including up to about 98.5% of the metal ions and the tin ions including up to about 1.5% of the metal ions, providing a plating bias to a conductive layer formed on the semiconductor substrate while the conductive layer is in fluid contact with the plating solution, the plating bias being configured to overlap a plating potential range of both copper and tin, and simultaneously plating copper and tin ions onto the conductive layer from the plating solution to form a homogenous copper tin alloy layer on the conductive layer.

Description

HOMOGENEOUS COPPER-TIN ALLOY PLATING FOR ENHANCEMENT OF ELECTRO-MIGRATION RESISTANCE IN INTERCONNECTS

INVENTORS:

DEENESH PADHI

SIVAKAMI RAMANATHAN

CHRIS R. MCGUIRK

SRINIVAS GANDIKOTA

GIRISH DIXIT

BACKGROUND OF THE INVENTION Field of the Invention

[0001] Embodiments of the invention generally relate to a method and apparatus for depositing a substantially homogenous thin film copper-tin alloy into a high aspect ratio sub 0.15 micron sized feature on a semiconductor substrate.

Description of the Related Art

[0002] Metallization of sub-quarter micron sized features is a foundational technology for present and future generations of integrated circuit manufacturing processes. More particularly, in devices such as ultra large scale integration-type (ULSI) devices, i.e., devices having integrated circuits with more than a million logic gates, the multilevel interconnects that lie at the heart of these devices are generally formed by filling high aspect ratio interconnect features with a conductive material, such as copper or aluminum, for example. Conventionally, deposition techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), for example, have been used to fill these interconnect features. However, as interconnect sizes decrease and aspect ratios increase, void-free interconnect feature fill via conventional metallization techniques becomes increasingly difficult. As a result thereof, plating techniques, such as electrochemical plating (ECP) and electroless plating, have emerged as viable processes for void free filling of sub- quarter micron sized high aspect ratio interconnect features in integrated circuit manufacturing processes.

[0003] In an ECP process, for example, sub-quarter micron sized high aspect ratio features formed into the surface of a substrate may be efficiently filled with a conductive material, such as copper. ECP plating processes are generally two stage processes, wherein a seed layer is first formed over the surface features of the substrate, and then the surface features of the substrate are exposed to an electrolyte solution, while an electrical bias is simultaneously applied between the substrate and an anode positioned within the electrolyte solution. The electrolyte solution is generally rich in ions to be plated onto the surface of the substrate, and therefore, the application of the electrical bias causes these ions to be plated onto the seed layer.

[0004] However, one challenge associated with ECP copper deposition processes, for example, is that the extremely small size of the conductive interconnect lines results in a substantial increase in the potential to form voids in the interconnect lines via electromigration modes. Inasmuch as the substantial increase in the potential to form voids in the interconnect lines via electromigration modes is directly related to the intrinsic electromigration resistance of the copper line, it is desirable to generate conductive lines having minimal electrical resistance, while also having desirable electromigration characteristics. One method for improving the electromigration resistance of copper lines is to alloy copper with a heavy metal without appreciably increasing the electrical resistance of the alloy when compared to copper, while simultaneously increasing the electromigration resistance characteristics of the alloy.

[0005] Tin has been found to be a suitable alloying element that improves the electromigration resistance of copper. However, current deposition techniques generally deposit individual layers of copper and tin on top of each other, and then anneal the entire structure to form a copper tin alloy. This approach may be problematic, as the annealing process has been shown to form copper tin alloys having varying uniformity/homogeneity in cross-section, which may generate inconsistent conductive characteristics along the conductive line that may result in void formation. Additionally, although deposition of copper-tin alloys via electrochemical deposition has been conventionally used to generate solder bump points and other larger scale features, conventional apparatuses and methods have not been successful in depositing a homogenous copper-tin alloy into a high aspect ratio feature, i.e., a feature where the height to width ratio is at least 7, without encountering voids in the fill deposition. Additionally, conventional copper-tin alloy plating methods have focused upon alloys having large percentages of tin and small concentrations of copper, which is undesirable for semiconductor device interconnects, as the resistance characteristics of tin rich alloys are substantially higher than copper or copper rich alloys. Void free fill of high aspect ratio features, such as those that make up the multilevel conductive interconnects in semiconductor devices, is critical to the continued success and continued progress of ULSI technology.

[0006] Therefore, there is a need for a method and apparatus for depositing a substantially homogenous copper-tin alloy thin film into a high aspect ratio feature of a semiconductor device.

SUMMARY OF THE INVENTION

[0007] Aspects of the invention generally provide an electrochemical plating cell configured to plate a homogenous copper-tin alloy into high aspect ratio sub 0.15 micron features of a semiconductor device. In one aspect, the plating cell includes a substrate support member having a substantially planar lower surface configured to engage a non-production side of a substrate, and an annular insulative cathode contact ring having a plurality of conductive biasing members formed therein, each of the plurality of conductive biasing members being configured to electrically engage a plating surface of a substrate. In one embodiment of this aspect, the plating cell further includes a plating cell container configured to hold a volume of electrochemical plating solution, a power supply in electrical communication with the plurality of conductive members and being configured to apply a plating bias to the plating surface, and an anode positioned in the plating cell container in a position where the anode is immersed in the electrochemical plating solution. During immersion of the substrate, the plating solution is flowed into the plating cell at a flow rate of between about 0.5 GPM and about 6.5 GPM and has a concentration of copper ions of between about 0.2M and 0.8M and a concentration of tin ions at between about 0.1 M and about 0.9M, and the plating bias has a current density of between about 5 mA/cm2 and about 60 mA/cm2.

[0008] Another aspect of the invention provides a method for plating a homogenous copper-tin alloy into a high aspect ratio sub 0.15 micron feature on a plating surface of a semiconductor substrate. In one aspect, the method provides a plating solution to an electrochemical plating cell, wherein the plating solution includes an acid solution having at least one of sulfuric acid and phosphoric acid therein, a copper ion source, a tin ion source having at least one of SnSO and SnCI2 therein, and at least one organic plating additive. In one embodiment of the aspect, the method further includes exposing a deposition surface having a seed layer formed thereon to the plating solution, supplying an electrical deposition bias to the seed layer, wherein the deposition bias generates a current density of between about 5 mA/cm2 and about 60 mA cm2 across the surface of the seed layer, and rotating the deposition surface at a rotation rate of between about 5 RPM and about 40 RPM, simultaneously plating tin ions and copper ions on the substrate surface to form a homogenous copper-tin alloy, and annealing the copper-tin alloy at a temperature of between about 200° C and about 400° C for a duration of between about 5 minutes and about 60 minutes.

[0009] Embodiments of the invention may further provide a method for plating a homogenous copper tin alloy onto a semiconductor substrate. The method generally includes providing a plating solution to a plating cell, wherein the plating solution contains an acid, a copper ion source, and a tin ion source, the copper ion source including up to about 98.5% of the metal ions and the tin ions including up to about 1.5% of the metal ions, providing a plating bias to a conductive layer formed on the semiconductor substrate while the conductive layer is in fluid contact with the plating solution, the plating bias being configured to overlap a plating potential range of both copper and tin, and simultaneously plating copper and tin ions onto the conductive layer from the plating solution to form a homogenous copper tin alloy layer on the conductive layer.

[0010] Embodiments of the invention may further provide a method for plating a homogenous copper-tin alloy onto a semiconductor substrate. The method generally includes providing a plating solution to an electrochemical plating cell, exposing a deposition surface of the substrate having a seed layer formed thereon to the plating solution, supplying an electrical deposition bias to the seed layer, wherein the deposition bias generates a current density of between about 5 mA/cm2 and about 60 mA/cm2 across the surface of the seed layer, simultaneously plating tin ions and copper ions on the substrate surface to form a homogenous copper-tin alloy. Further, the plating solution generally includes an acid comprising at least one of sulfuric acid and phosphoric acid, a copper ion source at a concentration of between about 0.4 and about 0.9M, a tin ion source, the tin ion source including at least one of SnSO4 and SnC , the tin ion source being at a concentration of between about 0.1 and 0.4, and at least one organic plating additive.

[0011] Embodiments of the invention may further provide a method for plating a substantially homogenous copper tin alloy layer on a conductive seed layer formed onto a semiconductor substrate. The method generally includes providing a plating solution having both copper ions and tin ions therein, exposing the conductive seed layer to the plating solution, and applying a plating bias to the conductive seed layer to plate the substantially homogenous copper tin alloy layer onto the conductive seed layer, wherein the plating solution includes between about 0.2 M and about 0.5 M of copper ion concentration and between about 0.4 M and about 0.8M of tin ion concentration, and wherein the plating bias includes a current density of between about 5 mA/cm2 and about 60 mA/cm2.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

[0013] Figure 1 illustrates an exemplary weir-type plating cell of the invention.

[0014] Figure 2 illustrates an exemplary face down type plating cell of the invention.

[0015] Figure 3 illustrates a current verses voltage plot for individual deposition of copper and tin. [0016] Figure 4 illustrates exemplary tin concentrations verses current densities plots for embodiments of the invention.

[0017] Figures 5a and 5b illustrate exemplary tin concentrations verses substrate revolution rates in the plating solution for embodiments of the invention.

[0018] Figure 6 illustrates a plot of Rs verses current densities for embodiments of the invention.

[0019] Figure 7 illustrates a plot of Rs verses the revolution rate for the substrate in the plating solution for embodiments of the invention.

[0020] Figure 8 illustrates a plot of Rs verses current densities for embodiments of the invention.

[0021] Figure 9 illustrates a plot of the weight percentage of tin verses the flow rate of the plating solution into the plating cell for embodiments of the invention.

[0022] Figure 10 illustrates a plot of the angular orientation of the homogenous film verses the counts.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Aspects of the invention generally provide a method and apparatus for forming a substantially homogenous copper-tin alloy layer onto a semiconductor substrate, and in particular, for filling high aspect ratio (7 or higher) features with a substantially homogenous copper-tin alloy that has a large concentration of copper (above about 97%) and a substantially smaller concentration of tin (about 0.2% to about 1.5%). The copper-tin alloy, which provides enhanced electromigration resistance in conductive features of semiconductor devices and prevents the formation of voids at the interfaces when high current is passed through the interconnect, is generally formed onto the substrate and into the features via an ECP process. Embodiments of the ECP process for depositing the copper-tin alloy generally include adding a calculated amount of tin to a copper plating solution and applying a calculated voltage to a substrate immersed in the plating solution. The calculated amount of tin added to the plating solution and the calculated voltage applied are specifically selected to provide for the deposition of a substantially O 03/085713 homogenous copper-tin alloy. Additionally, embodiments of the invention are configured to plate the copper-tin alloy into very high aspect ratio features, i.e., greater than 10:1, for narrow conductive structures, i.e., sub 0.10 micron width features. The deposition of the copper-tin alloy is accomplished, for example, by depositing a very thin copper-tin layer on a PVD copper seed layer by an electroless deposition process followed by electroplating the copper-tin alloy in the plating solution described below.

[0024] Figure 1 illustrates a cross sectional view of an exemplary weir-type plater 100 of the invention. Plater 100 generally includes an electrolyte container 112 having an open top portion and a lid/substrate holder 114 that is pivotally disposed above the electrolyte container 112. Lid/substrate holder 114 is generally configured to support a substrate 122 on a lower surface of thereof via a plurality of grooves 124 that are formed into the lower surface of the substrate holder 114. Grooves 124 are in fluid communication with a vacuum pump (not shown), and therefore, when a negative pressure is applied to groves 124 by the vacuum pump, the substrate 122 is secured to the substrate holder 114 in a vacuum chucking-type operation.

[0025] A contact ring 120 is positioned on a lower surface of the lid member, for example, and is in electrical communication with a power supply (not shown). As such, contact ring 120 is configured to electrically engage the substrate 122 and provide a plating bias thereto. Contact ring 120, which may be annular in shape, generally includes a plurality of conductive contact pins 126 distributed about the peripheral portion of the contact ring 120. The plurality of contact pins 126 generally extend radially inwardly over the perimeter of the substrate 122 to contact a conductive seed layer formed on substrate 122 with the tips of the contact pins 126. Additionally, electrolyte container 112 may include a separation membrane 128 positioned between an anode 116 and the substrate 122. The membrane 128 may operate to define respective anodic and cathodic chambers in the electrolyte container 112, i.e., the anodic chamber will surround the anode and the cathodic chamber will be adjacent the plating surface of the substrate. The anode 116 is configured to supply ions to a plating solution contained within container 112. The separation membrane is generally a membrane configured to allow the plating solution supplied to container 112 to flow therethrough, while restricting the flow of other materials, i.e., contaminants, copper balls, etc., from flowing through the membrane and contacting the substrate 122. The plating solution is supplied to the electrolyte container 112 by a supply line 118, which is generally in fluid communication with a pump and electrolyte supply system, as is known in the art.

[0026] Further, with regard to the construction and/or configuration of anode 116, it is to be noted that tin can exist in both a divalent and a tetravalent state. As such, the transition from the divalent to the tetravalent state generally takes place at a potential more negative than that of the potential of copper metal to oxidize to Cu2+. This presents a challenge during plating, as the Sn2+ ions will generally be oxidized on the anode surface resulting in the formation of SnO2, which is a ceramic that is not soluble in acids. These solid particles may block the anode and necessitate a rise in the applied voltage with plating, eventually leading to complete isolation of the anode from the electrolyte. Furthermore, the formation of SnO2 also causes the bath to be generally dirty and causes the filters to clog frequently and decrease the Sn2+ concentration in the bath. However, embodiments of the present invention address these challenges by increasing the anode surface area to such an extent that the anodic current density is limited to small values (even as the cathodic current density can be as large as 60 mA/cm2). This results in maintaining the anodic potential at very small values where the oxidation reaction of Sn2+ to Sn4+ is not possible.

[0027] Additionally, the penetration of Sn2+ ions into the anode chamber can be prevented by insertion of a cationic membrane. This can also be achieved by having an anode chamber (not having any Sn2+), which is separated from the cathodic chamber by a fluid permeable membrane. The anodic chamber should have a positive pressure with respect to the cathodic chamber, so that there is fluid flow only in the direction towards the cathodic chamber. Furthermore, the temperature of the anodic chamber can be kept higher than that in the cathodic chamber so that convection is towards the cathode chamber.

[0028] Figure 2 illustrates a cross sectional view of another exemplary electroplating process cell 200 of the invention. Processing cell 200 generally includes a head assembly 210, a process kit 220, and an electrolyte collector 240. The electrolyte collector 240 is generally configured to be secured onto a mainframe of a plating system. The electrolyte collector 240 generally includes an inner wall 246, an outer wall 248, and a bottom 247 connecting the respective walls. An electrolyte outlet 249 is disposed through the bottom 247 of the electrolyte collector 240 and connected to an electrolyte replenishing system through tubes, hoses, pipes or other fluid transfer connectors. The head assembly 210 is generally mounted onto a head assembly frame 252 that includes a mounting post 254 and a cantilever arm 256. The mounting post 254 is generally mounted onto a mainframe body 214, and the cantilever arm 256 generally extends laterally from an upper portion of the mounting post 254. Generally, mounting post 254 provides rotational movement with respect to a vertical axis along the mounting post to allow rotation of the head assembly 210. The lower end of the cantilever arm 256 is generally connected to a cantilever arm actuator 257, such as a pneumatic cylinder, mounted on the mounting post 254. The cantilever arm actuator 257 provides pivotal movement of the cantilever arm 256 with respect to the joint between the cantilever arm 256 and the mounting post 254.

[0029] Head assembly 210 generally includes a substrate holder assembly 250 and a substrate assembly actuator 258. The substrate assembly actuator 258 operates to rotate and/or raise/lower the substrate holder assembly 250. The substrate holder assembly 250 generally includes a substrate holder 264 and an integrally formed cathode contact ring 266. Substrate holder assembly 250 includes a plurality of vacuum channels 267 formed in a lower side of the substrate holder assembly 250. Vacuum channels 267, which are generally in communication with a vacuum pump (not shown), for example, are annularly positioned about the lower surface of the substrate holder assembly 250 and configured to provide sufficient vacuum pressure to secure a substrate thereto for processing. The contact ring 266, which is generally in electrical communication with a power supply (not shown), includes an annular body having a plurality of conducting members disposed thereon for communicating electrical energy from the power supply to a substrate positioned on the holder assembly 250. The annular body of the contact ring 266 is generally constructed of an insulating material in order to electrically isolate the plurality of conducting members from surrounding components other than the substrate. The body and conducting members of the contact ring 266 generally form a diametrically interior substrate seating surface, which, during processing, may support the substrate being processed by the apparatus 200. The contact ring of the invention, however, is configured to electrically engage and contact the substrate being processed on the non-production side of the substrate, i.e., on the backside of the substrate, so that the production side of the substrate is free of electrical or mechanical contacts therewith. As such, substrates processed in plating cell 200 will generally have a backside conductive layer configured to electrically engage the backside contact ring deposited thereon. Additionally, the backside conductive layer, which may generally be a seed layer extension, may be configured to communicate electrical power applied thereto to the front or production side of the substrate in order to cause plating thereon.

[0030] In operation, regardless of the plating cell configuration utilized, a substrate to be plated is generally secured to a substrate support member and the plating surface of the substrate is brought into contact with a plating solution. While in contact with the plating solution, an electrical bias is applied to a seed layer deposited on the plating surface of the substrate. The electrical bias is generally a bias configured to bias the substrate surface/seed layer with a cathodic charge, which causes the plating ions in the plating solution to be urged out of the solution and to plate on the cathodically charged substrate surface/seed layer.

[0031] In conventional plating systems, the plating solution generally includes an aqueous solution that contains sulfuric acid, phosphoric acid, or derivatives thereof. The electroplating solution may further include one or more organic additives, i.e., levelers, suppressors, accelerators, and/or other additives known in the art to facilitate control over the plating process. The additives are typically organic materials that are known to adsorb onto the surface of the substrate being plated. Useful suppressors, for example, may include polyethers, such as polyethylene, glycol, or other polymers such as polypropylene oxide, that are known to inhibit the rate of deposition on the substrate. Useful accelerators, for example, may include sulfides or disulfides, such as bis (3-sulfopropyl) disulfide, which affects the microstructure of copper deposited on the substrate. Useful levelers may generally include amines or polyamines, which improve the thickness distribution of copper deposited on the substrate. [0032] Inasmuch as the present invention is configured to deposit a homogenous copper-tin alloy in an electrochemical plating process, conventional copper plating solutions may be modified to include the tin ions necessary to support copper-tin plating. However, the amount of copper and tin deposited in an electrochemical plating process is generally governed by two factors: first, the plating potential at which plating operations are conducted; and second, the concentration of tin ions in the plating solution in proportion to the concentration of the copper ions in the solution. With regard to the concentration of tin in a plating solution, since tin has a very small solid solubility in copper, generally less than about 0.5 weight percent, incorporation of large amounts of tin into plating solutions generally results in formation of intermetallics, which are known to be detrimental to interconnect applications for semiconductor devices. Therefore, it is desirable to maintain the tin percentage in the plated alloy below about 1.5%, which provides good conductivity characteristics as well as good electromigration characteristics when compared to conventional copper interconnects. Additionally, any local agglomeration of tin, which results from high concentrations of tin in the plating solution or the copper-tin alloy generated, will also produce disadvantages. Therefore, embodiments of the invention contemplate calculated concentrations of tin configured to generate optimal plating characteristics without forming intermetallics, wherein the calculated concentrations of tin are generally substantially smaller than the concentrations of the copper in the plating solution, i.e., less than about 1.5% of tin verses about 98.5% or more of copper.

[0033] With regard to the plating potential used in plating a homogenous copper-tin thin film, it is known that specific plating potential ranges result in optimized plating of specific metals. Therefore, in order for a copper-tin alloy to be plated from a unitary plating solution, the plating potential applied during plating operations will generally overlap the plating potential ranges for both metals. As such, when the plating potential applied is resident in the plating ranges for both metals, then simultaneous plating of both metals may be conducted. It is to be noted, however, that the plating potential for metals varies with the concentration of the metal ions in the plating solution, along with other parameters. As such, particular processing parameters will vary from processing system to processing system. However, for reference, the standard reduction potential for copper is 0.34 volts with respect to a standard hydrogen electrode, while the standard reduction potential for tin is -0.13 volts with respect to a standard hydrogen electrode. The change in the reduction potential resulting from concentration variances may generally be calculated by the following equation:

E = E0 -R .|n[M+], (1 )

wherein E generally represents the deposition potential of the metal, Eo represents the standard deposition potential, R represents a constant, T represents the temperature of the plating solution, and M represents the concentration of the metal ions being plated in the plating solution. Therefore, since the standard deposition/reduction potential of copper is substantially greater than the standard deposition potential of tin, the reduction potential of copper may be brought closer to the reduction potential of tin via manipulation of the processing parameters noted in equation (1 ). However, although equation (1 ) indicates that the reduction potentials for copper and tin may be brought closer in order to facilitate homogenous plating of a copper-tin alloy, changes in ion concentrations alone generally do not result in large changes in the reduction potential of a metal. Additionally, conventional copper plating systems are generally optimized to achieve void free fill of high aspect ratio features, and therefore, it is not desirable to modify the copper ion concentration in the plating solution in order to achieve simultaneous copper and tin plating, as the copper plating characteristics may suffer from modification. As such, another parameter that is adjusted in order to obtain efficient and simultaneous plating of both copper and tin is the plating potential or current density applied to the substrate surface during the plating process.

[0034] For example, Figure 3 illustrates a current verses voltage plot for deposition of copper and tin individually. As illustrated in Figure 3, at potential V-i, there is no tin deposition and very little copper deposition. However, as the potential is increased from Vi to V3, the amount of tin deposition increases, as does the deposition of copper. The same effect, to a limited extent, as noted above, is had by increasing the concentration of tin ions (Sn2+) in the plating solution. Alternatively, although generally undesirable in conventional plating systems for the reasons noted above, the same effect maybe had by decreasing the concentration of the copper ions (Cu2+) in the plating solution. Therefore, in view of the parameters that may be modified in order to facilitate simultaneous copper-tin deposition, embodiments of the invention contemplate that the following processing parameters will allow for the formation of a substantially homogenous copper-tin alloy thin film in an electrochemical plating cell.

[0035] A copper plating solution may be used to implement embodiments of the invention. A conventional copper plating solution, as noted above, may include, for example, a copper source, a halide source, and one or more organic additives configured to provide a control element over the plating characteristics of the plating solution. Copper plating solutions are commercially available from companies such as Enthone and Shipley, for example. The copper source for electrochemical plating solutions may be copper sulfate, for example, which has a copper ion concentration of between about 5 g/L and about 100 g/L. The plating solution may additionally contain an acid, which, for example, may be at a concentration of between about 5 g/L and about 200 g/L, and further, the plating solution may contain halide ions, such as chloride, for example, which may be at a concentration of between about 10 ppm and about 200 ppm. Exemplary acids that may be used in plating solution include sulfuric acid, phosphoric acid, and/or derivatives thereof. In addition to using copper sulfate as the copper source, embodiments of the invention contemplate that the plating solution may include other copper salts, such as copper fluoborate, copper gluconate, copper sulfamate, copper sulfonate, copper pyrophosphate, copper chloride, or copper cyanide, for example, as the copper source. However, embodiments of the invention are not limited to these parameters.

[0036] The conventional copper electroplating solution may further include one or more organic additives configured to provide a control element of the plating characteristics of the plating solution. Additives, which may be, for example, levelers, inhibitors, suppressors, brighteners, accelerators, or other additives known in the art, are typically organic materials that adsorb onto the surface of the substrate being plated. Useful suppressors typically include copolymers - ethylene oxide, propylene oxide, polyethers, such as polyethylene glycol (PEG), for example, and/or other polymers, such as polyethylene-polypropylene oxides, which adsorb on the substrate surface, slowing down copper deposition in the adsorbed areas. Useful accelerators typically include sulfides or disulfides, such as bis (3- sulfopropyl) disulfide, MPSA, and SPS molecules, which compete with suppressors for adsorption sites, accelerating copper deposition in adsorbed areas. Useful levelers typically include amines, thiadiazole, imidazole, and other nitrogen containing organics. Useful inhibitors typically include sodium benzoate and sodium sulfite, which inhibit the rate of copper deposition on the substrate. Additionally hydroquinone may be utilized as an inhibitor, and may be added to the plating solution at in a concentration of up to about 2500 ppm, for example.

[0037] During plating, the additives are generally consumed at the substrate surface. As such, plating systems generally include a replenishment mechanism configured to replace the additives consumed in the plating process, so that a relatively constant concentration of the additives may be maintained the plating solution. However, it is generally known that the differences in diffusion rates of the various additives may result in varying concentrations of particular additives at the top of a high aspect ratio feature compared to the bottom of the feature, thereby setting up , different plating rates at the top of the feature verses the bottom of the feature. For example, suppressors may be larger molecules that diffuse slower than accelerators, and therefore, fewer suppressors may adsorb onto the bottom surface of a high aspect ratio feature than accelerators. As such, the bottom of the feature may plate at a faster rate than the top of the feature, thus increasing the fill rate of the feature. Therefore, an appropriate composition of additives in the plating solution is desired to facilitate void-free fill of high aspect ratio features.

[0038] In order to simultaneously plate both copper and tin, embodiments of the invention contemplate adding a source of tin ions to the above noted copper plating solution. The source for the tin ions includes, for example, SnSO , SnCI2, or another tin containing compound acceptable to a copper electrochemical plating solution. The concentration of the tin ions in the plating solution is between about 0.1 M and about 0.9M, while the concentration of the copper ions in the plating solution is between about 0.2M and about 0.8M. In another aspect of the invention, the copper concentration in the plating solution may be between about 0.4M and about 0.8M. The plating current density applied to the substrate during a copper-tin electrodeposition process using the copper-tin plating solution is between about 5 mA/cm2 and about 60 mA/cm2, for example, at a constant current density. Alternatively, the plating current density may be varied throughout the copper-tin deposition process, i.e., the current density is stepped up, down, or alternated between lower and higher current densities during a plating process. For example, the current density is calculated to facilitate copper-tin deposition in an initial stage of filling a feature, and then the current density is changed to facilitate a more copper heavy deposition once the feature is somewhat lined with a copper-tin alloy at the interfaces. Additionally, the substrate support member supporting the substrate during the copper-tin electrodeposition process is rotated at between about 5 RPM and about 40 RPM, for example, while the flow rate of the copper-tin electroplating solution to the electroplating cell is between about 0.5 GPM and about 6.5 GPM, for example. Embodiments of the invention contemplate that the plating cell is capable of providing generally constant hydrodynamics, so that the flow of the plating solution across the plating surface of the substrate is constant. This operates to maintain a fresh supply of both copper and tin ions at the plating surface, which is important to simultaneous plating operations, as one ion may generally deplete faster than another ion and cause non-uniformity (spatial non- homogenous alloys) in the alloy layer.

[0039] Once the homogenous copper-tin layer is deposited, the layer may be annealed. The annealing process may contribute to the grain size determination, the grain distribution in the alloy, and the crystalline structure of the alloy. Embodiments of the invention contemplate that an annealing process may be implemented to anneal the homogenous copper-tin alloy films, wherein the annealing process includes exposing the film to a temperature of between about 200°C and about 400°C, for example. The exposure/annealing time for the copper- tin film may be between about 5 minutes and about 1 hour, depending upon the structure desired and the thermal budget available for the process. The resulting substantially homogenous copper-tin layer will generally have a tin concentration of up to about 2% per weight. More particularly, the homogenous copper-tin alloy of the invention will have a tin concentration of between about 0.2 weight percent and about 1 weight percent, or between about 0.2 weight percent and about 0.6 weight percent, for example. [0040] Figures 4, 5a, and 5b generally illustrate exemplary plots of the relationship between varying tin concentrations and the current density applied to the substrate during plating and the revolution rate of the substrate during the plating operation. Figure 4, in particular, illustrates a plot of a copper-tin alloy deposition of the invention, wherein the rotation rate of the substrate in the plating solution is maintained constant at 20 RPM, the copper concentration in the plating solution is varied between about 28g/L and about 44g/L and the tin concentration in the plating solution is varied from 5g/L to about 20g/L, which is generally calculated to generate a copper-tin alloy having less than about 1.5% of tin. Figures 5a and 5b illustrate exemplary plots of the a plating process of the invention using varying concentrations of tin and copper in the plating solution at increasing substrate rotation speeds for each sample concentration configuration in the solution. Each of the concentration regimes illustrated in Figures 5a and 5b contain a copper concentration that is substantially higher than the tin concentration of the plating solution, as is desired for the present invention. Figures 6, 7, and 8 illustrate exemplary plots of Rs (mOhms/area) verses the current density for embodiments of the invention. Figure 6 is specifically directed to a post annealing stage. Figure 7 illustrates several exemplary plating solution concentrations, i.e., tin and copper concentrations, applied to a plating process at carried substrate rotation rates. However, as with the previous illustrations, the copper and tin concentrations for the solutions are set up so that there is substantially more copper in the resulting alloy than tin, i.e., only about 0.5% to about 1.5% tin in the deposited alloy as a result of the metal concentrations in the plating solutions. Figure 8 illustrates the relationship between the current density applied to the substrate during the plating process and the resistance per unit of area of the substrate, wherein the relationships are illustrated for several exemplary tin and copper concentrations. Figure 9 illustrates an exemplary plot of the relationship between the tin concentration and the flow rate of the plating solution into the electroplating cell for embodiments of the invention. Figure 10 illustrates a plot of the crystalline structure of copper and a copper-tin alloy as a function of the rotation speed of the substrate during the plating operation. It is to be noted, however, that the data illustrated in Figures 4 - 10 represents confirmed experimental data for embodiments of the invention. [0041] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:
1. A method for plating a homogenous copper tin alloy onto a semiconductor substrate, comprising: providing a plating solution to a plating cell, wherein the plating solution contains an acid, a copper ion source, and a tin ion source, the copper ion source including between about 70% and about 98.5% of the metal ions and the tin ions including between about 1.5% and about 30% of the metal ions; providing a plating bias to a conductive layer formed on the semiconductor substrate while the conductive layer is in fluid contact with the plating solution, the plating bias being configured to overlap a plating potential range of both copper and tin; and simultaneously plating copper and tin ions onto the conductive layer from the plating solution to form a homogenous copper tin alloy layer on the conductive layer.
2. The method of claim 1 , wherein the tin ion source comprises at least one of SnSO4 and SnCI2.
3. The method of claim 1 , wherein the concentration of the copper ion source is between about 0.2M and about 0.9M.
4. The method of claim 1 , wherein the concentration of the tin ion source is between about 0.1 M and about 0.8M.
5. The method of claim 1 , wherein the plating bias includes a current density of between about 5 mA/cm2 and about 60 mA/cm2.
6. The method of claim 1 , further comprising rotating the substrate during the plating process.
7. The method of claim 1 , wherein the plating bias is configured to plate a homogenous copper tin alloy during a first stage and a substantially tin free copper metal layer during a second stage, the second stage occurring after the first stage.
8. The method of claim 1 , further comprising annealing the homogenous copper tin alloy at a temperature of between about 200°C and about 400°C for between about 5 minutes and about 1 hour.
9. The method of claim 1 , further comprising calculating a change in reduction potential for copper and tin resulting from concentration variances from the following equation:
E = Eo -R -ln[M+], wherein E represents the deposition potential of the metal, E0 represents the standard deposition potential, R represents a constant, T represents the temperature of the plating solution, and M represents the concentration of the metal ions being plated in the plating solution.
10. The method of claim 9, wherein the plating bias is calculated from the calculated concentration variances.
11. A method for plating a homogenous copper-tin alloy onto a semiconductor substrate, comprising: providing a plating solution to an electrochemical plating cell, the plating solution comprising: "r an acid comprising at least one of sulfuric acid and phosphoric acid.; a copper ion source at a concentration of between about 0.4M and about 0.9M; a tin ion source, the tin ion source including at least one of SnS0 and SnCfe, the tin ion source being at a concentration of between about 0.1M and 0.4M; and at least one organic plating additive; exposing a deposition surface of the substrate having a seed layer formed thereon to the plating solution; supplying an electrical deposition bias to the seed layer, wherein the deposition bias generates a current density of between about 5 mA/cm2 and about 60 mA/cm2 across the surface of the seed layer; and
19
RECTIFIED SHEET (RULE 91 simultaneously plating tin ions and copper ions on the substrate surface to form a homogenous copper-tin alloy.
12. The method of claim 1 , further comprising annealing the copper-tin alloy at a temperature of between about 200°C and about 400°C for a duration of between about 5 minutes and about 60 minutes.
13. The method of claim 11 , further comprising rotating the substrate during the plating process at a rotation rate of between about 5 RPM and about 40 RPM.
14. The method of claim 11 , wherein the homogenous copper tin alloy includes less than about 1.5% of tin.
15. The method of claim 11 , wherein the homogenous copper tin alloy includes up to about 98.5% copper.
16. The method of claim 11 , wherein the deposition bias is configured to overlap a calculated plating potential range for the particular copper concentration and the particular tin concentration of the plating solution.
17. The method of claim 16, further comprising calculating a change in reduction potential for copper and tin resulting from concentration variances from the following equation:
E = Eo -R -lnϊM*], wherein E represents the deposition potential of the metal, Eo represents the standard deposition potential, R represents a constant, T represents the temperature of the plating solution, and M represents the concentration of the metal ions being plated in the plating solution.
18. The method of claim 11 , further comprising maintaining the electrical deposition bias at a magnitude small enough to prevent an oxidation reaction of Sn2+ to Sn4+.
20
RECTIFIED SHEET (RULE 91)
19. A method for plating a substantially homogenous copper tin alloy layer on a conductive seed layer formed onto a semiconductor substrate, comprising: providing a plating solution having both copper ions and tin ions therein; exposing the conductive seed layer to the plating solution; and applying a plating bias to the conductive seed layer to plate the substantially homogenous copper tin alloy layer onto the conductive seed layer, wherein the plating solution includes between about 0.2M and about 0.5M of copper ion concentration and between about 0.4M and about 0.8M of tin ion concentration, and wherein the plating bias includes a current density of between about 5 mA/cm2 and about 60 mA/cm2.
20. The method of claim 19, wherein the plating bias is calculated to overlap a plating potential range of copper and tin.
21. The method of claim 19, further comprising annealing the substantially homogenous copper tin alloy layer after the plating step.
22. The method of claim .19, further comprising calculating a change in reduction potential for copper and tin resulting from concentration variances from the following equation:
E = Eo -R -ln M*], wherein E represents the deposition potential of the metal, Eo represents the standard deposition potential, R represents a constant, T represents the temperature of the plating solution, and M represents the concentration of the metal ions being plated in the plating solution.
23. The method of claim 22, wherein the calculated reduction potentials are used to determine an alloy plating bias that will overlap copper ions and tin ions in the plating solution.
21
RECTIFIED SHEET RU
PCT/US2003/002224 2002-04-03 2003-01-24 Homogeneous copper-tin alloy plating for enhancement of electro-migration resistance in interconnects WO2003085713A1 (en)

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