US20060175201A1 - Immersion process for electroplating applications - Google Patents

Immersion process for electroplating applications Download PDF

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Publication number
US20060175201A1
US20060175201A1 US11052443 US5244305A US2006175201A1 US 20060175201 A1 US20060175201 A1 US 20060175201A1 US 11052443 US11052443 US 11052443 US 5244305 A US5244305 A US 5244305A US 2006175201 A1 US2006175201 A1 US 2006175201A1
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Prior art keywords
substrate
waveform
plating
method
current
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Abandoned
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US11052443
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Hooman Hafezi
Joseph Behnke
Aron Rosenfeld
Timothy Webb
Joseph Yahalom
Christopher McGuirk
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Applied Materials Inc
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Applied Materials Inc
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18Electroplating using modulated, pulsed or reversing current
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/34Pretreatment of metallic surfaces to be electroplated
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors coated first with a seed layer, e.g. for filling vias
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

A method for immersing a substrate into a plating solution. In one embodiment, the method includes applying a first waveform to the substrate as the substrate is being immersed into the plating solution, stopping the application of the first waveform to the substrate as soon as the substrate is fully immersed inside the plating solution, and applying a second waveform to the substrate prior to the substrate being situated into a plating position.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • Embodiments of the present invention generally relate to a method for immersing a semiconductor substrate into a processing fluid.
  • 2. Description of the Related Art
  • Metallization of sub-quarter micron sized features is a foundational technology for present and future generations of integrated circuit manufacturing processes. More particularly, in devices such as ultra-large-scale-integration devices, i.e., devices having integrated circuits with more than a million logic gates, the multilevel interconnects that lie at the heart of these devices are generally formed by filling high aspect ratio, i.e., greater than about 3:1, interconnect features with a conductive material, such as copper. Conventionally, deposition techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD) have been used to fill these interconnect features. However, as the interconnect sizes decrease and/or aspect ratios increase, void-free interconnect feature fill via conventional metallization techniques becomes increasingly difficult. Therefore, plating techniques, i.e., electrochemical plating (ECP) and electroless plating, have emerged as standard processes for void free filling of sub-quarter micron sized high aspect ratio interconnect features in integrated circuit manufacturing processes.
  • In an ECP process, for example, sub-quarter micron sized high aspect ratio features formed into the surface of a substrate (or a layer deposited thereon) may be efficiently filled with a conductive material. ECP plating processes generally involve two stages, wherein a seed layer is first formed over the surface features of the substrate (generally through PVD, CVD, electroless, electrolytic, or other deposition process), and then the surface features of the substrate are exposed to an electrolyte solution, while an electrical bias is applied between the seed layer and a copper anode positioned within the electrolyte solution. The electrolyte solution generally contains a source of metal that is be plated onto the surface of the substrate, and therefore, the application of the electrical bias causes the metal source to be plated onto the biased seed layer, thus depositing a layer of the ions on the substrate surface that fills the features.
  • However, one challenge associated with ECP processes is that the plating solutions, which are generally acidic, may chemically etch the seed layer during the process of immersing the substrate in the plating solution. Inasmuch as seed layers are generally relatively thin conductive layers, the chemical etching that may take place during the immersion process may result in conductive discontinuities in the seed layer, which may cause plating irregularities in the subsequent plating processes. Therefore, in order to prevent chemical etching during the immersion process, conventional electroplating systems apply an electrical loading bias to the substrate seed layer during the immersion process. The loading bias is generally configured to apply a cathodic bias to the substrate in order to prevent the chemical etching process and to cause at least some forward plating to occur. In a conventional process, the loading bias is a constant voltage applied to the substrate as the substrate is immersed in the plating solution and is maintained until the wafer reaches its plating position. The loading bias must be high enough to protect the seed layer from chemical etching and is in many cases higher for thinner seeds. In general, smaller features require thinner seeds. Therefore, as features become smaller, the required loading bias increases. It may also be desirable to further increase the loading bias beyond the level required to protect the seed layer in order to enhance nucleation of the electrodeposit.
  • However, for smaller features (e.g., about 65 nm or smaller), the conventional process is subject to failure for a number of problems. For example, the loading bias applied during the immersion may fill small features if it is sustained until the plating position is reached. However, this can lead to the formation of undesirable pinch-off voids. A pinch-off void is typically created when the current density on the sidewalls of a feature is high enough compared to the current density at the bottom of the feature such that the feature opening closes before the feature is fully filled. Further, in the early stages of the immersion process, i.e., when the substrate first contacts the plating solution, very high current densities have been detected across the wet area of the substrate. These initially high current densities can introduce extremely undesirable effects, such as surface defects, gas bubbles and non-uniform conditions across the surface of the substrate. Further, as the surface of the substrate is immersed in the tilting motion under the constant load bias, the conductive area of the substrate being immersed is changing (increasing), and therefore, the resistance of the conductive path is also changing (decreasing). As a result of the changes in the current path during the immersion process, the current density applied across the surface of the substrate varies through the immersion process. Although the immersion process may only take a few seconds, the uniformity of the initial electrodeposit may be affected by the varying current density applied across the surface of the seed layer, and therefore, the uniformity of layers subsequently plated over the seed layer may also be affected.
  • Therefore, a need exists in the art for an improved method for controlling the current density on the substrate during immersion.
  • SUMMARY OF THE INVENTION
  • One or more embodiments of the present invention are generally directed to a method for immersing a substrate into a plating solution. The method includes applying a first waveform to the substrate as the substrate is being immersed into the plating solution, stopping the application of the first waveform to the substrate as soon as the substrate is fully immersed inside the plating solution, and applying a second waveform to the substrate prior to the substrate being situated into a plating position.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
  • FIG. 1 illustrates a plating cell that may be used in connection with one or more embodiments of the invention.
  • FIG. 2 illustrates a sectional view of the plating cell and a head assembly during an immersion process.
  • FIG. 3 illustrates a time diagram of an immersion process in connection with one or more embodiments of the invention.
  • FIG. 4 illustrates a flow diagram of a method for immersing a substrate into a plating solution in accordance with one or more embodiments of the invention.
  • FIG. 5 illustrates the total current supplied to a substrate in accordance with an embodiment of the invention as compared to prior art.
  • DETAILED DESCRIPTION
  • FIG. 1 illustrates an exemplary plating cell 100 that may be used in connection with one or more embodiments of the invention. The plating cell 100 generally includes an outer basin 101 and an inner basin 102 positioned within outer basin 101. Inner basin 102 is generally configured to contain a plating solution that is used to plate a metal, e.g., copper, onto a substrate during an electrochemical plating process. During the plating process, the plating solution is generally continuously supplied to inner basin 102, and therefore, the plating solution continually overflows the uppermost point (generally termed a “weir”) of inner basin 102 and is collected by outer basin 101 and drained therefrom for chemical management and recirculation. Plating cell 100 may be generally positioned at a tilt angle, i.e., the frame portion 103 of plating cell 100 may generally be elevated on one side such that the components of plating cell 100 are tilted between about 3° and about 30°, or generally between about 4° and about 10° for optimal results. The frame member 103 of plating cell 100 supports an annular base member on an upper portion thereof. Since frame member 103 is elevated on one side, the upper generally planar surface of base member 104 is generally tilted from the horizontal at an angle that corresponds to the tilt angle of frame member 103 relative to a horizontal position. Base member 104 includes an annular or disk shaped recess formed into a central portion thereof, the annular recess being configured to receive a disk shaped anode member 105. Base member 104 further includes a plurality of fluid inlets/drains 109 extending from a lower surface thereof. Each of the fluid inlets/drains 109 are generally configured to individually supply or drain a fluid to or from either the anode compartment or the cathode compartment of plating cell 100. Anode member 105 generally includes a plurality of slots 107 formed therethrough, wherein the slots 107 are generally positioned in parallel orientation with each other across the surface of the anode 105. The parallel orientation allows for dense fluids generated at the anode surface to flow downwardly across the anode surface and into one of the slots 107.
  • Plating cell 100 may further include a membrane support assembly 106. Membrane support assembly 106 is generally secured at an outer periphery thereof to base member 104, and includes an interior region configured to allow fluids to pass therethrough. A membrane 108, which is generally an ionic membrane configured to selectively allow transmission of ions therethrough, is stretched across a lower surface of the support 206 and operates to fluidly separate a catholyte chamber and anolyte chamber portions of the plating cell. The membrane support assembly 106 may include an o-ring type seal positioned near a perimeter of the membrane, wherein the seal is configured to prevent fluids from traveling from one side of the membrane 108 secured on the membrane support 106 to the other side of the membrane 108. A diffusion plate 110, which is generally a porous ceramic disk member is configured to generate a substantially laminar flow or even flow of fluid in the direction of the substrate being plated, may optionally be positioned in the cell between membrane 108 and the substrate being plated. A more detailed description of the plating cell 100 may be found in commonly assigned U.S. patent application Ser. No. 10/781,040, which was filed on Feb. 18, 2004 under the title “METHOD FOR IMMERSING A SUBSTRATE”, claiming priority to U.S. Provisional Application Ser. No. 60/448,575, which was filed on Feb. 18, 2003, both of which are incorporated herein by reference in their entireties to the extent that these applications are not inconsistent with the present invention. Although one or more embodiments are described with referenced to a tilted plating cell, such as plating cell 100, other embodiments may be implemented in other types of plating cells, such as one described in commonly assigned U.S. patent application Ser. No. 10/135,546, which was filed on Apr. 29, 2002 under the title “APPARATUS AND METHOD FOR REGULATING THE ELECTRICAL POWER APPLIED TO A SUBSTRATE DURING IMMERSION,” which is incorporated herein by reference.
  • FIG. 2 illustrates an exemplary head assembly 200 used in connection with the plating cell 100. The head assembly 200 may include a contact ring 202 and a thrust plate assembly 204. A more detailed description of the contact ring 202 and thrust plate assembly 204 may be found in commonly assigned U.S. patent application Ser. No. 10/278,527, which was filed on Oct. 22, 2002 under the title “PLATING UNIFORMITY CONTROL BY CONTACT RING SHAPING”, and commonly assigned U.S. Pat. No. 6,251,236 entitled “CATHODE CONTACT RING FOR ELECTROCHEMICAL DEPOSITION,” both of which are hereby incorporated by reference in their entirety to the extent not inconsistent with the present invention.
  • The substrate may be secured to the contact ring 202, and the lower portion of the head assembly 200, i.e., the combination of the contact ring 202 and the thrust plate assembly 204, may be positioned at a tilt angle. The lower portion of head assembly 200 and the plating surface of the substrate positioned on the contact ring 202 may be tilted to the tilt angle as a result of the movement of head assembly 200. The tilt angle is defined as the angle between horizontal and the plating surface/production surface of the substrate secured to the contact ring 202. The tilt angle is generally between about 3° and about 30°, and more particularly, between about 3° and about 10°. Further, pivot point 208 may be positioned such that when the head assembly is tilted, a central vertical axis of the substrate remains in substantially the same location as when the substrate was positioned horizontally, i.e., the pivot point 208 may be positioned proximate contact ring 202.
  • Once the head assembly 200 is tilted, it may be actuated in the Z-direction to begin the immersion process. As the head assembly 200 is moved toward plating cell 100, the lower side of contact ring 202 contacts the plating solution as the head assembly 200 is actuated toward plating cell 100. The process of actuating head assembly 200 toward plating cell 100 may further include imparting rotational movement to contact ring 202. Thus, during the initial stages of the immersion process, contact ring 202 may be actuated in a vertical or Z-direction, while also being rotated about a central axis that intersects the radial center of the substrate, which is also generally orthogonal to the substrate surface.
  • As the substrate becomes immersed in the plating solution contained within plating cell 100, the Z-motion of head assembly 200 may be slowed and/or terminated and the tilt position of contact ring 202 may be returned to horizontal. This process generates a unique movement that includes both vertical actuation and tilt angle actuation, which has been shown to reduce bubble formation and adherence to the substrate surface during the immersion process. Further, the vertical and pivotal actuation of the substrate during immersion process may also include rotational movement of contact ring 202, which has been shown to further minimize bubble formation and adherence to the substrate surface during the immersion process.
  • Once the substrate is completely immersed into the plating solution contained within the plating cell 100, the head assembly 200 may further be actuated in a vertical direction (downward) and be pivoted about pivot point 208, to further immerse the substrate into the plating solution. Once the substrate is positioned deeper within the plating solution, the head assembly 200 may again be pivoted about pivot point 208, so the substrate surface may be positioned in parallel relationship to the upper surface of the anode 105. These various processes may also include rotating the substrate, which operates to dislodge any bubbles formed during the immersion process from the substrate surface.
  • FIG. 3 illustrates a time diagram 300 of an immersion process in connection with one or more embodiments of the invention. Stage 310 refers to a time period during which the substrate is immersed into the plating solution. The time period covered by stage 310 spans from when the substrate first contacts the plating solution to when the substrate is fully immersed. In one embodiment, stage 310 lasts from about 0.10 seconds to about 1.0 second. Stage 320 refers to a time period from the moment the substrate is fully immersed to the moment the substrate is situated in a plating position. In one embodiment, stage 320 lasts from about 1 second to about 5 seconds. Stage 330 refers to a time period during which the substrate is in a plating position. The plating position is defined as the position during which a conventional plating waveform is applied to completely fill the largest features on the substrate and overplate the substrate to a final total thickness.
  • FIG. 4 illustrates a flow diagram of a method 400 for immersing a substrate into a plating solution in accordance with one or more embodiments of the invention. At step 410, a first waveform is applied to the substrate as the substrate is immersed into the plating solution. A waveform is a sequence of voltages or currents designed to control the current density on the substrate surface. The waveform may comprise a constant voltage or current, a series of voltage or current steps, a gradually or periodically varying voltage or current, a pulsed voltage or current, or any combination of the above. When the waveform involves applying a voltage, the voltage may be applied to the entire cell or to the substrate relative to a reference electrode 250 disposed inside the plating solution, as shown in FIG. 2. The waveforms discussed herein may be implemented in several ways. These ways include varying the voltage or current under recipe control, in response to a substrate position sensor, or in response to a direct measure of voltage or current passing through the cell. Recipe control is defined as applying a waveform in which the voltage or current are varied in time in a predetermined manner based on the expected trajectory of the substrate. As such, recipe control is distinct from schemes where the applied voltage or current vary in response to a sensor that actively detects the position, voltage, or current on the substrate in real time. Recipe control may be necessary for certain advanced processes where the time period over which the voltage or current must be varied is so short such that there is insufficient time to send the sensor signal, communicate it to the control system such as a computer, and analyze it before applying the next voltage or current. A typical implementation of recipe control involves performing a number of experiments or calculations to identify the desired duration for each voltage or current to be applied. Once known, these voltages and currents constitute a predetermined waveform that can be applied thereafter every time a substrate is processed.
  • In view of FIG. 3, step 410 occurs during stage 310. As such, the time period during which the first waveform is applied may last from the moment the substrate first contacts the plating solution to the moment the substrate is fully immersed. That time period may last from about 0.10 seconds to about 1.0 second. In one embodiment, the first waveform includes a constant voltage. Surprisingly, the first waveform may include a voltage such that the resulting current density on the substrate exceeds the threshold for pinch-off voids. This threshold is a predetermined current density that would lead to the formation of pinch-off voids if maintained throughout stages 310 and 320. The predetermined threshold required to create a pinch-off void is primarily a function of feature size; however, it may also be a function of plating solution chemistry and seed layer profile and thickness.
  • In yet another embodiment, the first waveform comprises a voltage that is ramped, i.e., increases over time. In still another embodiment, the first waveform comprises a sequence of voltages that increases over time. In still yet another embodiment, the first waveform comprises a voltage that is stepped or multistepped, i.e., includes two or more constant voltages, wherein each successive voltage is different from the previous voltage. In such embodiments, application of the first waveform is configured to ensure that the feature filling process occurs at all points on the substrate within a suitable current density window and to facilitate uniform deposition of metal ions across the substrate. Although the first waveform has been described as being voltage controlled, other embodiments of the invention contemplate the first waveform as being current controlled.
  • In yet another embodiment, applying the first waveform includes applying a first voltage to the substrate as the substrate first contacts the plating solution, stopping the application of the first constant voltage to the substrate after a predetermined period of time (or after a predetermined amount of current supplied to the substrate is reached), and supplying a first current to the substrate from the moment the predetermined period of time ends (or from the moment the predetermined amount of current is reached) to the moment the substrate is completely immersed. When the substrate first contacts the plating solution, there is a short period of time during which the plating solution climbs up the substrate surface due to capillary forces, thereby creating a wicking effect. This wicking effect may cause a high current density on the wet area of the substrate since the wet area is small and the cell resistance is low. Accordingly, the first constant voltage may be configured to take into account this wicking effect. As the substrate is being immersed into the plating solution, the fluid dynamics of the wet area of the substrate changes. As such, the first current is configured to take into account the fluid dynamics changes in vertical velocity, swing motion and rotation of the substrate and capillary forces of the plating solution. Further, the first constant voltage and the first current may each be a function of seed layer thickness, feature size, plating solution concentration, substrate size and plating cell geometry/design.
  • Referring now to step 420, once the substrate is fully immersed, application of the first waveform is stopped and a second waveform is applied to the substrate from the time the substrate is fully immersed to the time the substrate is situated into a plating position. In one embodiment, step 420 occurs during stage 320. As such, the time period during which the second waveform is applied lasts from the moment the substrate is fully immersed to the moment the substrate is situated in a plating position. The second waveform may be applied for about 1 second to about 5 seconds. In this manner, the first and second waveforms are applied to the substrate prior to the substrate being situated in the plating position. However, the second waveform may also continue to be applied to the substrate for a predetermined period of time after the substrate is situated in the plating position (stage 330).
  • In one embodiment, the second waveform includes a constant current. In another embodiment, the second waveform includes a current less than a predetermined threshold configured to perform a bottom-up fill. The predetermined threshold required to initiate a bottom-up fill is typically a function of feature size, plating solution chemistry and seed layer thickness. A bottom-up fill refers to a higher rate of deposition at the bottom of a feature than at the sidewalls. In such an embodiment, application of the second waveform may be configured to grow and thicken a conformal metal layer on the seed layer prior to filling the features or prior to a bottom-up fill.
  • In another embodiment, the second waveform includes a current that starts from below about a predetermined threshold configured to perform a bottom-up fill and increases as the thickness of a layer of deposit from the plating solution to the substrate increases. In such an embodiment, in addition to growing and thickening a conformal metal layer on the seed layer prior to filling the features or prior to a bottom-up fill, application of the second waveform may be configured to ensure that the feature filling process occurs at all points on the substrate within a suitable current density window and to facilitate uniform deposition of metal ions across the substrate.
  • In yet another embodiment, step 420 may include application of a pulsed voltage or current prior to the application of the various embodiments of second waveform described above. The pulsed voltage or current may be greater than a predetermined threshold configured to create a pinch-off void inside a feature. In such an embodiment, the pulsed voltage or current may be configured to enhance or attract metal ions contained inside the plating solution to portions of the substrate where the seed layer coverage is thin, patchy or completely absent.
  • Once the substrate is situated in the plating position, a plating waveform is applied to the substrate (step 430). The plating waveform is defined as a waveform designed to complete the filling of the largest features on the substrate and overplate the substrate to the desired final thickness of the deposit. For example, a plating waveform may consist of a sequence of one or more constant current steps. In one embodiment, application of the second waveform is stopped before the substrate is situated in the plating position and the plating waveform is applied to the substrate while the substrate is still being situated into the plating position. In another embodiment, the second waveform continues to be applied to the substrate for a predetermined period of time while the substrate is in the plating position before the plating waveform is applied.
  • A specific example is described below to further illustrate the invention. During stage 310, a first waveform having a constant cell voltage of 2 V, which corresponds to a current density of 5 mA/cm2 on a fully immersed substrate, is applied for about 0.7 sec. During stage 320, a second waveform having a constant current equivalent to 3 mA/cm2 is applied for about 1 to 4 seconds. This is followed by a typical plating waveform which is a sequence of three constant-current steps beginning at the end of stage 320. An example of the plating waveform includes depositing 500 Å at a current density of 5 mA/cm2, followed by depositing 1000 Å at a current density of 10 mA/cm2, and followed by depositing 8500 Å at a current density of 40 mA/cm2. The above example applies to the case of a 300 mm wafer with a 500 Å seed layer, trench features that are 55 nm wide and 150 nm deep, and via features that are 80 nm in diameter and 360 nm deep. The plating bath used contained 40 g/L copper, 10 g/L acid, 50 ppm chloride, and optimized concentrations of plating additives such as the Enthone Viaform accelerator, suppressor, and leveler. For comparison, an example of the prior art may include applying a cell voltage of 2 V for the duration of stages 310 and 320, then applying a typical plating waveform from the end of stage 320. An example of the invention in view of a prior art example is illustrated in FIG. 5, which shows the total current supplied to the substrate as a result of the applied waveforms. While the prior art example is suitable for larger feature sizes, it often leads to significant pinch-off voids for the feature sizes mentioned above.
  • While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (24)

  1. 1. A method for immersing a substrate into a plating solution, comprising:
    applying a first waveform to the substrate as the substrate is being immersed into the plating solution;
    stopping the application of the first waveform to the substrate as soon as the substrate is fully immersed inside the plating solution; and
    applying a second waveform to the substrate prior to the substrate being situated into a plating position.
  2. 2. The method of claim 1, further comprising:
    stopping the application of the second waveform once the substrate is situated in the plating position; and
    applying a plating waveform to the substrate.
  3. 3. The method of claim 1, wherein the first waveform comprises a constant voltage.
  4. 4. The method of claim 1, wherein the first waveform comprises a voltage greater than a predetermined threshold for creating a pinch-off void inside a feature.
  5. 5. The method of claim 1, wherein the first waveform comprises a voltage that increases over time.
  6. 6. The method of claim 1, wherein the first waveform comprises a sequence of voltages that increases over time.
  7. 7. The method of claim 1, wherein the first waveform comprises a first constant voltage and a second constant voltage higher than the first constant voltage.
  8. 8. The method of claim 1, wherein applying the first waveform comprises:
    applying a first constant voltage to the substrate as the substrate first contacts the plating solution;
    stopping the application of the first constant voltage to the substrate after a predetermined period of time and prior to the substrate being fully immersed in the plating solution; and
    supplying a current to the substrate from the moment the predetermined period of time ends to the moment the substrate is completely immersed.
  9. 9. The method of claim 8, wherein the predetermined period of time is from about 0.10 seconds to about 1.0 second.
  10. 10. The method of claim 1, wherein applying the first waveform comprises:
    applying a first constant voltage to the substrate as the substrate first contacts the plating solution;
    stopping the application of the first constant voltage to the substrate after a predetermined current supplied to the substrate is reached; and
    supplying a current to the substrate from the moment the predetermined current supplied to the substrate is reached to the moment the substrate is completely immersed.
  11. 11. The method of claim 1, wherein the first waveform is applied to the substrate from about 0.10 seconds to about 1.0 second.
  12. 12. The method of claim 1, wherein the second waveform comprises a constant current.
  13. 13. The method of claim 1, wherein the second waveform comprises a current less than a predetermined threshold for performing a bottom-up fill.
  14. 14. The method of claim 4, wherein the second waveform comprises a current less than a predetermined threshold for performing a bottom-up fill.
  15. 15. The method of claim 1, further comprising stopping the application of the second waveform before the substrate is situated in the plating position; and applying a plating waveform to the substrate while the substrate is still being situated into the plating position.
  16. 16. The method of claim 4, further comprising stopping the application of the second waveform before the substrate is situated in the plating position; and applying a plating waveform to the substrate while the substrate is still being situated into the plating position.
  17. 17. The method of claim 13, further comprising stopping the application of the second waveform before the substrate is situated in the plating position; and applying a plating waveform to the substrate while the substrate is still being situated into the plating position.
  18. 18. The method of claim 1, wherein the second waveform comprises a current that starts from below a predetermined threshold for performing a bottom-up fill and increases as the thickness of a layer of deposit from the plating solution to the substrate increases.
  19. 19. The method of claim 4, wherein the second waveform comprises a current that starts from below a predetermined threshold for performing a bottom-up fill and increases as the thickness of a layer of deposit from the plating solution to the substrate increases.
  20. 20. The method of claim 18, further comprising stopping the application of the second waveform before the substrate is situated in the plating position; and applying a plating waveform to the substrate while the substrate is still being situated into the plating position.
  21. 21. The method of claim 1, wherein the second waveform comprises a pulsed current or a pulsed voltage.
  22. 22. The method of claim 4, wherein the second waveform comprises a pulsed current or a pulsed voltage.
  23. 23. The method of claim 1, wherein the first waveform and the second waveform are applied under recipe control.
  24. 24. The method of claim 1, further comprising immersing the substrate at an angle.
US11052443 2005-02-07 2005-02-07 Immersion process for electroplating applications Abandoned US20060175201A1 (en)

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US11052443 US20060175201A1 (en) 2005-02-07 2005-02-07 Immersion process for electroplating applications
PCT/US2006/003025 WO2006086169A3 (en) 2005-02-07 2006-01-31 Immersion process for electroplating applications

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