JP2004063540A - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP2004063540A
JP2004063540A JP2002216310A JP2002216310A JP2004063540A JP 2004063540 A JP2004063540 A JP 2004063540A JP 2002216310 A JP2002216310 A JP 2002216310A JP 2002216310 A JP2002216310 A JP 2002216310A JP 2004063540 A JP2004063540 A JP 2004063540A
Authority
JP
Japan
Prior art keywords
pad
insulating film
semiconductor device
double structure
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002216310A
Other languages
English (en)
Inventor
Masao Nakahira
中平　政男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Priority to JP2002216310A priority Critical patent/JP2004063540A/ja
Priority to US10/622,728 priority patent/US6762499B2/en
Priority to TW092119948A priority patent/TWI228815B/zh
Priority to KR10-2003-0051270A priority patent/KR100529199B1/ko
Publication of JP2004063540A publication Critical patent/JP2004063540A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

【課題】パッド下に回路が存在するレイアウト構造において、ワイヤのボンディング性を損なうことなく、ウェハテスト時のパッド下回路へのダメージを減らすことのできる半導体装置を提供することにある。
【解決手段】半導体基板４上にＩ／Ｏバッファ回路パターン２を形成し、層間絶縁膜にＩ／Ｏバッファ回路パターンとパッドを接続するためのスルーホール１０を形成し、第ｎ番目の金属配線層にて２重構造の１重目のパッド８を形成する。さらに絶縁膜９を積層し、２重構造の上下パッドを接続するスルーホール１１を形成し、第ｎ＋１番目の金属配線層で２重構造パッドの２重目１と１重構造パッド３および両者を接続する配線１２を構成する。
【選択図】　　　図１

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置に関し、特にワイヤのボンディング性を損なうことなく、ウェハテスト時のパッド下回路へのダメージを減らし、パッド下回路のクラック発生率を低減させることのできる半導体装置に関する。
【０００２】
【従来の技術】
従来、この種の半導体装置は、特に大規模ＬＳＩの場合は図２に示すようにＩ／Ｏバッファ上２に、メタル２重構造のパッド１を配置している、この配置を取った場合にウェハテストおよびワイヤボンディングを行うと、パッド下回路へのダメージが大きくなり、ダメージを回避するためにメタル１重構造にするとパッドが剥がれやすくなるためにボンディング性の低下を招いてしまうため、これらを回避する手段を講ずる必要がある。
【０００３】
【発明が解決しようとする課題】
上述した従来の半導体装置においては、Ｉ／Ｏバッファ５上に、メタル２重構造のパッド１を配置し、ウェハテストおよびワイヤボンディングを行うと、パッド下の回路パターンへのダメージが大きくなり、ダメージを回避するためにメタル１重構造にするとボンディング性の低下を招いてしまうという欠点がある。
【０００４】
したがって、本発明の目的はパッド下に回路が存在するレイアウト構造（Ｃｉｒｃｕｉｔ　Ｕｎｄｅｒ　Ｐａｄ、以下ＣＵＰ）において、ワイヤのボンディング性を損なうことなく、ウェハテスト時のパッド下回路へのダメージを減らし、パッド下回路のクラック発生率を低減させることのできる半導体装置を提供することにある。
【０００５】
【課題を解決するための手段】
本発明の半導体装置は、半導体基板上に回路パターンならびに必要な配線層および層間絶縁膜を形成し、その上に第１の絶縁膜を積層し、この絶縁膜に回路パターンとパッドを接続するためのスルーホールを形成し、次に前記第１の絶縁膜上に第１の金属配線層を形成し、この金属配線層に２重構造の１重目のパッドを形成する。さらに第２の絶縁膜を積層し、この第２の絶縁膜に２重構造の上下パッドを接続するスルーホールを形成し、さらに前記第２の絶縁膜上に第２の金属配線層を形成し、この第２の金属層に２重構造パッドの２重目と１重構造パッドおよび両者を接続する金属配線を構成することを特徴としている。
【０００６】
【発明の実施の形態】
次に、本発明について図面を参照して説明する。図１は本発明の実施形態の構成を示す平面および断面図である。図１に示されるように、本実施形態は、半導体基板４上にＩ／Ｏバッファ回路２のパターンを形成し、その後半導体装置の内部回路に必要なｎ−１層の金属配線層６までの金属配線パターンとそれらの上部に第１の絶縁膜７を形成し、ここまでの絶縁膜にＩ／Ｏバッファ回路２のパターンとパッドを接続するためのスルーホール１０を形成し、第ｎ番目の金属配線層にて２重構造の１重目のパッド８を形成する。さらに第２の絶縁膜９を積層し、２重構造の上下パッドを接続する上部パッドの接着強度を増加するため複数のスルーホール１１を形成し、工程削減のため第ｎ＋１番目の金属配線層で２重構造パッドの２重目１と１重構造パッド３および両者を接続する配線１２を構成する。また前記絶縁膜を窒化膜で構成することも強度的に効果をあげることができる。
【０００７】
次にこの半導体装置のパッドの使用方法について説明する。ウェハテスト時メタル１重構造のパッド３を使用し、ワイヤボンディング時メタル２重構造のパッド１を使用する。メタル１重構造のパッド３をウェハテスト時に使用することで、テスト時にパッド下回路に与えるダメージを低減し、メタル２重構造のパッド１をワイヤボンディング時に使用することで、強度を上げたボンディング性を確保できる。
【０００８】
【発明の効果】
以上説明したように、本発明は、メタル１重構造のパッド３をウェハテスト時に使用することで、テスト時にパッド下の回路パターンに与えるダメージを低減し、メタル２重構造のパッド１をワイヤボンディング時に使用することで、従来と同等のボンディング性を確保できる。
【図面の簡単な説明】
【図１】本発明の実施形態の構成を示す断面ならびに平面図である。
【図２】従来例を示す断面ならびに平面図である。
【符号の説明】
１　　メタル２重構造のパッド
２　　Ｉ／Ｏバッファ回路
３　　メタル１重構造のパッド
４　　半導体基板
５　　層間絶縁膜
６　　金属配線層
７　　第１の絶縁膜
８　　２重構造の１重目のパッド
９　　第２の絶縁膜
１０　　スルーホール
１１　　スルーホール
１２　　配線

Claims (6)

  1. 半導体基板上に形成され必要な加工を施された配線層および層間絶縁膜と、
    その上に形成した第１の絶縁膜と、
    前記第１の絶縁膜上に形成された２重構造の１重目のパッドと、
    前記第１の絶縁膜および２重構造の１重目のパッド上に積層された第２の絶縁膜と、
    この第２の絶縁膜に形成された２重構造の上下パッドを接続するスルーホールと、
    さらに前記第２の絶縁膜上に形成された前記２重構造パッドの２重目と１重構造パッドと、を含むことを特徴とする半導体装置。
  2. 前記１重構造および前記２重構造のパッド下に回路パターンが存在する請求項１記載の半導体装置。
  3. 前記回路パターンがＩ／Ｏバッファであることを特徴とする請求項１記載の半導体装置。
  4. 前記２重構造の上下間の導通を複数のスルーホールで結合したことを特徴とする請求項１乃至３記載の半導体装置。
  5. 前記第１の絶縁膜および前記第２の絶縁膜の両方或いは一方が窒化膜で構成されることを特徴とする請求項１乃至４記載の半導体装置。
  6. 前記１重構造のパッドと前記２重構造のパッドの上層が同一層の配線で結合されることを特徴とする請求項１乃至５記載の半導体装置。
JP2002216310A 2002-07-25 2002-07-25 半導体装置 Pending JP2004063540A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2002216310A JP2004063540A (ja) 2002-07-25 2002-07-25 半導体装置
US10/622,728 US6762499B2 (en) 2002-07-25 2003-07-21 Semiconductor integrated device
TW092119948A TWI228815B (en) 2002-07-25 2003-07-22 Semiconductor integrated device
KR10-2003-0051270A KR100529199B1 (ko) 2002-07-25 2003-07-25 반도체 집적 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002216310A JP2004063540A (ja) 2002-07-25 2002-07-25 半導体装置

Publications (1)

Publication Number Publication Date
JP2004063540A true JP2004063540A (ja) 2004-02-26

Family

ID=30767950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002216310A Pending JP2004063540A (ja) 2002-07-25 2002-07-25 半導体装置

Country Status (4)

Country Link
US (1) US6762499B2 (ja)
JP (1) JP2004063540A (ja)
KR (1) KR100529199B1 (ja)
TW (1) TWI228815B (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8174123B2 (en) 2008-12-24 2012-05-08 Renesas Electronics Corporation Semiconductor integrated circuit

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7629689B2 (en) * 2004-01-22 2009-12-08 Kawasaki Microelectronics, Inc. Semiconductor integrated circuit having connection pads over active elements
US7808115B2 (en) * 2004-05-03 2010-10-05 Broadcom Corporation Test circuit under pad
US20070111376A1 (en) 2005-04-29 2007-05-17 Stats Chippac Ltd. Integrated circuit package system
TWI288464B (en) * 2005-11-25 2007-10-11 Richtek Technology Corp Circuit under pad and method of forming a pad
FR2904472B1 (fr) * 2006-07-28 2008-10-31 Microcomposants De Haute Secur Procede de fabrication d'un circuit integre encapsule et circuit integre encapsule associe
US8614508B2 (en) * 2011-09-21 2013-12-24 Stats Chippac Ltd. Integrated circuit system with test pads and method of manufacture thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW416575U (en) * 1998-06-03 2000-12-21 United Integrated Circuits Corp Bonding pad structure
JP2974022B1 (ja) * 1998-10-01 1999-11-08 ヤマハ株式会社 半導体装置のボンディングパッド構造
JP4443005B2 (ja) 1999-08-09 2010-03-31 日本クラウンコルク株式会社 ワンピースプラスチックキャップ
JP2001358169A (ja) 2000-06-15 2001-12-26 Nec Corp 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8174123B2 (en) 2008-12-24 2012-05-08 Renesas Electronics Corporation Semiconductor integrated circuit

Also Published As

Publication number Publication date
KR20040010384A (ko) 2004-01-31
US20040016980A1 (en) 2004-01-29
TW200402861A (en) 2004-02-16
US6762499B2 (en) 2004-07-13
TWI228815B (en) 2005-03-01
KR100529199B1 (ko) 2005-11-17

Similar Documents

Publication Publication Date Title
JP2005527968A5 (ja)
JP5266720B2 (ja) 半導体装置
JP2010171386A (ja) 半導体装置及びその製造方法
JP2005236277A (ja) 半導体集積回路
JP3898350B2 (ja) 半導体装置
US8101470B2 (en) Foil based semiconductor package
JP2004063540A (ja) 半導体装置
JP2001358169A (ja) 半導体装置
JP2010147267A (ja) 半導体集積回路装置および半導体集積回路装置の製造方法
TW200843063A (en) Structure of semiconductor chip and package structure having semiconductor chip embedded therein
JP4021376B2 (ja) パッド構造
KR20100064602A (ko) 미로 같은 크랙 스토퍼 구조물을 갖는 반도체 및 제조 방법
JP3915670B2 (ja) 半導体装置およびその製造方法
KR100709443B1 (ko) 반도체 소자의 본딩 패드 형성방법
JP2008066440A (ja) 半導体装置およびその製造方法
JP2001135795A (ja) 半導体装置
KR100874430B1 (ko) 반도체 소자 및 그 제조 방법
JP2005268395A (ja) 半導体装置
JP2004363340A (ja) 半導体装置およびその製造方法
TW587317B (en) Construction and manufacturing of a chip package
JP2001007113A (ja) 半導体装置
JPH05183007A (ja) 半導体基板等のパッド構造
JP2004018964A5 (ja)
JP2011146521A (ja) 半導体装置
KR101133499B1 (ko) 반도체 장치 및 그 제조방법

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050615

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060426

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060509

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060607

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060627

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060704

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060801

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060920

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20070703

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070724