JP2003511003A - 集積回路に使用されるキャパシタの端子間のストレスを軽減するための方法および装置 - Google Patents

集積回路に使用されるキャパシタの端子間のストレスを軽減するための方法および装置

Info

Publication number
JP2003511003A
JP2003511003A JP2001527423A JP2001527423A JP2003511003A JP 2003511003 A JP2003511003 A JP 2003511003A JP 2001527423 A JP2001527423 A JP 2001527423A JP 2001527423 A JP2001527423 A JP 2001527423A JP 2003511003 A JP2003511003 A JP 2003511003A
Authority
JP
Japan
Prior art keywords
capacitor
node
voltage
capacitors
power state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2001527423A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003511003A5 (enExample
Inventor
ガネサン，ランカーシク
ジュングロース，オーウェン・ダブリュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JP2003511003A publication Critical patent/JP2003511003A/ja
Publication of JP2003511003A5 publication Critical patent/JP2003511003A5/ja
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2001527423A 1999-09-27 2000-07-18 集積回路に使用されるキャパシタの端子間のストレスを軽減するための方法および装置 Ceased JP2003511003A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/405,977 US6297974B1 (en) 1999-09-27 1999-09-27 Method and apparatus for reducing stress across capacitors used in integrated circuits
US09/405,977 1999-09-27
PCT/US2000/019623 WO2001024348A1 (en) 1999-09-27 2000-07-18 Method and apparatus for reducing stress across capacitors used in integrated circuits

Publications (2)

Publication Number Publication Date
JP2003511003A true JP2003511003A (ja) 2003-03-18
JP2003511003A5 JP2003511003A5 (enExample) 2007-08-16

Family

ID=23606020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001527423A Ceased JP2003511003A (ja) 1999-09-27 2000-07-18 集積回路に使用されるキャパシタの端子間のストレスを軽減するための方法および装置

Country Status (7)

Country Link
US (2) US6297974B1 (enExample)
JP (1) JP2003511003A (enExample)
KR (1) KR100438371B1 (enExample)
CN (1) CN1187884C (enExample)
AU (1) AU6109300A (enExample)
TW (1) TW473786B (enExample)
WO (1) WO2001024348A1 (enExample)

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US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
US7184313B2 (en) 2005-06-17 2007-02-27 Saifun Semiconductors Ltd. Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
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US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
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Publication number Priority date Publication date Assignee Title
CN117665498A (zh) * 2022-08-30 2024-03-08 瑞昱半导体股份有限公司 用于模拟电子元件的击穿的方法以及设备

Also Published As

Publication number Publication date
USRE41217E1 (en) 2010-04-13
AU6109300A (en) 2001-04-30
CN1187884C (zh) 2005-02-02
WO2001024348A1 (en) 2001-04-05
US6297974B1 (en) 2001-10-02
KR20020038773A (ko) 2002-05-23
CN1399811A (zh) 2003-02-26
KR100438371B1 (ko) 2004-07-02
TW473786B (en) 2002-01-21

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