WO2001024348A1 - Method and apparatus for reducing stress across capacitors used in integrated circuits - Google Patents

Method and apparatus for reducing stress across capacitors used in integrated circuits Download PDF

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Publication number
WO2001024348A1
WO2001024348A1 PCT/US2000/019623 US0019623W WO0124348A1 WO 2001024348 A1 WO2001024348 A1 WO 2001024348A1 US 0019623 W US0019623 W US 0019623W WO 0124348 A1 WO0124348 A1 WO 0124348A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
capacitor
voltage
capacitors
power state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/019623
Other languages
English (en)
French (fr)
Inventor
Ramkarthik Ganesan
Owen W. Jungroth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to AU61093/00A priority Critical patent/AU6109300A/en
Priority to JP2001527423A priority patent/JP2003511003A/ja
Publication of WO2001024348A1 publication Critical patent/WO2001024348A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type

Definitions

  • V the voltage across Cl (between node 1 and the middle node M)
  • VI the voltage across C2 (between the middle node M and ground level)
  • V2 the voltage across C2 (between the middle node M and ground level)
  • Figure 3 illustrates a stacked capacitor configuration with a voltage control mechanism to overcome the transient stress problem described above.
  • the middle node M between capacitor Cl and capacitor C2 is coupled to a control device 311 that is connected to a voltage source Vinit.
  • the control device 311 operates as a switch and is switched on or off based upon an input control signal 321.
  • the input control signal 321 is set to a first value when the circuit is in a first power state (e.g., a low power state) and set to a second value when the circuit is in a second power state (e.g., a high power state).
  • both the NWELL and the DINITPCW are set to ground level to turn off the control transistors 643 and 645 thus disconnecting or isolating the intermediate nodes INIT1 and INIT2 from the voltage DINITPCW
  • the NWELL and the DINITPCW are set to a positive voltage level causing the control transistors 643 and 645 to turn on thus connecting the intermediate nodes INIT1 and INIT2 to the DINITPCW voltage
  • the DINITPCW is set to the same voltage level as the output node 691 when the charge pump circuit is shut down By controlling the voltage level at the intermediate nodes INIT1 and INIT2 through the control transistors 643 and 645, the transient stress problem that would occur when the charge pump circuit transitions from one state (e g , running) to another state (e g , shut down) is solved
  • the output node of at least the final stage in the charge pump circuit can go from a negative voltage level (e.g., -15 volts) when the charge pump circuit is running to a positive voltage level (e.g., +11 volts) when the charge pump circuit is shut down and then gets initialized to a proper voltage level, for example +5 volts.
  • a negative voltage level e.g., -15 volts
  • +11 volts e.g., +11 volts
  • the total voltage sweep or the transient stress is 26 volts which exceeds the stress limitation of the capacitors even in the stacked configuration.
  • the voltage level at the middle node between the two capacitors connected in series is dynamically controlled as described above.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Semiconductor Integrated Circuits (AREA)
PCT/US2000/019623 1999-09-27 2000-07-18 Method and apparatus for reducing stress across capacitors used in integrated circuits Ceased WO2001024348A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU61093/00A AU6109300A (en) 1999-09-27 2000-07-18 Method and apparatus for reducing stress across capacitors used in integrated circuits
JP2001527423A JP2003511003A (ja) 1999-09-27 2000-07-18 集積回路に使用されるキャパシタの端子間のストレスを軽減するための方法および装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/405,977 US6297974B1 (en) 1999-09-27 1999-09-27 Method and apparatus for reducing stress across capacitors used in integrated circuits
US09/405,977 1999-09-27

Publications (1)

Publication Number Publication Date
WO2001024348A1 true WO2001024348A1 (en) 2001-04-05

Family

ID=23606020

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/019623 Ceased WO2001024348A1 (en) 1999-09-27 2000-07-18 Method and apparatus for reducing stress across capacitors used in integrated circuits

Country Status (7)

Country Link
US (2) US6297974B1 (enExample)
JP (1) JP2003511003A (enExample)
KR (1) KR100438371B1 (enExample)
CN (1) CN1187884C (enExample)
AU (1) AU6109300A (enExample)
TW (1) TW473786B (enExample)
WO (1) WO2001024348A1 (enExample)

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US6791396B2 (en) * 2001-10-24 2004-09-14 Saifun Semiconductors Ltd. Stack element circuit
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
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US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7148739B2 (en) * 2002-12-19 2006-12-12 Saifun Semiconductors Ltd. Charge pump element with body effect cancellation for early charge pump stages
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US6842383B2 (en) 2003-01-30 2005-01-11 Saifun Semiconductors Ltd. Method and circuit for operating a memory cell using a single charge pump
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US6885244B2 (en) 2003-03-24 2005-04-26 Saifun Semiconductors Ltd. Operational amplifier with fast rise time
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US6906966B2 (en) 2003-06-16 2005-06-14 Saifun Semiconductors Ltd. Fast discharge for program and verification
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7050319B2 (en) * 2003-12-03 2006-05-23 Micron Technology, Inc. Memory architecture and method of manufacture and operation thereof
US7176728B2 (en) * 2004-02-10 2007-02-13 Saifun Semiconductors Ltd High voltage low power driver
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US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
US7184313B2 (en) 2005-06-17 2007-02-27 Saifun Semiconductors Ltd. Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
JP2007027760A (ja) 2005-07-18 2007-02-01 Saifun Semiconductors Ltd 高密度不揮発性メモリアレイ及び製造方法
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
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US8461909B2 (en) 2010-12-30 2013-06-11 Stmicroelectronics S.R.L. Voltage booster

Also Published As

Publication number Publication date
JP2003511003A (ja) 2003-03-18
KR20020038773A (ko) 2002-05-23
TW473786B (en) 2002-01-21
AU6109300A (en) 2001-04-30
CN1399811A (zh) 2003-02-26
KR100438371B1 (ko) 2004-07-02
CN1187884C (zh) 2005-02-02
US6297974B1 (en) 2001-10-02
USRE41217E1 (en) 2010-04-13

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