JP2003501800A - 窒化物スペーサーを用いて高密度のメモリセルおよび小さな間隔を作る方法 - Google Patents
窒化物スペーサーを用いて高密度のメモリセルおよび小さな間隔を作る方法Info
- Publication number
- JP2003501800A JP2003501800A JP2001500325A JP2001500325A JP2003501800A JP 2003501800 A JP2003501800 A JP 2003501800A JP 2001500325 A JP2001500325 A JP 2001500325A JP 2001500325 A JP2001500325 A JP 2001500325A JP 2003501800 A JP2003501800 A JP 2003501800A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- nitride
- arc
- dimension
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 2
- 150000004767 nitrides Chemical class 0.000 claims abstract description 68
- 238000000034 method Methods 0.000 claims abstract description 53
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 30
- 239000006117 anti-reflective coating Substances 0.000 claims description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 26
- 229920005591 polysilicon Polymers 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000000206 photolithography Methods 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000007667 floating Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 85
- 238000001459 lithography Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 101000900567 Pisum sativum Disease resistance response protein Pi49 Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000035620 dolor Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/320,417 US6329124B1 (en) | 1999-05-26 | 1999-05-26 | Method to produce high density memory cells and small spaces by using nitride spacer |
| US09/320,417 | 1999-05-26 | ||
| PCT/US2000/006585 WO2000074121A1 (en) | 1999-05-26 | 2000-03-13 | Method to produce high density memory cells and small spaces by using nitride spacer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003501800A true JP2003501800A (ja) | 2003-01-14 |
| JP2003501800A5 JP2003501800A5 (enExample) | 2007-04-05 |
Family
ID=23246336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001500325A Pending JP2003501800A (ja) | 1999-05-26 | 2000-03-13 | 窒化物スペーサーを用いて高密度のメモリセルおよび小さな間隔を作る方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6329124B1 (enExample) |
| EP (1) | EP1181714A1 (enExample) |
| JP (1) | JP2003501800A (enExample) |
| KR (1) | KR100682638B1 (enExample) |
| WO (1) | WO2000074121A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014112655A (ja) * | 2012-10-30 | 2014-06-19 | Dainippon Printing Co Ltd | ナノインプリントモールドおよびその製造方法 |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG102681A1 (en) | 2001-02-19 | 2004-03-26 | Semiconductor Energy Lab | Light emitting device and method of manufacturing the same |
| US20030064585A1 (en) * | 2001-09-28 | 2003-04-03 | Yider Wu | Manufacture of semiconductor device with spacing narrower than lithography limit |
| US6664191B1 (en) * | 2001-10-09 | 2003-12-16 | Advanced Micro Devices, Inc. | Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space |
| US6977203B2 (en) * | 2001-11-20 | 2005-12-20 | General Semiconductor, Inc. | Method of forming narrow trenches in semiconductor substrates |
| US7029958B2 (en) * | 2003-11-04 | 2006-04-18 | Advanced Micro Devices, Inc. | Self aligned damascene gate |
| CN100356513C (zh) * | 2003-11-19 | 2007-12-19 | 旺宏电子股份有限公司 | 具有缩小间距的半导体元件及其形成方法 |
| JP4016009B2 (ja) * | 2004-03-24 | 2007-12-05 | 株式会社東芝 | パターン形成方法及び半導体装置の製造方法 |
| US20070052133A1 (en) * | 2005-09-07 | 2007-03-08 | Michael Gostkowski | Methods for fabricating sub-resolution line space patterns |
| CN100426466C (zh) * | 2006-02-24 | 2008-10-15 | 晶豪科技股份有限公司 | 形成具有缩小的字线间距的快闪单元阵列的方法 |
| US7772048B2 (en) * | 2007-02-23 | 2010-08-10 | Freescale Semiconductor, Inc. | Forming semiconductor fins using a sacrificial fin |
| KR100914289B1 (ko) * | 2007-10-26 | 2009-08-27 | 주식회사 하이닉스반도체 | 스페이서를 이용한 반도체 메모리소자의 패턴 형성방법 |
| US20180323078A1 (en) * | 2015-12-24 | 2018-11-08 | Intel Corporation | Pitch division using directed self-assembly |
| US10566194B2 (en) * | 2018-05-07 | 2020-02-18 | Lam Research Corporation | Selective deposition of etch-stop layer for enhanced patterning |
| CN116153781A (zh) * | 2021-11-23 | 2023-05-23 | 上海华力集成电路制造有限公司 | 半导体鳍状结构截断工艺 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62150826A (ja) * | 1985-12-25 | 1987-07-04 | Toshiba Corp | 半導体装置の製造方法 |
| JPH04207076A (ja) * | 1990-11-30 | 1992-07-29 | Toshiba Corp | 固体撮像装置の製造方法 |
| JPH04291758A (ja) * | 1990-12-10 | 1992-10-15 | Samsung Electron Co Ltd | マスクプグラム方式の読出し専用メモリー装置の製造方法 |
| JPH06232095A (ja) * | 1993-01-29 | 1994-08-19 | Sony Corp | パターンの形成方法 |
| JPH0786244A (ja) * | 1993-09-13 | 1995-03-31 | Sony Corp | ドライエッチング方法 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4415383A (en) * | 1982-05-10 | 1983-11-15 | Northern Telecom Limited | Method of fabricating semiconductor devices using laser annealing |
| JPH02283039A (ja) | 1989-04-25 | 1990-11-20 | Toshiba Corp | 電荷転送装置と電荷転送装置の製造方法 |
| US5580384A (en) | 1989-09-22 | 1996-12-03 | Balzers Aktiengesellschaft | Method and apparatus for chemical coating on opposite surfaces of workpieces |
| WO1991006119A1 (fr) | 1989-10-20 | 1991-05-02 | Oki Electric Industry Co., Ltd. | Procede de fabrication des dispositifs a circuit integre a semi-conducteur |
| US5420067A (en) | 1990-09-28 | 1995-05-30 | The United States Of America As Represented By The Secretary Of The Navy | Method of fabricatring sub-half-micron trenches and holes |
| US5296410A (en) | 1992-12-16 | 1994-03-22 | Samsung Electronics Co., Ltd. | Method for separating fine patterns of a semiconductor device |
| KR100366910B1 (ko) * | 1994-04-05 | 2003-03-04 | 소니 가부시끼 가이샤 | 반도체장치의제조방법 |
| US5667940A (en) | 1994-05-11 | 1997-09-16 | United Microelectronics Corporation | Process for creating high density integrated circuits utilizing double coating photoresist mask |
| DE4445427C2 (de) | 1994-12-20 | 1997-04-30 | Schott Glaswerke | Plasma-CVD-Verfahren zur Herstellung einer Gradientenschicht |
| US5541130A (en) | 1995-06-07 | 1996-07-30 | International Business Machines Corporation | Process for making and programming a flash memory array |
| KR19980021248A (ko) * | 1996-09-14 | 1998-06-25 | 김광호 | 반도체소자 미세패턴 형성방법 |
| US6191034B1 (en) * | 1997-05-30 | 2001-02-20 | Advanced Micro Devices | Forming minimal size spaces in integrated circuit conductive lines |
| US6180465B1 (en) * | 1998-11-20 | 2001-01-30 | Advanced Micro Devices | Method of making high performance MOSFET with channel scaling mask feature |
| US6274445B1 (en) * | 1999-02-03 | 2001-08-14 | Philips Semi-Conductor, Inc. | Method of manufacturing shallow source/drain junctions in a salicide process |
-
1999
- 1999-05-26 US US09/320,417 patent/US6329124B1/en not_active Expired - Lifetime
-
2000
- 2000-03-13 EP EP00917905A patent/EP1181714A1/en not_active Ceased
- 2000-03-13 JP JP2001500325A patent/JP2003501800A/ja active Pending
- 2000-03-13 WO PCT/US2000/006585 patent/WO2000074121A1/en not_active Ceased
- 2000-03-13 KR KR1020017014946A patent/KR100682638B1/ko not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62150826A (ja) * | 1985-12-25 | 1987-07-04 | Toshiba Corp | 半導体装置の製造方法 |
| JPH04207076A (ja) * | 1990-11-30 | 1992-07-29 | Toshiba Corp | 固体撮像装置の製造方法 |
| JPH04291758A (ja) * | 1990-12-10 | 1992-10-15 | Samsung Electron Co Ltd | マスクプグラム方式の読出し専用メモリー装置の製造方法 |
| JPH06232095A (ja) * | 1993-01-29 | 1994-08-19 | Sony Corp | パターンの形成方法 |
| JPH0786244A (ja) * | 1993-09-13 | 1995-03-31 | Sony Corp | ドライエッチング方法 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014112655A (ja) * | 2012-10-30 | 2014-06-19 | Dainippon Printing Co Ltd | ナノインプリントモールドおよびその製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100682638B1 (ko) | 2007-02-15 |
| US6329124B1 (en) | 2001-12-11 |
| EP1181714A1 (en) | 2002-02-27 |
| WO2000074121A1 (en) | 2000-12-07 |
| KR20010113838A (ko) | 2001-12-28 |
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