JP2003297994A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

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Publication number
JP2003297994A
JP2003297994A JP2002093625A JP2002093625A JP2003297994A JP 2003297994 A JP2003297994 A JP 2003297994A JP 2002093625 A JP2002093625 A JP 2002093625A JP 2002093625 A JP2002093625 A JP 2002093625A JP 2003297994 A JP2003297994 A JP 2003297994A
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Japan
Prior art keywords
tab
semiconductor
semiconductor device
chip
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002093625A
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English (en)
Japanese (ja)
Other versions
JP2003297994A5 (enExample
Inventor
Taika Arai
大夏 新井
Fujiaki Nose
藤明 野瀬
Hiroshi Kikuchi
広 菊地
Yoichi Tamaoki
洋一 玉置
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2002093625A priority Critical patent/JP2003297994A/ja
Priority to US10/396,360 priority patent/US6876067B2/en
Publication of JP2003297994A publication Critical patent/JP2003297994A/ja
Publication of JP2003297994A5 publication Critical patent/JP2003297994A5/ja
Pending legal-status Critical Current

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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2002093625A 2002-03-29 2002-03-29 半導体装置およびその製造方法 Pending JP2003297994A (ja)

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Cited By (2)

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JP2012060105A (ja) * 2010-08-09 2012-03-22 Renesas Electronics Corp 半導体装置、半導体装置の製造方法、金型、および封止装置
JP2017028131A (ja) * 2015-07-23 2017-02-02 株式会社デンソー パッケージ実装体

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JPH08222710A (ja) * 1995-02-17 1996-08-30 Mitsubishi Electric Corp 半導体装置
EP1406300B1 (en) * 2001-07-09 2012-02-22 Sumitomo Metal Mining Company Limited Method of manufacturing a lead frame
JP3810411B2 (ja) * 2004-01-23 2006-08-16 Necエレクトロニクス株式会社 集積回路装置
JP4541717B2 (ja) * 2004-02-09 2010-09-08 ルネサスエレクトロニクス株式会社 集積回路装置及びその製造方法
US8008142B2 (en) 2009-03-13 2011-08-30 International Business Machines Corporation Self-aligned Schottky diode
CN111354695B (zh) * 2020-03-11 2022-11-15 珠海格力电器股份有限公司 封装结构及其制造方法
US12021038B2 (en) 2021-06-11 2024-06-25 Macom Technology Solutions Holdings, Inc. Solderable and wire bondable part marking

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US5041902A (en) * 1989-12-14 1991-08-20 Motorola, Inc. Molded electronic package with compression structures
JP3252569B2 (ja) * 1993-11-09 2002-02-04 株式会社デンソー 絶縁分離基板及びそれを用いた半導体装置及びその製造方法
JPH07335811A (ja) 1994-06-10 1995-12-22 Nippondenso Co Ltd 半導体装置
JPH11284119A (ja) 1998-03-27 1999-10-15 Mitsumi Electric Co Ltd 半導体集積デバイスの放熱構造
US6139977A (en) * 1998-06-10 2000-10-31 Lucent Technologies Inc. Palladium surface coating suitable for wirebonding and process for forming palladium surface coatings
US6429512B1 (en) * 1999-03-16 2002-08-06 Siliconware Precision Industries Co., Ltd. Ball grid array integrated circuit package with palladium coated heat-dissipation device
US6198163B1 (en) * 1999-10-18 2001-03-06 Amkor Technology, Inc. Thin leadframe-type semiconductor package having heat sink with recess and exposed surface
US6512244B1 (en) * 2001-05-07 2003-01-28 Advanced Micro Devices, Inc. SOI device with structure for enhancing carrier recombination and method of fabricating same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012060105A (ja) * 2010-08-09 2012-03-22 Renesas Electronics Corp 半導体装置、半導体装置の製造方法、金型、および封止装置
JP2017028131A (ja) * 2015-07-23 2017-02-02 株式会社デンソー パッケージ実装体

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