JP2003228989A - メモリアレイにデータビットを書き込むための方法 - Google Patents

メモリアレイにデータビットを書き込むための方法

Info

Publication number
JP2003228989A
JP2003228989A JP2003009048A JP2003009048A JP2003228989A JP 2003228989 A JP2003228989 A JP 2003228989A JP 2003009048 A JP2003009048 A JP 2003009048A JP 2003009048 A JP2003009048 A JP 2003009048A JP 2003228989 A JP2003228989 A JP 2003228989A
Authority
JP
Japan
Prior art keywords
memory
bit
data
input
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003009048A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003228989A5 (enExample
Inventor
Michael Christian Fischer
マイケル・クリスチャン・フィッシャー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2003228989A publication Critical patent/JP2003228989A/ja
Publication of JP2003228989A5 publication Critical patent/JP2003228989A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/06—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using diode elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Landscapes

  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
JP2003009048A 2002-01-18 2003-01-17 メモリアレイにデータビットを書き込むための方法 Pending JP2003228989A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/053995 2002-01-18
US10/053,995 US6687168B2 (en) 2002-01-18 2002-01-18 Method for writing data bits to a memory array

Publications (2)

Publication Number Publication Date
JP2003228989A true JP2003228989A (ja) 2003-08-15
JP2003228989A5 JP2003228989A5 (enExample) 2005-05-12

Family

ID=21987996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003009048A Pending JP2003228989A (ja) 2002-01-18 2003-01-17 メモリアレイにデータビットを書き込むための方法

Country Status (6)

Country Link
US (2) US6687168B2 (enExample)
EP (1) EP1329902A1 (enExample)
JP (1) JP2003228989A (enExample)
KR (1) KR20030063186A (enExample)
CN (1) CN1433019A (enExample)
TW (1) TWI266333B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6856627B2 (en) * 1999-01-15 2005-02-15 Cisco Technology, Inc. Method for routing information over a network
US6687168B2 (en) * 2002-01-18 2004-02-03 Hewlett-Packard Development Company, L.P. Method for writing data bits to a memory array
US7800932B2 (en) * 2005-09-28 2010-09-21 Sandisk 3D Llc Memory cell comprising switchable semiconductor memory element with trimmable resistance
US7106639B2 (en) * 2004-09-01 2006-09-12 Hewlett-Packard Development Company, L.P. Defect management enabled PIRM and method
US7450414B2 (en) * 2006-07-31 2008-11-11 Sandisk 3D Llc Method for using a mixed-use memory array
US20080025069A1 (en) * 2006-07-31 2008-01-31 Scheuerlein Roy E Mixed-use memory array with different data states
US7486537B2 (en) * 2006-07-31 2009-02-03 Sandisk 3D Llc Method for using a mixed-use memory array with different data states
TWI426384B (zh) * 2009-09-10 2014-02-11 Robustflash Technologies Ltd 資料寫入方法與系統

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173873A (en) 1990-06-28 1992-12-22 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration High speed magneto-resistive random access memory
FR2713398B1 (fr) 1993-11-30 1996-01-19 Sgs Thomson Microelectronics Fusible pour circuit intégré.
JP3560266B2 (ja) * 1995-08-31 2004-09-02 株式会社ルネサステクノロジ 半導体装置及び半導体データ装置
US5748519A (en) 1996-12-13 1998-05-05 Motorola, Inc. Method of selecting a memory cell in a magnetic random access memory device
WO2000026920A1 (fr) * 1998-10-29 2000-05-11 Hitachi, Ltd. Dispositif de circuit integre semi-conducteur
JP3800925B2 (ja) 2000-05-15 2006-07-26 日本電気株式会社 磁気ランダムアクセスメモリ回路
DE60111953T2 (de) * 2000-10-30 2006-04-20 Whiteley, Bruce Alan Fluidmischer mit drehbarem auslassrohr und dosieröffnungen
US6687168B2 (en) * 2002-01-18 2004-02-03 Hewlett-Packard Development Company, L.P. Method for writing data bits to a memory array
JP3808802B2 (ja) * 2002-06-20 2006-08-16 株式会社東芝 磁気ランダムアクセスメモリ

Also Published As

Publication number Publication date
US20030137891A1 (en) 2003-07-24
CN1433019A (zh) 2003-07-30
US6856570B2 (en) 2005-02-15
TWI266333B (en) 2006-11-11
KR20030063186A (ko) 2003-07-28
US6687168B2 (en) 2004-02-03
EP1329902A1 (en) 2003-07-23
US20040218412A1 (en) 2004-11-04
TW200302488A (en) 2003-08-01

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