TWI266333B - Method for writing data bits to a memory array - Google Patents

Method for writing data bits to a memory array

Info

Publication number
TWI266333B
TWI266333B TW091134353A TW91134353A TWI266333B TW I266333 B TWI266333 B TW I266333B TW 091134353 A TW091134353 A TW 091134353A TW 91134353 A TW91134353 A TW 91134353A TW I266333 B TWI266333 B TW I266333B
Authority
TW
Taiwan
Prior art keywords
memory array
data bits
writing data
causes
addressed bit
Prior art date
Application number
TW091134353A
Other languages
English (en)
Other versions
TW200302488A (en
Inventor
Michael Christian Fischer
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of TW200302488A publication Critical patent/TW200302488A/zh
Application granted granted Critical
Publication of TWI266333B publication Critical patent/TWI266333B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/06—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using diode elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Landscapes

  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
TW091134353A 2002-01-18 2002-11-26 Method for writing data bits to a memory array TWI266333B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/053,995 US6687168B2 (en) 2002-01-18 2002-01-18 Method for writing data bits to a memory array

Publications (2)

Publication Number Publication Date
TW200302488A TW200302488A (en) 2003-08-01
TWI266333B true TWI266333B (en) 2006-11-11

Family

ID=21987996

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091134353A TWI266333B (en) 2002-01-18 2002-11-26 Method for writing data bits to a memory array

Country Status (6)

Country Link
US (2) US6687168B2 (zh)
EP (1) EP1329902A1 (zh)
JP (1) JP2003228989A (zh)
KR (1) KR20030063186A (zh)
CN (1) CN1433019A (zh)
TW (1) TWI266333B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI426384B (zh) * 2009-09-10 2014-02-11 Robustflash Technologies Ltd 資料寫入方法與系統

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6856627B2 (en) * 1999-01-15 2005-02-15 Cisco Technology, Inc. Method for routing information over a network
US6687168B2 (en) * 2002-01-18 2004-02-03 Hewlett-Packard Development Company, L.P. Method for writing data bits to a memory array
US7800932B2 (en) * 2005-09-28 2010-09-21 Sandisk 3D Llc Memory cell comprising switchable semiconductor memory element with trimmable resistance
US7106639B2 (en) * 2004-09-01 2006-09-12 Hewlett-Packard Development Company, L.P. Defect management enabled PIRM and method
US7450414B2 (en) * 2006-07-31 2008-11-11 Sandisk 3D Llc Method for using a mixed-use memory array
US7486537B2 (en) * 2006-07-31 2009-02-03 Sandisk 3D Llc Method for using a mixed-use memory array with different data states
US20080025069A1 (en) * 2006-07-31 2008-01-31 Scheuerlein Roy E Mixed-use memory array with different data states

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173873A (en) 1990-06-28 1992-12-22 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration High speed magneto-resistive random access memory
FR2713398B1 (fr) 1993-11-30 1996-01-19 Sgs Thomson Microelectronics Fusible pour circuit intégré.
JP3560266B2 (ja) * 1995-08-31 2004-09-02 株式会社ルネサステクノロジ 半導体装置及び半導体データ装置
US5748519A (en) 1996-12-13 1998-05-05 Motorola, Inc. Method of selecting a memory cell in a magnetic random access memory device
US6452851B1 (en) * 1998-10-29 2002-09-17 Hitachi, Ltd. Semiconductor integrated circuit device
JP3800925B2 (ja) 2000-05-15 2006-07-26 日本電気株式会社 磁気ランダムアクセスメモリ回路
US6877890B2 (en) * 2000-10-30 2005-04-12 Bruce Alan Whiteley Fluid mixer with rotatable educator tube and metering orifices
US6687168B2 (en) * 2002-01-18 2004-02-03 Hewlett-Packard Development Company, L.P. Method for writing data bits to a memory array
JP3808802B2 (ja) * 2002-06-20 2006-08-16 株式会社東芝 磁気ランダムアクセスメモリ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI426384B (zh) * 2009-09-10 2014-02-11 Robustflash Technologies Ltd 資料寫入方法與系統

Also Published As

Publication number Publication date
US20040218412A1 (en) 2004-11-04
US20030137891A1 (en) 2003-07-24
EP1329902A1 (en) 2003-07-23
JP2003228989A (ja) 2003-08-15
KR20030063186A (ko) 2003-07-28
US6687168B2 (en) 2004-02-03
TW200302488A (en) 2003-08-01
CN1433019A (zh) 2003-07-30
US6856570B2 (en) 2005-02-15

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Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent