JP2003224228A - 半導体装置用パッケージ並びに半導体装置及びその製造方法 - Google Patents

半導体装置用パッケージ並びに半導体装置及びその製造方法

Info

Publication number
JP2003224228A
JP2003224228A JP2002023106A JP2002023106A JP2003224228A JP 2003224228 A JP2003224228 A JP 2003224228A JP 2002023106 A JP2002023106 A JP 2002023106A JP 2002023106 A JP2002023106 A JP 2002023106A JP 2003224228 A JP2003224228 A JP 2003224228A
Authority
JP
Japan
Prior art keywords
conductor pattern
semiconductor element
forming layer
semiconductor device
pattern forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002023106A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003224228A5 (enExample
Inventor
Seiki Shimada
清貴 島田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2002023106A priority Critical patent/JP2003224228A/ja
Publication of JP2003224228A publication Critical patent/JP2003224228A/ja
Publication of JP2003224228A5 publication Critical patent/JP2003224228A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2002023106A 2002-01-31 2002-01-31 半導体装置用パッケージ並びに半導体装置及びその製造方法 Pending JP2003224228A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002023106A JP2003224228A (ja) 2002-01-31 2002-01-31 半導体装置用パッケージ並びに半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002023106A JP2003224228A (ja) 2002-01-31 2002-01-31 半導体装置用パッケージ並びに半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2003224228A true JP2003224228A (ja) 2003-08-08
JP2003224228A5 JP2003224228A5 (enExample) 2005-06-16

Family

ID=27745908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002023106A Pending JP2003224228A (ja) 2002-01-31 2002-01-31 半導体装置用パッケージ並びに半導体装置及びその製造方法

Country Status (1)

Country Link
JP (1) JP2003224228A (enExample)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6870249B2 (en) 2002-12-24 2005-03-22 Oki Electric Industry Co., Ltd. Semiconductor device and manufacturing method thereof
JP2005340578A (ja) * 2004-05-28 2005-12-08 Sanyo Electric Co Ltd 回路装置
JP2008103615A (ja) * 2006-10-20 2008-05-01 Shinko Electric Ind Co Ltd 電子部品搭載多層配線基板及びその製造方法
CN100472776C (zh) * 2005-05-27 2009-03-25 环隆电气股份有限公司 小型化无线通讯模块及其制造方法
KR100907639B1 (ko) * 2007-12-20 2009-07-14 삼성전기주식회사 다층 인쇄회로기판의 제조방법 및 그것을 이용한 반도체플라스틱 패키지
JP2011187919A (ja) * 2010-03-05 2011-09-22 Samsung Electro-Mechanics Co Ltd 電子素子内蔵型印刷回路基板及びその製造方法
JP2015026777A (ja) * 2013-07-29 2015-02-05 富士通株式会社 電子部品
KR101517541B1 (ko) * 2006-12-07 2015-05-04 스태츠 칩팩 아이엔씨. 다층 반도체 패키지

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6870249B2 (en) 2002-12-24 2005-03-22 Oki Electric Industry Co., Ltd. Semiconductor device and manufacturing method thereof
JP2005340578A (ja) * 2004-05-28 2005-12-08 Sanyo Electric Co Ltd 回路装置
CN100472776C (zh) * 2005-05-27 2009-03-25 环隆电气股份有限公司 小型化无线通讯模块及其制造方法
JP2008103615A (ja) * 2006-10-20 2008-05-01 Shinko Electric Ind Co Ltd 電子部品搭載多層配線基板及びその製造方法
US8222747B2 (en) 2006-10-20 2012-07-17 Shinko Electric Industries Co., Ltd. Multilayer wiring substrate mounted with electronic component and method for manufacturing the same
KR101517541B1 (ko) * 2006-12-07 2015-05-04 스태츠 칩팩 아이엔씨. 다층 반도체 패키지
KR100907639B1 (ko) * 2007-12-20 2009-07-14 삼성전기주식회사 다층 인쇄회로기판의 제조방법 및 그것을 이용한 반도체플라스틱 패키지
JP2011187919A (ja) * 2010-03-05 2011-09-22 Samsung Electro-Mechanics Co Ltd 電子素子内蔵型印刷回路基板及びその製造方法
JP2015026777A (ja) * 2013-07-29 2015-02-05 富士通株式会社 電子部品

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